13e086edfSolivier moysan /* 23e086edfSolivier moysan * STM32 ALSA SoC Digital Audio Interface (SAI) driver. 33e086edfSolivier moysan * 43e086edfSolivier moysan * Copyright (C) 2016, STMicroelectronics - All Rights Reserved 53e086edfSolivier moysan * Author(s): Olivier Moysan <olivier.moysan@st.com> for STMicroelectronics. 63e086edfSolivier moysan * 73e086edfSolivier moysan * License terms: GPL V2.0. 83e086edfSolivier moysan * 93e086edfSolivier moysan * This program is free software; you can redistribute it and/or modify it 103e086edfSolivier moysan * under the terms of the GNU General Public License version 2 as published by 113e086edfSolivier moysan * the Free Software Foundation. 123e086edfSolivier moysan * 133e086edfSolivier moysan * This program is distributed in the hope that it will be useful, but 143e086edfSolivier moysan * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 153e086edfSolivier moysan * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more 163e086edfSolivier moysan * details. 173e086edfSolivier moysan */ 183e086edfSolivier moysan 193e086edfSolivier moysan #include <linux/clk.h> 208307b2afSOlivier Moysan #include <linux/clk-provider.h> 213e086edfSolivier moysan #include <linux/kernel.h> 223e086edfSolivier moysan #include <linux/module.h> 233e086edfSolivier moysan #include <linux/of_irq.h> 243e086edfSolivier moysan #include <linux/of_platform.h> 253e086edfSolivier moysan #include <linux/regmap.h> 263e086edfSolivier moysan 276eb17d70SOlivier Moysan #include <sound/asoundef.h> 283e086edfSolivier moysan #include <sound/core.h> 293e086edfSolivier moysan #include <sound/dmaengine_pcm.h> 303e086edfSolivier moysan #include <sound/pcm_params.h> 313e086edfSolivier moysan 323e086edfSolivier moysan #include "stm32_sai.h" 333e086edfSolivier moysan 343e086edfSolivier moysan #define SAI_FREE_PROTOCOL 0x0 356eb17d70SOlivier Moysan #define SAI_SPDIF_PROTOCOL 0x1 363e086edfSolivier moysan 373e086edfSolivier moysan #define SAI_SLOT_SIZE_AUTO 0x0 383e086edfSolivier moysan #define SAI_SLOT_SIZE_16 0x1 393e086edfSolivier moysan #define SAI_SLOT_SIZE_32 0x2 403e086edfSolivier moysan 413e086edfSolivier moysan #define SAI_DATASIZE_8 0x2 423e086edfSolivier moysan #define SAI_DATASIZE_10 0x3 433e086edfSolivier moysan #define SAI_DATASIZE_16 0x4 443e086edfSolivier moysan #define SAI_DATASIZE_20 0x5 453e086edfSolivier moysan #define SAI_DATASIZE_24 0x6 463e086edfSolivier moysan #define SAI_DATASIZE_32 0x7 473e086edfSolivier moysan 483e086edfSolivier moysan #define STM_SAI_FIFO_SIZE 8 493e086edfSolivier moysan #define STM_SAI_DAI_NAME_SIZE 15 503e086edfSolivier moysan 513e086edfSolivier moysan #define STM_SAI_IS_PLAYBACK(ip) ((ip)->dir == SNDRV_PCM_STREAM_PLAYBACK) 523e086edfSolivier moysan #define STM_SAI_IS_CAPTURE(ip) ((ip)->dir == SNDRV_PCM_STREAM_CAPTURE) 533e086edfSolivier moysan 543e086edfSolivier moysan #define STM_SAI_A_ID 0x0 553e086edfSolivier moysan #define STM_SAI_B_ID 0x1 563e086edfSolivier moysan 5703e78a24Solivier moysan #define STM_SAI_IS_SUB_A(x) ((x)->id == STM_SAI_A_ID) 5803e78a24Solivier moysan #define STM_SAI_IS_SUB_B(x) ((x)->id == STM_SAI_B_ID) 593e086edfSolivier moysan #define STM_SAI_BLOCK_NAME(x) (((x)->id == STM_SAI_A_ID) ? "A" : "B") 603e086edfSolivier moysan 615914d285SOlivier Moysan #define SAI_SYNC_NONE 0x0 625914d285SOlivier Moysan #define SAI_SYNC_INTERNAL 0x1 635914d285SOlivier Moysan #define SAI_SYNC_EXTERNAL 0x2 645914d285SOlivier Moysan 656eb17d70SOlivier Moysan #define STM_SAI_PROTOCOL_IS_SPDIF(ip) ((ip)->spdif) 666eb17d70SOlivier Moysan #define STM_SAI_HAS_SPDIF(x) ((x)->pdata->conf->has_spdif) 675914d285SOlivier Moysan #define STM_SAI_HAS_EXT_SYNC(x) (!STM_SAI_IS_F4(sai->pdata)) 685914d285SOlivier Moysan 696eb17d70SOlivier Moysan #define SAI_IEC60958_BLOCK_FRAMES 192 706eb17d70SOlivier Moysan #define SAI_IEC60958_STATUS_BYTES 24 716eb17d70SOlivier Moysan 728307b2afSOlivier Moysan #define SAI_MCLK_NAME_LEN 32 738307b2afSOlivier Moysan 743e086edfSolivier moysan /** 753e086edfSolivier moysan * struct stm32_sai_sub_data - private data of SAI sub block (block A or B) 763e086edfSolivier moysan * @pdev: device data pointer 773e086edfSolivier moysan * @regmap: SAI register map pointer 7803e78a24Solivier moysan * @regmap_config: SAI sub block register map configuration pointer 793e086edfSolivier moysan * @dma_params: dma configuration data for rx or tx channel 803e086edfSolivier moysan * @cpu_dai_drv: DAI driver data pointer 813e086edfSolivier moysan * @cpu_dai: DAI runtime data pointer 823e086edfSolivier moysan * @substream: PCM substream data pointer 833e086edfSolivier moysan * @pdata: SAI block parent data pointer 845914d285SOlivier Moysan * @np_sync_provider: synchronization provider node 853e086edfSolivier moysan * @sai_ck: kernel clock feeding the SAI clock generator 868307b2afSOlivier Moysan * @sai_mclk: master clock from SAI mclk provider 873e086edfSolivier moysan * @phys_addr: SAI registers physical base address 883e086edfSolivier moysan * @mclk_rate: SAI block master clock frequency (Hz). set at init 893e086edfSolivier moysan * @id: SAI sub block id corresponding to sub-block A or B 903e086edfSolivier moysan * @dir: SAI block direction (playback or capture). set at init 913e086edfSolivier moysan * @master: SAI block mode flag. (true=master, false=slave) set at init 926eb17d70SOlivier Moysan * @spdif: SAI S/PDIF iec60958 mode flag. set at init 933e086edfSolivier moysan * @fmt: SAI block format. relevant only for custom protocols. set at init 943e086edfSolivier moysan * @sync: SAI block synchronization mode. (none, internal or external) 955914d285SOlivier Moysan * @synco: SAI block ext sync source (provider setting). (none, sub-block A/B) 965914d285SOlivier Moysan * @synci: SAI block ext sync source (client setting). (SAI sync provider index) 973e086edfSolivier moysan * @fs_length: frame synchronization length. depends on protocol settings 983e086edfSolivier moysan * @slots: rx or tx slot number 993e086edfSolivier moysan * @slot_width: rx or tx slot width in bits 1003e086edfSolivier moysan * @slot_mask: rx or tx active slots mask. set at init or at runtime 1013e086edfSolivier moysan * @data_size: PCM data width. corresponds to PCM substream width. 1026eb17d70SOlivier Moysan * @spdif_frm_cnt: S/PDIF playback frame counter 1035f8a1000SOlivier Moysan * @iec958: iec958 data 104187e01d0Solivier moysan * @ctrl_lock: control lock 1053e086edfSolivier moysan */ 1063e086edfSolivier moysan struct stm32_sai_sub_data { 1073e086edfSolivier moysan struct platform_device *pdev; 1083e086edfSolivier moysan struct regmap *regmap; 10903e78a24Solivier moysan const struct regmap_config *regmap_config; 1103e086edfSolivier moysan struct snd_dmaengine_dai_dma_data dma_params; 1113e086edfSolivier moysan struct snd_soc_dai_driver *cpu_dai_drv; 1123e086edfSolivier moysan struct snd_soc_dai *cpu_dai; 1133e086edfSolivier moysan struct snd_pcm_substream *substream; 1143e086edfSolivier moysan struct stm32_sai_data *pdata; 1155914d285SOlivier Moysan struct device_node *np_sync_provider; 1163e086edfSolivier moysan struct clk *sai_ck; 1178307b2afSOlivier Moysan struct clk *sai_mclk; 1183e086edfSolivier moysan dma_addr_t phys_addr; 1193e086edfSolivier moysan unsigned int mclk_rate; 1203e086edfSolivier moysan unsigned int id; 1213e086edfSolivier moysan int dir; 1223e086edfSolivier moysan bool master; 1236eb17d70SOlivier Moysan bool spdif; 1243e086edfSolivier moysan int fmt; 1253e086edfSolivier moysan int sync; 1265914d285SOlivier Moysan int synco; 1275914d285SOlivier Moysan int synci; 1283e086edfSolivier moysan int fs_length; 1293e086edfSolivier moysan int slots; 1303e086edfSolivier moysan int slot_width; 1313e086edfSolivier moysan int slot_mask; 1323e086edfSolivier moysan int data_size; 1336eb17d70SOlivier Moysan unsigned int spdif_frm_cnt; 134187e01d0Solivier moysan struct snd_aes_iec958 iec958; 135187e01d0Solivier moysan struct mutex ctrl_lock; /* protect resources accessed by controls */ 1363e086edfSolivier moysan }; 1373e086edfSolivier moysan 1383e086edfSolivier moysan enum stm32_sai_fifo_th { 1393e086edfSolivier moysan STM_SAI_FIFO_TH_EMPTY, 1403e086edfSolivier moysan STM_SAI_FIFO_TH_QUARTER, 1413e086edfSolivier moysan STM_SAI_FIFO_TH_HALF, 1423e086edfSolivier moysan STM_SAI_FIFO_TH_3_QUARTER, 1433e086edfSolivier moysan STM_SAI_FIFO_TH_FULL, 1443e086edfSolivier moysan }; 1453e086edfSolivier moysan 1463e086edfSolivier moysan static bool stm32_sai_sub_readable_reg(struct device *dev, unsigned int reg) 1473e086edfSolivier moysan { 1483e086edfSolivier moysan switch (reg) { 1493e086edfSolivier moysan case STM_SAI_CR1_REGX: 1503e086edfSolivier moysan case STM_SAI_CR2_REGX: 1513e086edfSolivier moysan case STM_SAI_FRCR_REGX: 1523e086edfSolivier moysan case STM_SAI_SLOTR_REGX: 1533e086edfSolivier moysan case STM_SAI_IMR_REGX: 1543e086edfSolivier moysan case STM_SAI_SR_REGX: 1553e086edfSolivier moysan case STM_SAI_CLRFR_REGX: 1563e086edfSolivier moysan case STM_SAI_DR_REGX: 15703e78a24Solivier moysan case STM_SAI_PDMCR_REGX: 15803e78a24Solivier moysan case STM_SAI_PDMLY_REGX: 1593e086edfSolivier moysan return true; 1603e086edfSolivier moysan default: 1613e086edfSolivier moysan return false; 1623e086edfSolivier moysan } 1633e086edfSolivier moysan } 1643e086edfSolivier moysan 1653e086edfSolivier moysan static bool stm32_sai_sub_volatile_reg(struct device *dev, unsigned int reg) 1663e086edfSolivier moysan { 1673e086edfSolivier moysan switch (reg) { 1683e086edfSolivier moysan case STM_SAI_DR_REGX: 1693e086edfSolivier moysan return true; 1703e086edfSolivier moysan default: 1713e086edfSolivier moysan return false; 1723e086edfSolivier moysan } 1733e086edfSolivier moysan } 1743e086edfSolivier moysan 1753e086edfSolivier moysan static bool stm32_sai_sub_writeable_reg(struct device *dev, unsigned int reg) 1763e086edfSolivier moysan { 1773e086edfSolivier moysan switch (reg) { 1783e086edfSolivier moysan case STM_SAI_CR1_REGX: 1793e086edfSolivier moysan case STM_SAI_CR2_REGX: 1803e086edfSolivier moysan case STM_SAI_FRCR_REGX: 1813e086edfSolivier moysan case STM_SAI_SLOTR_REGX: 1823e086edfSolivier moysan case STM_SAI_IMR_REGX: 1833e086edfSolivier moysan case STM_SAI_SR_REGX: 1843e086edfSolivier moysan case STM_SAI_CLRFR_REGX: 1853e086edfSolivier moysan case STM_SAI_DR_REGX: 18603e78a24Solivier moysan case STM_SAI_PDMCR_REGX: 18703e78a24Solivier moysan case STM_SAI_PDMLY_REGX: 1883e086edfSolivier moysan return true; 1893e086edfSolivier moysan default: 1903e086edfSolivier moysan return false; 1913e086edfSolivier moysan } 1923e086edfSolivier moysan } 1933e086edfSolivier moysan 19403e78a24Solivier moysan static const struct regmap_config stm32_sai_sub_regmap_config_f4 = { 1953e086edfSolivier moysan .reg_bits = 32, 1963e086edfSolivier moysan .reg_stride = 4, 1973e086edfSolivier moysan .val_bits = 32, 1983e086edfSolivier moysan .max_register = STM_SAI_DR_REGX, 1993e086edfSolivier moysan .readable_reg = stm32_sai_sub_readable_reg, 2003e086edfSolivier moysan .volatile_reg = stm32_sai_sub_volatile_reg, 2013e086edfSolivier moysan .writeable_reg = stm32_sai_sub_writeable_reg, 2023e086edfSolivier moysan .fast_io = true, 2033e086edfSolivier moysan }; 2043e086edfSolivier moysan 20503e78a24Solivier moysan static const struct regmap_config stm32_sai_sub_regmap_config_h7 = { 20603e78a24Solivier moysan .reg_bits = 32, 20703e78a24Solivier moysan .reg_stride = 4, 20803e78a24Solivier moysan .val_bits = 32, 20903e78a24Solivier moysan .max_register = STM_SAI_PDMLY_REGX, 21003e78a24Solivier moysan .readable_reg = stm32_sai_sub_readable_reg, 21103e78a24Solivier moysan .volatile_reg = stm32_sai_sub_volatile_reg, 21203e78a24Solivier moysan .writeable_reg = stm32_sai_sub_writeable_reg, 21303e78a24Solivier moysan .fast_io = true, 21403e78a24Solivier moysan }; 21503e78a24Solivier moysan 216187e01d0Solivier moysan static int snd_pcm_iec958_info(struct snd_kcontrol *kcontrol, 217187e01d0Solivier moysan struct snd_ctl_elem_info *uinfo) 218187e01d0Solivier moysan { 219187e01d0Solivier moysan uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 220187e01d0Solivier moysan uinfo->count = 1; 221187e01d0Solivier moysan 222187e01d0Solivier moysan return 0; 223187e01d0Solivier moysan } 224187e01d0Solivier moysan 225187e01d0Solivier moysan static int snd_pcm_iec958_get(struct snd_kcontrol *kcontrol, 226187e01d0Solivier moysan struct snd_ctl_elem_value *uctl) 227187e01d0Solivier moysan { 228187e01d0Solivier moysan struct stm32_sai_sub_data *sai = snd_kcontrol_chip(kcontrol); 229187e01d0Solivier moysan 230187e01d0Solivier moysan mutex_lock(&sai->ctrl_lock); 231187e01d0Solivier moysan memcpy(uctl->value.iec958.status, sai->iec958.status, 4); 232187e01d0Solivier moysan mutex_unlock(&sai->ctrl_lock); 233187e01d0Solivier moysan 234187e01d0Solivier moysan return 0; 235187e01d0Solivier moysan } 236187e01d0Solivier moysan 237187e01d0Solivier moysan static int snd_pcm_iec958_put(struct snd_kcontrol *kcontrol, 238187e01d0Solivier moysan struct snd_ctl_elem_value *uctl) 239187e01d0Solivier moysan { 240187e01d0Solivier moysan struct stm32_sai_sub_data *sai = snd_kcontrol_chip(kcontrol); 241187e01d0Solivier moysan 242187e01d0Solivier moysan mutex_lock(&sai->ctrl_lock); 243187e01d0Solivier moysan memcpy(sai->iec958.status, uctl->value.iec958.status, 4); 244187e01d0Solivier moysan mutex_unlock(&sai->ctrl_lock); 245187e01d0Solivier moysan 246187e01d0Solivier moysan return 0; 247187e01d0Solivier moysan } 248187e01d0Solivier moysan 249187e01d0Solivier moysan static const struct snd_kcontrol_new iec958_ctls = { 250187e01d0Solivier moysan .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE | 251187e01d0Solivier moysan SNDRV_CTL_ELEM_ACCESS_VOLATILE), 252187e01d0Solivier moysan .iface = SNDRV_CTL_ELEM_IFACE_PCM, 253187e01d0Solivier moysan .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT), 254187e01d0Solivier moysan .info = snd_pcm_iec958_info, 255187e01d0Solivier moysan .get = snd_pcm_iec958_get, 256187e01d0Solivier moysan .put = snd_pcm_iec958_put, 257187e01d0Solivier moysan }; 258187e01d0Solivier moysan 2598307b2afSOlivier Moysan struct stm32_sai_mclk_data { 2608307b2afSOlivier Moysan struct clk_hw hw; 2618307b2afSOlivier Moysan unsigned long freq; 2628307b2afSOlivier Moysan struct stm32_sai_sub_data *sai_data; 2638307b2afSOlivier Moysan }; 2648307b2afSOlivier Moysan 2658307b2afSOlivier Moysan #define to_mclk_data(_hw) container_of(_hw, struct stm32_sai_mclk_data, hw) 2668307b2afSOlivier Moysan #define STM32_SAI_MAX_CLKS 1 2678307b2afSOlivier Moysan 2688307b2afSOlivier Moysan static int stm32_sai_get_clk_div(struct stm32_sai_sub_data *sai, 2698307b2afSOlivier Moysan unsigned long input_rate, 2708307b2afSOlivier Moysan unsigned long output_rate) 2718307b2afSOlivier Moysan { 2728307b2afSOlivier Moysan int version = sai->pdata->conf->version; 2738307b2afSOlivier Moysan int div; 2748307b2afSOlivier Moysan 2758307b2afSOlivier Moysan div = DIV_ROUND_CLOSEST(input_rate, output_rate); 2768307b2afSOlivier Moysan if (div > SAI_XCR1_MCKDIV_MAX(version)) { 2778307b2afSOlivier Moysan dev_err(&sai->pdev->dev, "Divider %d out of range\n", div); 2788307b2afSOlivier Moysan return -EINVAL; 2798307b2afSOlivier Moysan } 2808307b2afSOlivier Moysan dev_dbg(&sai->pdev->dev, "SAI divider %d\n", div); 2818307b2afSOlivier Moysan 2828307b2afSOlivier Moysan if (input_rate % div) 2838307b2afSOlivier Moysan dev_dbg(&sai->pdev->dev, 2848307b2afSOlivier Moysan "Rate not accurate. requested (%ld), actual (%ld)\n", 2858307b2afSOlivier Moysan output_rate, input_rate / div); 2868307b2afSOlivier Moysan 2878307b2afSOlivier Moysan return div; 2888307b2afSOlivier Moysan } 2898307b2afSOlivier Moysan 2908307b2afSOlivier Moysan static int stm32_sai_set_clk_div(struct stm32_sai_sub_data *sai, 2918307b2afSOlivier Moysan unsigned int div) 2928307b2afSOlivier Moysan { 2938307b2afSOlivier Moysan int version = sai->pdata->conf->version; 2948307b2afSOlivier Moysan int ret, cr1, mask; 2958307b2afSOlivier Moysan 2968307b2afSOlivier Moysan if (div > SAI_XCR1_MCKDIV_MAX(version)) { 2978307b2afSOlivier Moysan dev_err(&sai->pdev->dev, "Divider %d out of range\n", div); 2988307b2afSOlivier Moysan return -EINVAL; 2998307b2afSOlivier Moysan } 3008307b2afSOlivier Moysan 3018307b2afSOlivier Moysan mask = SAI_XCR1_MCKDIV_MASK(SAI_XCR1_MCKDIV_WIDTH(version)); 3028307b2afSOlivier Moysan cr1 = SAI_XCR1_MCKDIV_SET(div); 3038307b2afSOlivier Moysan ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, mask, cr1); 3048307b2afSOlivier Moysan if (ret < 0) 3058307b2afSOlivier Moysan dev_err(&sai->pdev->dev, "Failed to update CR1 register\n"); 3068307b2afSOlivier Moysan 3078307b2afSOlivier Moysan return ret; 3088307b2afSOlivier Moysan } 3098307b2afSOlivier Moysan 3108307b2afSOlivier Moysan static long stm32_sai_mclk_round_rate(struct clk_hw *hw, unsigned long rate, 3118307b2afSOlivier Moysan unsigned long *prate) 3128307b2afSOlivier Moysan { 3138307b2afSOlivier Moysan struct stm32_sai_mclk_data *mclk = to_mclk_data(hw); 3148307b2afSOlivier Moysan struct stm32_sai_sub_data *sai = mclk->sai_data; 3158307b2afSOlivier Moysan int div; 3168307b2afSOlivier Moysan 3178307b2afSOlivier Moysan div = stm32_sai_get_clk_div(sai, *prate, rate); 3188307b2afSOlivier Moysan if (div < 0) 3198307b2afSOlivier Moysan return div; 3208307b2afSOlivier Moysan 3218307b2afSOlivier Moysan mclk->freq = *prate / div; 3228307b2afSOlivier Moysan 3238307b2afSOlivier Moysan return mclk->freq; 3248307b2afSOlivier Moysan } 3258307b2afSOlivier Moysan 3268307b2afSOlivier Moysan static unsigned long stm32_sai_mclk_recalc_rate(struct clk_hw *hw, 3278307b2afSOlivier Moysan unsigned long parent_rate) 3288307b2afSOlivier Moysan { 3298307b2afSOlivier Moysan struct stm32_sai_mclk_data *mclk = to_mclk_data(hw); 3308307b2afSOlivier Moysan 3318307b2afSOlivier Moysan return mclk->freq; 3328307b2afSOlivier Moysan } 3338307b2afSOlivier Moysan 3348307b2afSOlivier Moysan static int stm32_sai_mclk_set_rate(struct clk_hw *hw, unsigned long rate, 3358307b2afSOlivier Moysan unsigned long parent_rate) 3368307b2afSOlivier Moysan { 3378307b2afSOlivier Moysan struct stm32_sai_mclk_data *mclk = to_mclk_data(hw); 3388307b2afSOlivier Moysan struct stm32_sai_sub_data *sai = mclk->sai_data; 3396b27e277SColin Ian King int div, ret; 3408307b2afSOlivier Moysan 3418307b2afSOlivier Moysan div = stm32_sai_get_clk_div(sai, parent_rate, rate); 3428307b2afSOlivier Moysan if (div < 0) 3438307b2afSOlivier Moysan return div; 3448307b2afSOlivier Moysan 3458307b2afSOlivier Moysan ret = stm32_sai_set_clk_div(sai, div); 3468307b2afSOlivier Moysan if (ret) 3478307b2afSOlivier Moysan return ret; 3488307b2afSOlivier Moysan 3498307b2afSOlivier Moysan mclk->freq = rate; 3508307b2afSOlivier Moysan 3518307b2afSOlivier Moysan return 0; 3528307b2afSOlivier Moysan } 3538307b2afSOlivier Moysan 3548307b2afSOlivier Moysan static int stm32_sai_mclk_enable(struct clk_hw *hw) 3558307b2afSOlivier Moysan { 3568307b2afSOlivier Moysan struct stm32_sai_mclk_data *mclk = to_mclk_data(hw); 3578307b2afSOlivier Moysan struct stm32_sai_sub_data *sai = mclk->sai_data; 3588307b2afSOlivier Moysan 3598307b2afSOlivier Moysan dev_dbg(&sai->pdev->dev, "Enable master clock\n"); 3608307b2afSOlivier Moysan 3618307b2afSOlivier Moysan return regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, 3628307b2afSOlivier Moysan SAI_XCR1_MCKEN, SAI_XCR1_MCKEN); 3638307b2afSOlivier Moysan } 3648307b2afSOlivier Moysan 3658307b2afSOlivier Moysan static void stm32_sai_mclk_disable(struct clk_hw *hw) 3668307b2afSOlivier Moysan { 3678307b2afSOlivier Moysan struct stm32_sai_mclk_data *mclk = to_mclk_data(hw); 3688307b2afSOlivier Moysan struct stm32_sai_sub_data *sai = mclk->sai_data; 3698307b2afSOlivier Moysan 3708307b2afSOlivier Moysan dev_dbg(&sai->pdev->dev, "Disable master clock\n"); 3718307b2afSOlivier Moysan 3728307b2afSOlivier Moysan regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, SAI_XCR1_MCKEN, 0); 3738307b2afSOlivier Moysan } 3748307b2afSOlivier Moysan 3758307b2afSOlivier Moysan static const struct clk_ops mclk_ops = { 3768307b2afSOlivier Moysan .enable = stm32_sai_mclk_enable, 3778307b2afSOlivier Moysan .disable = stm32_sai_mclk_disable, 3788307b2afSOlivier Moysan .recalc_rate = stm32_sai_mclk_recalc_rate, 3798307b2afSOlivier Moysan .round_rate = stm32_sai_mclk_round_rate, 3808307b2afSOlivier Moysan .set_rate = stm32_sai_mclk_set_rate, 3818307b2afSOlivier Moysan }; 3828307b2afSOlivier Moysan 3838307b2afSOlivier Moysan static int stm32_sai_add_mclk_provider(struct stm32_sai_sub_data *sai) 3848307b2afSOlivier Moysan { 3858307b2afSOlivier Moysan struct clk_hw *hw; 3868307b2afSOlivier Moysan struct stm32_sai_mclk_data *mclk; 3878307b2afSOlivier Moysan struct device *dev = &sai->pdev->dev; 3888307b2afSOlivier Moysan const char *pname = __clk_get_name(sai->sai_ck); 3898307b2afSOlivier Moysan char *mclk_name, *p, *s = (char *)pname; 3908307b2afSOlivier Moysan int ret, i = 0; 3918307b2afSOlivier Moysan 392496fa3baSWei Yongjun mclk = devm_kzalloc(dev, sizeof(*mclk), GFP_KERNEL); 3938307b2afSOlivier Moysan if (!mclk) 3948307b2afSOlivier Moysan return -ENOMEM; 3958307b2afSOlivier Moysan 3968307b2afSOlivier Moysan mclk_name = devm_kcalloc(dev, sizeof(char), 3978307b2afSOlivier Moysan SAI_MCLK_NAME_LEN, GFP_KERNEL); 3988307b2afSOlivier Moysan if (!mclk_name) 3998307b2afSOlivier Moysan return -ENOMEM; 4008307b2afSOlivier Moysan 4018307b2afSOlivier Moysan /* 4028307b2afSOlivier Moysan * Forge mclk clock name from parent clock name and suffix. 4038307b2afSOlivier Moysan * String after "_" char is stripped in parent name. 4048307b2afSOlivier Moysan */ 4058307b2afSOlivier Moysan p = mclk_name; 4066be0f96dSOlivier Moysan while (*s && *s != '_' && (i < (SAI_MCLK_NAME_LEN - 7))) { 4078307b2afSOlivier Moysan *p++ = *s++; 4088307b2afSOlivier Moysan i++; 4098307b2afSOlivier Moysan } 4106be0f96dSOlivier Moysan STM_SAI_IS_SUB_A(sai) ? strcat(p, "a_mclk") : strcat(p, "b_mclk"); 4118307b2afSOlivier Moysan 4128307b2afSOlivier Moysan mclk->hw.init = CLK_HW_INIT(mclk_name, pname, &mclk_ops, 0); 4138307b2afSOlivier Moysan mclk->sai_data = sai; 4148307b2afSOlivier Moysan hw = &mclk->hw; 4158307b2afSOlivier Moysan 4168307b2afSOlivier Moysan dev_dbg(dev, "Register master clock %s\n", mclk_name); 4178307b2afSOlivier Moysan ret = devm_clk_hw_register(&sai->pdev->dev, hw); 4188307b2afSOlivier Moysan if (ret) { 4198307b2afSOlivier Moysan dev_err(dev, "mclk register returned %d\n", ret); 4208307b2afSOlivier Moysan return ret; 4218307b2afSOlivier Moysan } 4228307b2afSOlivier Moysan sai->sai_mclk = hw->clk; 4238307b2afSOlivier Moysan 4248307b2afSOlivier Moysan /* register mclk provider */ 4258307b2afSOlivier Moysan return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw); 4268307b2afSOlivier Moysan } 4278307b2afSOlivier Moysan 4283e086edfSolivier moysan static irqreturn_t stm32_sai_isr(int irq, void *devid) 4293e086edfSolivier moysan { 4303e086edfSolivier moysan struct stm32_sai_sub_data *sai = (struct stm32_sai_sub_data *)devid; 4313e086edfSolivier moysan struct platform_device *pdev = sai->pdev; 4323e086edfSolivier moysan unsigned int sr, imr, flags; 4333e086edfSolivier moysan snd_pcm_state_t status = SNDRV_PCM_STATE_RUNNING; 4343e086edfSolivier moysan 4353e086edfSolivier moysan regmap_read(sai->regmap, STM_SAI_IMR_REGX, &imr); 4363e086edfSolivier moysan regmap_read(sai->regmap, STM_SAI_SR_REGX, &sr); 4373e086edfSolivier moysan 4383e086edfSolivier moysan flags = sr & imr; 4393e086edfSolivier moysan if (!flags) 4403e086edfSolivier moysan return IRQ_NONE; 4413e086edfSolivier moysan 4423e086edfSolivier moysan regmap_update_bits(sai->regmap, STM_SAI_CLRFR_REGX, SAI_XCLRFR_MASK, 4433e086edfSolivier moysan SAI_XCLRFR_MASK); 4443e086edfSolivier moysan 445d807cdfbSOlivier Moysan if (!sai->substream) { 446d807cdfbSOlivier Moysan dev_err(&pdev->dev, "Device stopped. Spurious IRQ 0x%x\n", sr); 447d807cdfbSOlivier Moysan return IRQ_NONE; 448d807cdfbSOlivier Moysan } 449d807cdfbSOlivier Moysan 4503e086edfSolivier moysan if (flags & SAI_XIMR_OVRUDRIE) { 451602fdadcSolivier moysan dev_err(&pdev->dev, "IRQ %s\n", 4523e086edfSolivier moysan STM_SAI_IS_PLAYBACK(sai) ? "underrun" : "overrun"); 4533e086edfSolivier moysan status = SNDRV_PCM_STATE_XRUN; 4543e086edfSolivier moysan } 4553e086edfSolivier moysan 4563e086edfSolivier moysan if (flags & SAI_XIMR_MUTEDETIE) 457602fdadcSolivier moysan dev_dbg(&pdev->dev, "IRQ mute detected\n"); 4583e086edfSolivier moysan 4593e086edfSolivier moysan if (flags & SAI_XIMR_WCKCFGIE) { 460602fdadcSolivier moysan dev_err(&pdev->dev, "IRQ wrong clock configuration\n"); 4613e086edfSolivier moysan status = SNDRV_PCM_STATE_DISCONNECTED; 4623e086edfSolivier moysan } 4633e086edfSolivier moysan 4643e086edfSolivier moysan if (flags & SAI_XIMR_CNRDYIE) 465602fdadcSolivier moysan dev_err(&pdev->dev, "IRQ Codec not ready\n"); 4663e086edfSolivier moysan 4673e086edfSolivier moysan if (flags & SAI_XIMR_AFSDETIE) { 468602fdadcSolivier moysan dev_err(&pdev->dev, "IRQ Anticipated frame synchro\n"); 4693e086edfSolivier moysan status = SNDRV_PCM_STATE_XRUN; 4703e086edfSolivier moysan } 4713e086edfSolivier moysan 4723e086edfSolivier moysan if (flags & SAI_XIMR_LFSDETIE) { 473602fdadcSolivier moysan dev_err(&pdev->dev, "IRQ Late frame synchro\n"); 4743e086edfSolivier moysan status = SNDRV_PCM_STATE_XRUN; 4753e086edfSolivier moysan } 4763e086edfSolivier moysan 477b1625fbbSTakashi Iwai if (status != SNDRV_PCM_STATE_RUNNING) 478b1625fbbSTakashi Iwai snd_pcm_stop_xrun(sai->substream); 4793e086edfSolivier moysan 4803e086edfSolivier moysan return IRQ_HANDLED; 4813e086edfSolivier moysan } 4823e086edfSolivier moysan 4833e086edfSolivier moysan static int stm32_sai_set_sysclk(struct snd_soc_dai *cpu_dai, 4843e086edfSolivier moysan int clk_id, unsigned int freq, int dir) 4853e086edfSolivier moysan { 4863e086edfSolivier moysan struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 487701a6ec3Solivier moysan int ret; 4883e086edfSolivier moysan 4898307b2afSOlivier Moysan if (dir == SND_SOC_CLOCK_OUT) { 490701a6ec3Solivier moysan ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, 491701a6ec3Solivier moysan SAI_XCR1_NODIV, 492701a6ec3Solivier moysan (unsigned int)~SAI_XCR1_NODIV); 493701a6ec3Solivier moysan if (ret < 0) 494701a6ec3Solivier moysan return ret; 495701a6ec3Solivier moysan 4963e086edfSolivier moysan dev_dbg(cpu_dai->dev, "SAI MCLK frequency is %uHz\n", freq); 4978307b2afSOlivier Moysan sai->mclk_rate = freq; 4988307b2afSOlivier Moysan 4998307b2afSOlivier Moysan if (sai->sai_mclk) { 5008307b2afSOlivier Moysan ret = clk_set_rate_exclusive(sai->sai_mclk, 5018307b2afSOlivier Moysan sai->mclk_rate); 5028307b2afSOlivier Moysan if (ret) { 5038307b2afSOlivier Moysan dev_err(cpu_dai->dev, 5048307b2afSOlivier Moysan "Could not set mclk rate\n"); 5058307b2afSOlivier Moysan return ret; 5068307b2afSOlivier Moysan } 5078307b2afSOlivier Moysan } 5083e086edfSolivier moysan } 5093e086edfSolivier moysan 5103e086edfSolivier moysan return 0; 5113e086edfSolivier moysan } 5123e086edfSolivier moysan 5133e086edfSolivier moysan static int stm32_sai_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask, 5143e086edfSolivier moysan u32 rx_mask, int slots, int slot_width) 5153e086edfSolivier moysan { 5163e086edfSolivier moysan struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 5173e086edfSolivier moysan int slotr, slotr_mask, slot_size; 5183e086edfSolivier moysan 5196eb17d70SOlivier Moysan if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { 5206eb17d70SOlivier Moysan dev_warn(cpu_dai->dev, "Slot setting relevant only for TDM\n"); 5216eb17d70SOlivier Moysan return 0; 5226eb17d70SOlivier Moysan } 5236eb17d70SOlivier Moysan 524602fdadcSolivier moysan dev_dbg(cpu_dai->dev, "Masks tx/rx:%#x/%#x, slots:%d, width:%d\n", 5253e086edfSolivier moysan tx_mask, rx_mask, slots, slot_width); 5263e086edfSolivier moysan 5273e086edfSolivier moysan switch (slot_width) { 5283e086edfSolivier moysan case 16: 5293e086edfSolivier moysan slot_size = SAI_SLOT_SIZE_16; 5303e086edfSolivier moysan break; 5313e086edfSolivier moysan case 32: 5323e086edfSolivier moysan slot_size = SAI_SLOT_SIZE_32; 5333e086edfSolivier moysan break; 5343e086edfSolivier moysan default: 5353e086edfSolivier moysan slot_size = SAI_SLOT_SIZE_AUTO; 5363e086edfSolivier moysan break; 5373e086edfSolivier moysan } 5383e086edfSolivier moysan 5393e086edfSolivier moysan slotr = SAI_XSLOTR_SLOTSZ_SET(slot_size) | 5403e086edfSolivier moysan SAI_XSLOTR_NBSLOT_SET(slots - 1); 5413e086edfSolivier moysan slotr_mask = SAI_XSLOTR_SLOTSZ_MASK | SAI_XSLOTR_NBSLOT_MASK; 5423e086edfSolivier moysan 5433e086edfSolivier moysan /* tx/rx mask set in machine init, if slot number defined in DT */ 5443e086edfSolivier moysan if (STM_SAI_IS_PLAYBACK(sai)) { 5453e086edfSolivier moysan sai->slot_mask = tx_mask; 5463e086edfSolivier moysan slotr |= SAI_XSLOTR_SLOTEN_SET(tx_mask); 5473e086edfSolivier moysan } 5483e086edfSolivier moysan 5493e086edfSolivier moysan if (STM_SAI_IS_CAPTURE(sai)) { 5503e086edfSolivier moysan sai->slot_mask = rx_mask; 5513e086edfSolivier moysan slotr |= SAI_XSLOTR_SLOTEN_SET(rx_mask); 5523e086edfSolivier moysan } 5533e086edfSolivier moysan 5543e086edfSolivier moysan slotr_mask |= SAI_XSLOTR_SLOTEN_MASK; 5553e086edfSolivier moysan 5563e086edfSolivier moysan regmap_update_bits(sai->regmap, STM_SAI_SLOTR_REGX, slotr_mask, slotr); 5573e086edfSolivier moysan 5583e086edfSolivier moysan sai->slot_width = slot_width; 5593e086edfSolivier moysan sai->slots = slots; 5603e086edfSolivier moysan 5613e086edfSolivier moysan return 0; 5623e086edfSolivier moysan } 5633e086edfSolivier moysan 5643e086edfSolivier moysan static int stm32_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) 5653e086edfSolivier moysan { 5663e086edfSolivier moysan struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 56761fb4ff7SOlivier Moysan int cr1, frcr = 0; 56861fb4ff7SOlivier Moysan int cr1_mask, frcr_mask = 0; 5693e086edfSolivier moysan int ret; 5703e086edfSolivier moysan 5713e086edfSolivier moysan dev_dbg(cpu_dai->dev, "fmt %x\n", fmt); 5723e086edfSolivier moysan 5736eb17d70SOlivier Moysan /* Do not generate master by default */ 5746eb17d70SOlivier Moysan cr1 = SAI_XCR1_NODIV; 5756eb17d70SOlivier Moysan cr1_mask = SAI_XCR1_NODIV; 5766eb17d70SOlivier Moysan 5776eb17d70SOlivier Moysan cr1_mask |= SAI_XCR1_PRTCFG_MASK; 5786eb17d70SOlivier Moysan if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { 5796eb17d70SOlivier Moysan cr1 |= SAI_XCR1_PRTCFG_SET(SAI_SPDIF_PROTOCOL); 5806eb17d70SOlivier Moysan goto conf_update; 5816eb17d70SOlivier Moysan } 5826eb17d70SOlivier Moysan 5836eb17d70SOlivier Moysan cr1 |= SAI_XCR1_PRTCFG_SET(SAI_FREE_PROTOCOL); 58461fb4ff7SOlivier Moysan 5853e086edfSolivier moysan switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 5863e086edfSolivier moysan /* SCK active high for all protocols */ 5873e086edfSolivier moysan case SND_SOC_DAIFMT_I2S: 5883e086edfSolivier moysan cr1 |= SAI_XCR1_CKSTR; 5893e086edfSolivier moysan frcr |= SAI_XFRCR_FSOFF | SAI_XFRCR_FSDEF; 5903e086edfSolivier moysan break; 5913e086edfSolivier moysan /* Left justified */ 5923e086edfSolivier moysan case SND_SOC_DAIFMT_MSB: 5933e086edfSolivier moysan frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSDEF; 5943e086edfSolivier moysan break; 5953e086edfSolivier moysan /* Right justified */ 5963e086edfSolivier moysan case SND_SOC_DAIFMT_LSB: 5973e086edfSolivier moysan frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSDEF; 5983e086edfSolivier moysan break; 5993e086edfSolivier moysan case SND_SOC_DAIFMT_DSP_A: 6003e086edfSolivier moysan frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSOFF; 6013e086edfSolivier moysan break; 6023e086edfSolivier moysan case SND_SOC_DAIFMT_DSP_B: 6033e086edfSolivier moysan frcr |= SAI_XFRCR_FSPOL; 6043e086edfSolivier moysan break; 6053e086edfSolivier moysan default: 6063e086edfSolivier moysan dev_err(cpu_dai->dev, "Unsupported protocol %#x\n", 6073e086edfSolivier moysan fmt & SND_SOC_DAIFMT_FORMAT_MASK); 6083e086edfSolivier moysan return -EINVAL; 6093e086edfSolivier moysan } 6103e086edfSolivier moysan 61161fb4ff7SOlivier Moysan cr1_mask |= SAI_XCR1_CKSTR; 6123e086edfSolivier moysan frcr_mask |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSOFF | 6133e086edfSolivier moysan SAI_XFRCR_FSDEF; 6143e086edfSolivier moysan 6153e086edfSolivier moysan /* DAI clock strobing. Invert setting previously set */ 6163e086edfSolivier moysan switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 6173e086edfSolivier moysan case SND_SOC_DAIFMT_NB_NF: 6183e086edfSolivier moysan break; 6193e086edfSolivier moysan case SND_SOC_DAIFMT_IB_NF: 6203e086edfSolivier moysan cr1 ^= SAI_XCR1_CKSTR; 6213e086edfSolivier moysan break; 6223e086edfSolivier moysan case SND_SOC_DAIFMT_NB_IF: 6233e086edfSolivier moysan frcr ^= SAI_XFRCR_FSPOL; 6243e086edfSolivier moysan break; 6253e086edfSolivier moysan case SND_SOC_DAIFMT_IB_IF: 6263e086edfSolivier moysan /* Invert fs & sck */ 6273e086edfSolivier moysan cr1 ^= SAI_XCR1_CKSTR; 6283e086edfSolivier moysan frcr ^= SAI_XFRCR_FSPOL; 6293e086edfSolivier moysan break; 6303e086edfSolivier moysan default: 6313e086edfSolivier moysan dev_err(cpu_dai->dev, "Unsupported strobing %#x\n", 6323e086edfSolivier moysan fmt & SND_SOC_DAIFMT_INV_MASK); 6333e086edfSolivier moysan return -EINVAL; 6343e086edfSolivier moysan } 6353e086edfSolivier moysan cr1_mask |= SAI_XCR1_CKSTR; 6363e086edfSolivier moysan frcr_mask |= SAI_XFRCR_FSPOL; 6373e086edfSolivier moysan 6383e086edfSolivier moysan regmap_update_bits(sai->regmap, STM_SAI_FRCR_REGX, frcr_mask, frcr); 6393e086edfSolivier moysan 6403e086edfSolivier moysan /* DAI clock master masks */ 6413e086edfSolivier moysan switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 6423e086edfSolivier moysan case SND_SOC_DAIFMT_CBM_CFM: 6433e086edfSolivier moysan /* codec is master */ 6443e086edfSolivier moysan cr1 |= SAI_XCR1_SLAVE; 6453e086edfSolivier moysan sai->master = false; 6463e086edfSolivier moysan break; 6473e086edfSolivier moysan case SND_SOC_DAIFMT_CBS_CFS: 6483e086edfSolivier moysan sai->master = true; 6493e086edfSolivier moysan break; 6503e086edfSolivier moysan default: 6513e086edfSolivier moysan dev_err(cpu_dai->dev, "Unsupported mode %#x\n", 6523e086edfSolivier moysan fmt & SND_SOC_DAIFMT_MASTER_MASK); 6533e086edfSolivier moysan return -EINVAL; 6543e086edfSolivier moysan } 6555914d285SOlivier Moysan 6565914d285SOlivier Moysan /* Set slave mode if sub-block is synchronized with another SAI */ 6575914d285SOlivier Moysan if (sai->sync) { 6585914d285SOlivier Moysan dev_dbg(cpu_dai->dev, "Synchronized SAI configured as slave\n"); 6595914d285SOlivier Moysan cr1 |= SAI_XCR1_SLAVE; 6605914d285SOlivier Moysan sai->master = false; 6615914d285SOlivier Moysan } 6625914d285SOlivier Moysan 6633e086edfSolivier moysan cr1_mask |= SAI_XCR1_SLAVE; 6643e086edfSolivier moysan 6656eb17d70SOlivier Moysan conf_update: 6663e086edfSolivier moysan ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, cr1_mask, cr1); 6673e086edfSolivier moysan if (ret < 0) { 6683e086edfSolivier moysan dev_err(cpu_dai->dev, "Failed to update CR1 register\n"); 6693e086edfSolivier moysan return ret; 6703e086edfSolivier moysan } 6713e086edfSolivier moysan 6723e086edfSolivier moysan sai->fmt = fmt; 6733e086edfSolivier moysan 6743e086edfSolivier moysan return 0; 6753e086edfSolivier moysan } 6763e086edfSolivier moysan 6773e086edfSolivier moysan static int stm32_sai_startup(struct snd_pcm_substream *substream, 6783e086edfSolivier moysan struct snd_soc_dai *cpu_dai) 6793e086edfSolivier moysan { 6803e086edfSolivier moysan struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 6813e086edfSolivier moysan int imr, cr2, ret; 6823e086edfSolivier moysan 6833e086edfSolivier moysan sai->substream = substream; 6843e086edfSolivier moysan 685b8468192SOlivier Moysan if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { 686b8468192SOlivier Moysan snd_pcm_hw_constraint_mask64(substream->runtime, 687b8468192SOlivier Moysan SNDRV_PCM_HW_PARAM_FORMAT, 688b8468192SOlivier Moysan SNDRV_PCM_FMTBIT_S32_LE); 689b8468192SOlivier Moysan snd_pcm_hw_constraint_single(substream->runtime, 690b8468192SOlivier Moysan SNDRV_PCM_HW_PARAM_CHANNELS, 2); 691b8468192SOlivier Moysan } 692b8468192SOlivier Moysan 6933e086edfSolivier moysan ret = clk_prepare_enable(sai->sai_ck); 6943e086edfSolivier moysan if (ret < 0) { 695602fdadcSolivier moysan dev_err(cpu_dai->dev, "Failed to enable clock: %d\n", ret); 6963e086edfSolivier moysan return ret; 6973e086edfSolivier moysan } 6983e086edfSolivier moysan 6993e086edfSolivier moysan /* Enable ITs */ 7003e086edfSolivier moysan 7013e086edfSolivier moysan regmap_update_bits(sai->regmap, STM_SAI_CLRFR_REGX, 7023e086edfSolivier moysan SAI_XCLRFR_MASK, SAI_XCLRFR_MASK); 7033e086edfSolivier moysan 7043e086edfSolivier moysan imr = SAI_XIMR_OVRUDRIE; 7053e086edfSolivier moysan if (STM_SAI_IS_CAPTURE(sai)) { 7063e086edfSolivier moysan regmap_read(sai->regmap, STM_SAI_CR2_REGX, &cr2); 7073e086edfSolivier moysan if (cr2 & SAI_XCR2_MUTECNT_MASK) 7083e086edfSolivier moysan imr |= SAI_XIMR_MUTEDETIE; 7093e086edfSolivier moysan } 7103e086edfSolivier moysan 7113e086edfSolivier moysan if (sai->master) 7123e086edfSolivier moysan imr |= SAI_XIMR_WCKCFGIE; 7133e086edfSolivier moysan else 7143e086edfSolivier moysan imr |= SAI_XIMR_AFSDETIE | SAI_XIMR_LFSDETIE; 7153e086edfSolivier moysan 7163e086edfSolivier moysan regmap_update_bits(sai->regmap, STM_SAI_IMR_REGX, 7173e086edfSolivier moysan SAI_XIMR_MASK, imr); 7183e086edfSolivier moysan 7193e086edfSolivier moysan return 0; 7203e086edfSolivier moysan } 7213e086edfSolivier moysan 7223e086edfSolivier moysan static int stm32_sai_set_config(struct snd_soc_dai *cpu_dai, 7233e086edfSolivier moysan struct snd_pcm_substream *substream, 7243e086edfSolivier moysan struct snd_pcm_hw_params *params) 7253e086edfSolivier moysan { 7263e086edfSolivier moysan struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 7273e086edfSolivier moysan int cr1, cr1_mask, ret; 7283e086edfSolivier moysan 729a4529d2bSOlivier Moysan /* 730a4529d2bSOlivier Moysan * DMA bursts increment is set to 4 words. 731a4529d2bSOlivier Moysan * SAI fifo threshold is set to half fifo, to keep enough space 732a4529d2bSOlivier Moysan * for DMA incoming bursts. 733a4529d2bSOlivier Moysan */ 7343e086edfSolivier moysan regmap_update_bits(sai->regmap, STM_SAI_CR2_REGX, 7353e086edfSolivier moysan SAI_XCR2_FFLUSH | SAI_XCR2_FTH_MASK, 736a4529d2bSOlivier Moysan SAI_XCR2_FFLUSH | 737a4529d2bSOlivier Moysan SAI_XCR2_FTH_SET(STM_SAI_FIFO_TH_HALF)); 7383e086edfSolivier moysan 7396eb17d70SOlivier Moysan /* DS bits in CR1 not set for SPDIF (size forced to 24 bits).*/ 7406eb17d70SOlivier Moysan if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { 7416eb17d70SOlivier Moysan sai->spdif_frm_cnt = 0; 7426eb17d70SOlivier Moysan return 0; 7436eb17d70SOlivier Moysan } 7446eb17d70SOlivier Moysan 7453e086edfSolivier moysan /* Mode, data format and channel config */ 74661fb4ff7SOlivier Moysan cr1_mask = SAI_XCR1_DS_MASK; 7473e086edfSolivier moysan switch (params_format(params)) { 7483e086edfSolivier moysan case SNDRV_PCM_FORMAT_S8: 7497e751e37Solivier moysan cr1 = SAI_XCR1_DS_SET(SAI_DATASIZE_8); 7503e086edfSolivier moysan break; 7513e086edfSolivier moysan case SNDRV_PCM_FORMAT_S16_LE: 7527e751e37Solivier moysan cr1 = SAI_XCR1_DS_SET(SAI_DATASIZE_16); 7533e086edfSolivier moysan break; 7543e086edfSolivier moysan case SNDRV_PCM_FORMAT_S32_LE: 7557e751e37Solivier moysan cr1 = SAI_XCR1_DS_SET(SAI_DATASIZE_32); 7563e086edfSolivier moysan break; 7573e086edfSolivier moysan default: 7583e086edfSolivier moysan dev_err(cpu_dai->dev, "Data format not supported"); 7593e086edfSolivier moysan return -EINVAL; 7603e086edfSolivier moysan } 7613e086edfSolivier moysan 7623e086edfSolivier moysan cr1_mask |= SAI_XCR1_MONO; 7633e086edfSolivier moysan if ((sai->slots == 2) && (params_channels(params) == 1)) 7643e086edfSolivier moysan cr1 |= SAI_XCR1_MONO; 7653e086edfSolivier moysan 7663e086edfSolivier moysan ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, cr1_mask, cr1); 7673e086edfSolivier moysan if (ret < 0) { 7683e086edfSolivier moysan dev_err(cpu_dai->dev, "Failed to update CR1 register\n"); 7693e086edfSolivier moysan return ret; 7703e086edfSolivier moysan } 7713e086edfSolivier moysan 7723e086edfSolivier moysan return 0; 7733e086edfSolivier moysan } 7743e086edfSolivier moysan 7753e086edfSolivier moysan static int stm32_sai_set_slots(struct snd_soc_dai *cpu_dai) 7763e086edfSolivier moysan { 7773e086edfSolivier moysan struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 7783e086edfSolivier moysan int slotr, slot_sz; 7793e086edfSolivier moysan 7803e086edfSolivier moysan regmap_read(sai->regmap, STM_SAI_SLOTR_REGX, &slotr); 7813e086edfSolivier moysan 7823e086edfSolivier moysan /* 7833e086edfSolivier moysan * If SLOTSZ is set to auto in SLOTR, align slot width on data size 7843e086edfSolivier moysan * By default slot width = data size, if not forced from DT 7853e086edfSolivier moysan */ 7863e086edfSolivier moysan slot_sz = slotr & SAI_XSLOTR_SLOTSZ_MASK; 7873e086edfSolivier moysan if (slot_sz == SAI_XSLOTR_SLOTSZ_SET(SAI_SLOT_SIZE_AUTO)) 7883e086edfSolivier moysan sai->slot_width = sai->data_size; 7893e086edfSolivier moysan 7903e086edfSolivier moysan if (sai->slot_width < sai->data_size) { 7913e086edfSolivier moysan dev_err(cpu_dai->dev, 7923e086edfSolivier moysan "Data size %d larger than slot width\n", 7933e086edfSolivier moysan sai->data_size); 7943e086edfSolivier moysan return -EINVAL; 7953e086edfSolivier moysan } 7963e086edfSolivier moysan 7973e086edfSolivier moysan /* Slot number is set to 2, if not specified in DT */ 7983e086edfSolivier moysan if (!sai->slots) 7993e086edfSolivier moysan sai->slots = 2; 8003e086edfSolivier moysan 8013e086edfSolivier moysan /* The number of slots in the audio frame is equal to NBSLOT[3:0] + 1*/ 8023e086edfSolivier moysan regmap_update_bits(sai->regmap, STM_SAI_SLOTR_REGX, 8033e086edfSolivier moysan SAI_XSLOTR_NBSLOT_MASK, 8043e086edfSolivier moysan SAI_XSLOTR_NBSLOT_SET((sai->slots - 1))); 8053e086edfSolivier moysan 8063e086edfSolivier moysan /* Set default slots mask if not already set from DT */ 8073e086edfSolivier moysan if (!(slotr & SAI_XSLOTR_SLOTEN_MASK)) { 8083e086edfSolivier moysan sai->slot_mask = (1 << sai->slots) - 1; 8093e086edfSolivier moysan regmap_update_bits(sai->regmap, 8103e086edfSolivier moysan STM_SAI_SLOTR_REGX, SAI_XSLOTR_SLOTEN_MASK, 8113e086edfSolivier moysan SAI_XSLOTR_SLOTEN_SET(sai->slot_mask)); 8123e086edfSolivier moysan } 8133e086edfSolivier moysan 814602fdadcSolivier moysan dev_dbg(cpu_dai->dev, "Slots %d, slot width %d\n", 8153e086edfSolivier moysan sai->slots, sai->slot_width); 8163e086edfSolivier moysan 8173e086edfSolivier moysan return 0; 8183e086edfSolivier moysan } 8193e086edfSolivier moysan 8203e086edfSolivier moysan static void stm32_sai_set_frame(struct snd_soc_dai *cpu_dai) 8213e086edfSolivier moysan { 8223e086edfSolivier moysan struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 8233e086edfSolivier moysan int fs_active, offset, format; 8243e086edfSolivier moysan int frcr, frcr_mask; 8253e086edfSolivier moysan 8263e086edfSolivier moysan format = sai->fmt & SND_SOC_DAIFMT_FORMAT_MASK; 8273e086edfSolivier moysan sai->fs_length = sai->slot_width * sai->slots; 8283e086edfSolivier moysan 8293e086edfSolivier moysan fs_active = sai->fs_length / 2; 8303e086edfSolivier moysan if ((format == SND_SOC_DAIFMT_DSP_A) || 8313e086edfSolivier moysan (format == SND_SOC_DAIFMT_DSP_B)) 8323e086edfSolivier moysan fs_active = 1; 8333e086edfSolivier moysan 8343e086edfSolivier moysan frcr = SAI_XFRCR_FRL_SET((sai->fs_length - 1)); 8353e086edfSolivier moysan frcr |= SAI_XFRCR_FSALL_SET((fs_active - 1)); 8363e086edfSolivier moysan frcr_mask = SAI_XFRCR_FRL_MASK | SAI_XFRCR_FSALL_MASK; 8373e086edfSolivier moysan 838602fdadcSolivier moysan dev_dbg(cpu_dai->dev, "Frame length %d, frame active %d\n", 8393e086edfSolivier moysan sai->fs_length, fs_active); 8403e086edfSolivier moysan 8413e086edfSolivier moysan regmap_update_bits(sai->regmap, STM_SAI_FRCR_REGX, frcr_mask, frcr); 8423e086edfSolivier moysan 8433e086edfSolivier moysan if ((sai->fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_LSB) { 8443e086edfSolivier moysan offset = sai->slot_width - sai->data_size; 8453e086edfSolivier moysan 8463e086edfSolivier moysan regmap_update_bits(sai->regmap, STM_SAI_SLOTR_REGX, 8473e086edfSolivier moysan SAI_XSLOTR_FBOFF_MASK, 8483e086edfSolivier moysan SAI_XSLOTR_FBOFF_SET(offset)); 8493e086edfSolivier moysan } 8503e086edfSolivier moysan } 8513e086edfSolivier moysan 852187e01d0Solivier moysan static void stm32_sai_init_iec958_status(struct stm32_sai_sub_data *sai) 853187e01d0Solivier moysan { 854187e01d0Solivier moysan unsigned char *cs = sai->iec958.status; 855187e01d0Solivier moysan 856187e01d0Solivier moysan cs[0] = IEC958_AES0_CON_NOT_COPYRIGHT | IEC958_AES0_CON_EMPHASIS_NONE; 857187e01d0Solivier moysan cs[1] = IEC958_AES1_CON_GENERAL; 858187e01d0Solivier moysan cs[2] = IEC958_AES2_CON_SOURCE_UNSPEC | IEC958_AES2_CON_CHANNEL_UNSPEC; 859187e01d0Solivier moysan cs[3] = IEC958_AES3_CON_CLOCK_1000PPM | IEC958_AES3_CON_FS_NOTID; 860187e01d0Solivier moysan } 861187e01d0Solivier moysan 862187e01d0Solivier moysan static void stm32_sai_set_iec958_status(struct stm32_sai_sub_data *sai, 863187e01d0Solivier moysan struct snd_pcm_runtime *runtime) 864187e01d0Solivier moysan { 865187e01d0Solivier moysan if (!runtime) 866187e01d0Solivier moysan return; 867187e01d0Solivier moysan 868187e01d0Solivier moysan /* Force the sample rate according to runtime rate */ 869187e01d0Solivier moysan mutex_lock(&sai->ctrl_lock); 870187e01d0Solivier moysan switch (runtime->rate) { 871187e01d0Solivier moysan case 22050: 872187e01d0Solivier moysan sai->iec958.status[3] = IEC958_AES3_CON_FS_22050; 873187e01d0Solivier moysan break; 874187e01d0Solivier moysan case 44100: 875187e01d0Solivier moysan sai->iec958.status[3] = IEC958_AES3_CON_FS_44100; 876187e01d0Solivier moysan break; 877187e01d0Solivier moysan case 88200: 878187e01d0Solivier moysan sai->iec958.status[3] = IEC958_AES3_CON_FS_88200; 879187e01d0Solivier moysan break; 880187e01d0Solivier moysan case 176400: 881187e01d0Solivier moysan sai->iec958.status[3] = IEC958_AES3_CON_FS_176400; 882187e01d0Solivier moysan break; 883187e01d0Solivier moysan case 24000: 884187e01d0Solivier moysan sai->iec958.status[3] = IEC958_AES3_CON_FS_24000; 885187e01d0Solivier moysan break; 886187e01d0Solivier moysan case 48000: 887187e01d0Solivier moysan sai->iec958.status[3] = IEC958_AES3_CON_FS_48000; 888187e01d0Solivier moysan break; 889187e01d0Solivier moysan case 96000: 890187e01d0Solivier moysan sai->iec958.status[3] = IEC958_AES3_CON_FS_96000; 891187e01d0Solivier moysan break; 892187e01d0Solivier moysan case 192000: 893187e01d0Solivier moysan sai->iec958.status[3] = IEC958_AES3_CON_FS_192000; 894187e01d0Solivier moysan break; 895187e01d0Solivier moysan case 32000: 896187e01d0Solivier moysan sai->iec958.status[3] = IEC958_AES3_CON_FS_32000; 897187e01d0Solivier moysan break; 898187e01d0Solivier moysan default: 899187e01d0Solivier moysan sai->iec958.status[3] = IEC958_AES3_CON_FS_NOTID; 900187e01d0Solivier moysan break; 901187e01d0Solivier moysan } 902187e01d0Solivier moysan mutex_unlock(&sai->ctrl_lock); 903187e01d0Solivier moysan } 904187e01d0Solivier moysan 9053e086edfSolivier moysan static int stm32_sai_configure_clock(struct snd_soc_dai *cpu_dai, 9063e086edfSolivier moysan struct snd_pcm_hw_params *params) 9073e086edfSolivier moysan { 9083e086edfSolivier moysan struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 90970605450SYueHaibing int div = 0; 9108307b2afSOlivier Moysan int sai_clk_rate, mclk_ratio, den; 9116eb17d70SOlivier Moysan unsigned int rate = params_rate(params); 9123e086edfSolivier moysan 9136eb17d70SOlivier Moysan if (!(rate % 11025)) 9143e086edfSolivier moysan clk_set_parent(sai->sai_ck, sai->pdata->clk_x11k); 9153e086edfSolivier moysan else 9163e086edfSolivier moysan clk_set_parent(sai->sai_ck, sai->pdata->clk_x8k); 9173e086edfSolivier moysan sai_clk_rate = clk_get_rate(sai->sai_ck); 9183e086edfSolivier moysan 91903e78a24Solivier moysan if (STM_SAI_IS_F4(sai->pdata)) { 9208307b2afSOlivier Moysan /* mclk on (NODIV=0) 9213e086edfSolivier moysan * mclk_rate = 256 * fs 9223e086edfSolivier moysan * MCKDIV = 0 if sai_ck < 3/2 * mclk_rate 9233e086edfSolivier moysan * MCKDIV = sai_ck / (2 * mclk_rate) otherwise 9248307b2afSOlivier Moysan * mclk off (NODIV=1) 9258307b2afSOlivier Moysan * MCKDIV ignored. sck = sai_ck 9263e086edfSolivier moysan */ 9278307b2afSOlivier Moysan if (!sai->mclk_rate) 9288307b2afSOlivier Moysan return 0; 9298307b2afSOlivier Moysan 9308307b2afSOlivier Moysan if (2 * sai_clk_rate >= 3 * sai->mclk_rate) { 9318307b2afSOlivier Moysan div = stm32_sai_get_clk_div(sai, sai_clk_rate, 93203e78a24Solivier moysan 2 * sai->mclk_rate); 9338307b2afSOlivier Moysan if (div < 0) 9348307b2afSOlivier Moysan return div; 9358307b2afSOlivier Moysan } 93603e78a24Solivier moysan } else { 93703e78a24Solivier moysan /* 93803e78a24Solivier moysan * TDM mode : 93903e78a24Solivier moysan * mclk on 94003e78a24Solivier moysan * MCKDIV = sai_ck / (ws x 256) (NOMCK=0. OSR=0) 94103e78a24Solivier moysan * MCKDIV = sai_ck / (ws x 512) (NOMCK=0. OSR=1) 94203e78a24Solivier moysan * mclk off 94303e78a24Solivier moysan * MCKDIV = sai_ck / (frl x ws) (NOMCK=1) 94403e78a24Solivier moysan * Note: NOMCK/NODIV correspond to same bit. 94503e78a24Solivier moysan */ 9466eb17d70SOlivier Moysan if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { 9478307b2afSOlivier Moysan div = stm32_sai_get_clk_div(sai, sai_clk_rate, 9488307b2afSOlivier Moysan rate * 128); 9498307b2afSOlivier Moysan if (div < 0) 9508307b2afSOlivier Moysan return div; 9516eb17d70SOlivier Moysan } else { 95203e78a24Solivier moysan if (sai->mclk_rate) { 9536eb17d70SOlivier Moysan mclk_ratio = sai->mclk_rate / rate; 95470605450SYueHaibing if ((mclk_ratio != 512) && 95570605450SYueHaibing (mclk_ratio != 256)) { 95603e78a24Solivier moysan dev_err(cpu_dai->dev, 95703e78a24Solivier moysan "Wrong mclk ratio %d\n", 95803e78a24Solivier moysan mclk_ratio); 95903e78a24Solivier moysan return -EINVAL; 96003e78a24Solivier moysan } 9618307b2afSOlivier Moysan div = stm32_sai_get_clk_div(sai, sai_clk_rate, 9626eb17d70SOlivier Moysan sai->mclk_rate); 9638307b2afSOlivier Moysan if (div < 0) 9648307b2afSOlivier Moysan return div; 96503e78a24Solivier moysan } else { 9666eb17d70SOlivier Moysan /* mclk-fs not set, master clock not active */ 96703e78a24Solivier moysan den = sai->fs_length * params_rate(params); 9688307b2afSOlivier Moysan div = stm32_sai_get_clk_div(sai, sai_clk_rate, 9698307b2afSOlivier Moysan den); 9708307b2afSOlivier Moysan if (div < 0) 9718307b2afSOlivier Moysan return div; 97203e78a24Solivier moysan } 97303e78a24Solivier moysan } 9746eb17d70SOlivier Moysan } 9753e086edfSolivier moysan 9768307b2afSOlivier Moysan return stm32_sai_set_clk_div(sai, div); 9773e086edfSolivier moysan } 9783e086edfSolivier moysan 9793e086edfSolivier moysan static int stm32_sai_hw_params(struct snd_pcm_substream *substream, 9803e086edfSolivier moysan struct snd_pcm_hw_params *params, 9813e086edfSolivier moysan struct snd_soc_dai *cpu_dai) 9823e086edfSolivier moysan { 9833e086edfSolivier moysan struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 9843e086edfSolivier moysan int ret; 9853e086edfSolivier moysan 9863e086edfSolivier moysan sai->data_size = params_width(params); 9873e086edfSolivier moysan 988187e01d0Solivier moysan if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { 989187e01d0Solivier moysan /* Rate not already set in runtime structure */ 990187e01d0Solivier moysan substream->runtime->rate = params_rate(params); 991187e01d0Solivier moysan stm32_sai_set_iec958_status(sai, substream->runtime); 992187e01d0Solivier moysan } else { 9933e086edfSolivier moysan ret = stm32_sai_set_slots(cpu_dai); 9943e086edfSolivier moysan if (ret < 0) 9953e086edfSolivier moysan return ret; 9963e086edfSolivier moysan stm32_sai_set_frame(cpu_dai); 9976eb17d70SOlivier Moysan } 9983e086edfSolivier moysan 9993e086edfSolivier moysan ret = stm32_sai_set_config(cpu_dai, substream, params); 10003e086edfSolivier moysan if (ret) 10013e086edfSolivier moysan return ret; 10023e086edfSolivier moysan 10033e086edfSolivier moysan if (sai->master) 10043e086edfSolivier moysan ret = stm32_sai_configure_clock(cpu_dai, params); 10053e086edfSolivier moysan 10063e086edfSolivier moysan return ret; 10073e086edfSolivier moysan } 10083e086edfSolivier moysan 10093e086edfSolivier moysan static int stm32_sai_trigger(struct snd_pcm_substream *substream, int cmd, 10103e086edfSolivier moysan struct snd_soc_dai *cpu_dai) 10113e086edfSolivier moysan { 10123e086edfSolivier moysan struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 10133e086edfSolivier moysan int ret; 10143e086edfSolivier moysan 10153e086edfSolivier moysan switch (cmd) { 10163e086edfSolivier moysan case SNDRV_PCM_TRIGGER_START: 10173e086edfSolivier moysan case SNDRV_PCM_TRIGGER_RESUME: 10183e086edfSolivier moysan case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 10193e086edfSolivier moysan dev_dbg(cpu_dai->dev, "Enable DMA and SAI\n"); 10203e086edfSolivier moysan 10213e086edfSolivier moysan regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, 10223e086edfSolivier moysan SAI_XCR1_DMAEN, SAI_XCR1_DMAEN); 10233e086edfSolivier moysan 10243e086edfSolivier moysan /* Enable SAI */ 10253e086edfSolivier moysan ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, 10263e086edfSolivier moysan SAI_XCR1_SAIEN, SAI_XCR1_SAIEN); 10273e086edfSolivier moysan if (ret < 0) 10283e086edfSolivier moysan dev_err(cpu_dai->dev, "Failed to update CR1 register\n"); 10293e086edfSolivier moysan break; 10303e086edfSolivier moysan case SNDRV_PCM_TRIGGER_SUSPEND: 10313e086edfSolivier moysan case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 10323e086edfSolivier moysan case SNDRV_PCM_TRIGGER_STOP: 10333e086edfSolivier moysan dev_dbg(cpu_dai->dev, "Disable DMA and SAI\n"); 10343e086edfSolivier moysan 103547a8907dSOlivier Moysan regmap_update_bits(sai->regmap, STM_SAI_IMR_REGX, 103647a8907dSOlivier Moysan SAI_XIMR_MASK, 0); 103747a8907dSOlivier Moysan 10383e086edfSolivier moysan regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, 10393e086edfSolivier moysan SAI_XCR1_SAIEN, 10403e086edfSolivier moysan (unsigned int)~SAI_XCR1_SAIEN); 10414fa17938Solivier moysan 10424fa17938Solivier moysan ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, 10434fa17938Solivier moysan SAI_XCR1_DMAEN, 10444fa17938Solivier moysan (unsigned int)~SAI_XCR1_DMAEN); 10453e086edfSolivier moysan if (ret < 0) 10463e086edfSolivier moysan dev_err(cpu_dai->dev, "Failed to update CR1 register\n"); 10476eb17d70SOlivier Moysan 10486eb17d70SOlivier Moysan if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) 10496eb17d70SOlivier Moysan sai->spdif_frm_cnt = 0; 10503e086edfSolivier moysan break; 10513e086edfSolivier moysan default: 10523e086edfSolivier moysan return -EINVAL; 10533e086edfSolivier moysan } 10543e086edfSolivier moysan 10553e086edfSolivier moysan return ret; 10563e086edfSolivier moysan } 10573e086edfSolivier moysan 10583e086edfSolivier moysan static void stm32_sai_shutdown(struct snd_pcm_substream *substream, 10593e086edfSolivier moysan struct snd_soc_dai *cpu_dai) 10603e086edfSolivier moysan { 10613e086edfSolivier moysan struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 10623e086edfSolivier moysan 10633e086edfSolivier moysan regmap_update_bits(sai->regmap, STM_SAI_IMR_REGX, SAI_XIMR_MASK, 0); 10643e086edfSolivier moysan 1065701a6ec3Solivier moysan regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, SAI_XCR1_NODIV, 1066701a6ec3Solivier moysan SAI_XCR1_NODIV); 1067701a6ec3Solivier moysan 10683e086edfSolivier moysan clk_disable_unprepare(sai->sai_ck); 10698307b2afSOlivier Moysan 10708307b2afSOlivier Moysan clk_rate_exclusive_put(sai->sai_mclk); 10718307b2afSOlivier Moysan 10723e086edfSolivier moysan sai->substream = NULL; 10733e086edfSolivier moysan } 10743e086edfSolivier moysan 1075187e01d0Solivier moysan static int stm32_sai_pcm_new(struct snd_soc_pcm_runtime *rtd, 1076187e01d0Solivier moysan struct snd_soc_dai *cpu_dai) 1077187e01d0Solivier moysan { 1078187e01d0Solivier moysan struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev); 10795f8a1000SOlivier Moysan struct snd_kcontrol_new knew = iec958_ctls; 1080187e01d0Solivier moysan 1081187e01d0Solivier moysan if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { 1082187e01d0Solivier moysan dev_dbg(&sai->pdev->dev, "%s: register iec controls", __func__); 10835f8a1000SOlivier Moysan knew.device = rtd->pcm->device; 10845f8a1000SOlivier Moysan return snd_ctl_add(rtd->pcm->card, snd_ctl_new1(&knew, sai)); 1085187e01d0Solivier moysan } 1086187e01d0Solivier moysan 1087187e01d0Solivier moysan return 0; 1088187e01d0Solivier moysan } 1089187e01d0Solivier moysan 10903e086edfSolivier moysan static int stm32_sai_dai_probe(struct snd_soc_dai *cpu_dai) 10913e086edfSolivier moysan { 10923e086edfSolivier moysan struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev); 109361fb4ff7SOlivier Moysan int cr1 = 0, cr1_mask; 10943e086edfSolivier moysan 10958307b2afSOlivier Moysan sai->cpu_dai = cpu_dai; 10968307b2afSOlivier Moysan 10973e086edfSolivier moysan sai->dma_params.addr = (dma_addr_t)(sai->phys_addr + STM_SAI_DR_REGX); 1098a4529d2bSOlivier Moysan /* 1099a4529d2bSOlivier Moysan * DMA supports 4, 8 or 16 burst sizes. Burst size 4 is the best choice, 1100a4529d2bSOlivier Moysan * as it allows bytes, half-word and words transfers. (See DMA fifos 1101a4529d2bSOlivier Moysan * constraints). 1102a4529d2bSOlivier Moysan */ 1103a4529d2bSOlivier Moysan sai->dma_params.maxburst = 4; 11043e086edfSolivier moysan /* Buswidth will be set by framework at runtime */ 11053e086edfSolivier moysan sai->dma_params.addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED; 11063e086edfSolivier moysan 11073e086edfSolivier moysan if (STM_SAI_IS_PLAYBACK(sai)) 11083e086edfSolivier moysan snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params, NULL); 11093e086edfSolivier moysan else 11103e086edfSolivier moysan snd_soc_dai_init_dma_data(cpu_dai, NULL, &sai->dma_params); 11113e086edfSolivier moysan 1112187e01d0Solivier moysan /* Next settings are not relevant for spdif mode */ 1113187e01d0Solivier moysan if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) 1114187e01d0Solivier moysan return 0; 1115187e01d0Solivier moysan 111661fb4ff7SOlivier Moysan cr1_mask = SAI_XCR1_RX_TX; 111761fb4ff7SOlivier Moysan if (STM_SAI_IS_CAPTURE(sai)) 111861fb4ff7SOlivier Moysan cr1 |= SAI_XCR1_RX_TX; 111961fb4ff7SOlivier Moysan 11205914d285SOlivier Moysan /* Configure synchronization */ 11215914d285SOlivier Moysan if (sai->sync == SAI_SYNC_EXTERNAL) { 11225914d285SOlivier Moysan /* Configure synchro client and provider */ 11235914d285SOlivier Moysan sai->pdata->set_sync(sai->pdata, sai->np_sync_provider, 11245914d285SOlivier Moysan sai->synco, sai->synci); 11255914d285SOlivier Moysan } 11265914d285SOlivier Moysan 11275914d285SOlivier Moysan cr1_mask |= SAI_XCR1_SYNCEN_MASK; 11285914d285SOlivier Moysan cr1 |= SAI_XCR1_SYNCEN_SET(sai->sync); 11295914d285SOlivier Moysan 113061fb4ff7SOlivier Moysan return regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, cr1_mask, cr1); 11313e086edfSolivier moysan } 11323e086edfSolivier moysan 11333e086edfSolivier moysan static const struct snd_soc_dai_ops stm32_sai_pcm_dai_ops = { 11343e086edfSolivier moysan .set_sysclk = stm32_sai_set_sysclk, 11353e086edfSolivier moysan .set_fmt = stm32_sai_set_dai_fmt, 11363e086edfSolivier moysan .set_tdm_slot = stm32_sai_set_dai_tdm_slot, 11373e086edfSolivier moysan .startup = stm32_sai_startup, 11383e086edfSolivier moysan .hw_params = stm32_sai_hw_params, 11393e086edfSolivier moysan .trigger = stm32_sai_trigger, 11403e086edfSolivier moysan .shutdown = stm32_sai_shutdown, 11413e086edfSolivier moysan }; 11423e086edfSolivier moysan 11436eb17d70SOlivier Moysan static int stm32_sai_pcm_process_spdif(struct snd_pcm_substream *substream, 11446eb17d70SOlivier Moysan int channel, unsigned long hwoff, 11456eb17d70SOlivier Moysan void *buf, unsigned long bytes) 11466eb17d70SOlivier Moysan { 11476eb17d70SOlivier Moysan struct snd_pcm_runtime *runtime = substream->runtime; 11486eb17d70SOlivier Moysan struct snd_soc_pcm_runtime *rtd = substream->private_data; 11496eb17d70SOlivier Moysan struct snd_soc_dai *cpu_dai = rtd->cpu_dai; 11506eb17d70SOlivier Moysan struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev); 11516eb17d70SOlivier Moysan int *ptr = (int *)(runtime->dma_area + hwoff + 11526eb17d70SOlivier Moysan channel * (runtime->dma_bytes / runtime->channels)); 11536eb17d70SOlivier Moysan ssize_t cnt = bytes_to_samples(runtime, bytes); 11546eb17d70SOlivier Moysan unsigned int frm_cnt = sai->spdif_frm_cnt; 11556eb17d70SOlivier Moysan unsigned int byte; 11566eb17d70SOlivier Moysan unsigned int mask; 11576eb17d70SOlivier Moysan 11586eb17d70SOlivier Moysan do { 11596eb17d70SOlivier Moysan *ptr = ((*ptr >> 8) & 0x00ffffff); 11606eb17d70SOlivier Moysan 11616eb17d70SOlivier Moysan /* Set channel status bit */ 11626eb17d70SOlivier Moysan byte = frm_cnt >> 3; 11636eb17d70SOlivier Moysan mask = 1 << (frm_cnt - (byte << 3)); 1164187e01d0Solivier moysan if (sai->iec958.status[byte] & mask) 11656eb17d70SOlivier Moysan *ptr |= 0x04000000; 11666eb17d70SOlivier Moysan ptr++; 11676eb17d70SOlivier Moysan 11686eb17d70SOlivier Moysan if (!(cnt % 2)) 11696eb17d70SOlivier Moysan frm_cnt++; 11706eb17d70SOlivier Moysan 11716eb17d70SOlivier Moysan if (frm_cnt == SAI_IEC60958_BLOCK_FRAMES) 11726eb17d70SOlivier Moysan frm_cnt = 0; 11736eb17d70SOlivier Moysan } while (--cnt); 11746eb17d70SOlivier Moysan sai->spdif_frm_cnt = frm_cnt; 11756eb17d70SOlivier Moysan 11766eb17d70SOlivier Moysan return 0; 11776eb17d70SOlivier Moysan } 11786eb17d70SOlivier Moysan 11793e086edfSolivier moysan static const struct snd_pcm_hardware stm32_sai_pcm_hw = { 11803e086edfSolivier moysan .info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP, 11813e086edfSolivier moysan .buffer_bytes_max = 8 * PAGE_SIZE, 11823e086edfSolivier moysan .period_bytes_min = 1024, /* 5ms at 48kHz */ 11833e086edfSolivier moysan .period_bytes_max = PAGE_SIZE, 11843e086edfSolivier moysan .periods_min = 2, 11853e086edfSolivier moysan .periods_max = 8, 11863e086edfSolivier moysan }; 11873e086edfSolivier moysan 11883e086edfSolivier moysan static struct snd_soc_dai_driver stm32_sai_playback_dai[] = { 11893e086edfSolivier moysan { 11903e086edfSolivier moysan .probe = stm32_sai_dai_probe, 1191187e01d0Solivier moysan .pcm_new = stm32_sai_pcm_new, 11923e086edfSolivier moysan .id = 1, /* avoid call to fmt_single_name() */ 11933e086edfSolivier moysan .playback = { 11943e086edfSolivier moysan .channels_min = 1, 11953e086edfSolivier moysan .channels_max = 2, 11963e086edfSolivier moysan .rate_min = 8000, 11973e086edfSolivier moysan .rate_max = 192000, 11983e086edfSolivier moysan .rates = SNDRV_PCM_RATE_CONTINUOUS, 11993e086edfSolivier moysan /* DMA does not support 24 bits transfers */ 12003e086edfSolivier moysan .formats = 12013e086edfSolivier moysan SNDRV_PCM_FMTBIT_S8 | 12023e086edfSolivier moysan SNDRV_PCM_FMTBIT_S16_LE | 12033e086edfSolivier moysan SNDRV_PCM_FMTBIT_S32_LE, 12043e086edfSolivier moysan }, 12053e086edfSolivier moysan .ops = &stm32_sai_pcm_dai_ops, 12063e086edfSolivier moysan } 12073e086edfSolivier moysan }; 12083e086edfSolivier moysan 12093e086edfSolivier moysan static struct snd_soc_dai_driver stm32_sai_capture_dai[] = { 12103e086edfSolivier moysan { 12113e086edfSolivier moysan .probe = stm32_sai_dai_probe, 12123e086edfSolivier moysan .id = 1, /* avoid call to fmt_single_name() */ 12133e086edfSolivier moysan .capture = { 12143e086edfSolivier moysan .channels_min = 1, 12153e086edfSolivier moysan .channels_max = 2, 12163e086edfSolivier moysan .rate_min = 8000, 12173e086edfSolivier moysan .rate_max = 192000, 12183e086edfSolivier moysan .rates = SNDRV_PCM_RATE_CONTINUOUS, 12193e086edfSolivier moysan /* DMA does not support 24 bits transfers */ 12203e086edfSolivier moysan .formats = 12213e086edfSolivier moysan SNDRV_PCM_FMTBIT_S8 | 12223e086edfSolivier moysan SNDRV_PCM_FMTBIT_S16_LE | 12233e086edfSolivier moysan SNDRV_PCM_FMTBIT_S32_LE, 12243e086edfSolivier moysan }, 12253e086edfSolivier moysan .ops = &stm32_sai_pcm_dai_ops, 12263e086edfSolivier moysan } 12273e086edfSolivier moysan }; 12283e086edfSolivier moysan 12293e086edfSolivier moysan static const struct snd_dmaengine_pcm_config stm32_sai_pcm_config = { 12303e086edfSolivier moysan .pcm_hardware = &stm32_sai_pcm_hw, 12313e086edfSolivier moysan .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, 12323e086edfSolivier moysan }; 12333e086edfSolivier moysan 12346eb17d70SOlivier Moysan static const struct snd_dmaengine_pcm_config stm32_sai_pcm_config_spdif = { 12356eb17d70SOlivier Moysan .pcm_hardware = &stm32_sai_pcm_hw, 12366eb17d70SOlivier Moysan .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, 12376eb17d70SOlivier Moysan .process = stm32_sai_pcm_process_spdif, 12386eb17d70SOlivier Moysan }; 12396eb17d70SOlivier Moysan 12403e086edfSolivier moysan static const struct snd_soc_component_driver stm32_component = { 12413e086edfSolivier moysan .name = "stm32-sai", 12423e086edfSolivier moysan }; 12433e086edfSolivier moysan 12443e086edfSolivier moysan static const struct of_device_id stm32_sai_sub_ids[] = { 12453e086edfSolivier moysan { .compatible = "st,stm32-sai-sub-a", 12463e086edfSolivier moysan .data = (void *)STM_SAI_A_ID}, 12473e086edfSolivier moysan { .compatible = "st,stm32-sai-sub-b", 12483e086edfSolivier moysan .data = (void *)STM_SAI_B_ID}, 12493e086edfSolivier moysan {} 12503e086edfSolivier moysan }; 12513e086edfSolivier moysan MODULE_DEVICE_TABLE(of, stm32_sai_sub_ids); 12523e086edfSolivier moysan 12533e086edfSolivier moysan static int stm32_sai_sub_parse_of(struct platform_device *pdev, 12543e086edfSolivier moysan struct stm32_sai_sub_data *sai) 12553e086edfSolivier moysan { 12563e086edfSolivier moysan struct device_node *np = pdev->dev.of_node; 12573e086edfSolivier moysan struct resource *res; 12583e086edfSolivier moysan void __iomem *base; 12595914d285SOlivier Moysan struct of_phandle_args args; 12605914d285SOlivier Moysan int ret; 12613e086edfSolivier moysan 12623e086edfSolivier moysan if (!np) 12633e086edfSolivier moysan return -ENODEV; 12643e086edfSolivier moysan 12653e086edfSolivier moysan res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 12663e086edfSolivier moysan base = devm_ioremap_resource(&pdev->dev, res); 12673e086edfSolivier moysan if (IS_ERR(base)) 12683e086edfSolivier moysan return PTR_ERR(base); 12693e086edfSolivier moysan 12703e086edfSolivier moysan sai->phys_addr = res->start; 127103e78a24Solivier moysan 127203e78a24Solivier moysan sai->regmap_config = &stm32_sai_sub_regmap_config_f4; 127303e78a24Solivier moysan /* Note: PDM registers not available for H7 sub-block B */ 127403e78a24Solivier moysan if (STM_SAI_IS_H7(sai->pdata) && STM_SAI_IS_SUB_A(sai)) 127503e78a24Solivier moysan sai->regmap_config = &stm32_sai_sub_regmap_config_h7; 127603e78a24Solivier moysan 127703e78a24Solivier moysan sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "sai_ck", 127803e78a24Solivier moysan base, sai->regmap_config); 127903e78a24Solivier moysan if (IS_ERR(sai->regmap)) { 128003e78a24Solivier moysan dev_err(&pdev->dev, "Failed to initialize MMIO\n"); 128103e78a24Solivier moysan return PTR_ERR(sai->regmap); 128203e78a24Solivier moysan } 12833e086edfSolivier moysan 12843e086edfSolivier moysan /* Get direction property */ 12853e086edfSolivier moysan if (of_property_match_string(np, "dma-names", "tx") >= 0) { 12863e086edfSolivier moysan sai->dir = SNDRV_PCM_STREAM_PLAYBACK; 12873e086edfSolivier moysan } else if (of_property_match_string(np, "dma-names", "rx") >= 0) { 12883e086edfSolivier moysan sai->dir = SNDRV_PCM_STREAM_CAPTURE; 12893e086edfSolivier moysan } else { 12903e086edfSolivier moysan dev_err(&pdev->dev, "Unsupported direction\n"); 12913e086edfSolivier moysan return -EINVAL; 12923e086edfSolivier moysan } 12933e086edfSolivier moysan 12946eb17d70SOlivier Moysan /* Get spdif iec60958 property */ 12956eb17d70SOlivier Moysan sai->spdif = false; 12966eb17d70SOlivier Moysan if (of_get_property(np, "st,iec60958", NULL)) { 12976eb17d70SOlivier Moysan if (!STM_SAI_HAS_SPDIF(sai) || 12986eb17d70SOlivier Moysan sai->dir == SNDRV_PCM_STREAM_CAPTURE) { 12996eb17d70SOlivier Moysan dev_err(&pdev->dev, "S/PDIF IEC60958 not supported\n"); 13006eb17d70SOlivier Moysan return -EINVAL; 13016eb17d70SOlivier Moysan } 1302187e01d0Solivier moysan stm32_sai_init_iec958_status(sai); 13036eb17d70SOlivier Moysan sai->spdif = true; 13046eb17d70SOlivier Moysan sai->master = true; 13056eb17d70SOlivier Moysan } 13066eb17d70SOlivier Moysan 13075914d285SOlivier Moysan /* Get synchronization property */ 13085914d285SOlivier Moysan args.np = NULL; 13095914d285SOlivier Moysan ret = of_parse_phandle_with_fixed_args(np, "st,sync", 1, 0, &args); 13105914d285SOlivier Moysan if (ret < 0 && ret != -ENOENT) { 13115914d285SOlivier Moysan dev_err(&pdev->dev, "Failed to get st,sync property\n"); 13125914d285SOlivier Moysan return ret; 13135914d285SOlivier Moysan } 13145914d285SOlivier Moysan 13155914d285SOlivier Moysan sai->sync = SAI_SYNC_NONE; 13165914d285SOlivier Moysan if (args.np) { 13175914d285SOlivier Moysan if (args.np == np) { 13185d585e1eSRob Herring dev_err(&pdev->dev, "%pOFn sync own reference\n", np); 13195914d285SOlivier Moysan of_node_put(args.np); 13205914d285SOlivier Moysan return -EINVAL; 13215914d285SOlivier Moysan } 13225914d285SOlivier Moysan 13235914d285SOlivier Moysan sai->np_sync_provider = of_get_parent(args.np); 13245914d285SOlivier Moysan if (!sai->np_sync_provider) { 13255d585e1eSRob Herring dev_err(&pdev->dev, "%pOFn parent node not found\n", 13265d585e1eSRob Herring np); 13275914d285SOlivier Moysan of_node_put(args.np); 13285914d285SOlivier Moysan return -ENODEV; 13295914d285SOlivier Moysan } 13305914d285SOlivier Moysan 13315914d285SOlivier Moysan sai->sync = SAI_SYNC_INTERNAL; 13325914d285SOlivier Moysan if (sai->np_sync_provider != sai->pdata->pdev->dev.of_node) { 13335914d285SOlivier Moysan if (!STM_SAI_HAS_EXT_SYNC(sai)) { 13345914d285SOlivier Moysan dev_err(&pdev->dev, 13355914d285SOlivier Moysan "External synchro not supported\n"); 13365914d285SOlivier Moysan of_node_put(args.np); 13375914d285SOlivier Moysan return -EINVAL; 13385914d285SOlivier Moysan } 13395914d285SOlivier Moysan sai->sync = SAI_SYNC_EXTERNAL; 13405914d285SOlivier Moysan 13415914d285SOlivier Moysan sai->synci = args.args[0]; 13425914d285SOlivier Moysan if (sai->synci < 1 || 13435914d285SOlivier Moysan (sai->synci > (SAI_GCR_SYNCIN_MAX + 1))) { 13445914d285SOlivier Moysan dev_err(&pdev->dev, "Wrong SAI index\n"); 13455914d285SOlivier Moysan of_node_put(args.np); 13465914d285SOlivier Moysan return -EINVAL; 13475914d285SOlivier Moysan } 13485914d285SOlivier Moysan 13495914d285SOlivier Moysan if (of_property_match_string(args.np, "compatible", 13505914d285SOlivier Moysan "st,stm32-sai-sub-a") >= 0) 13515914d285SOlivier Moysan sai->synco = STM_SAI_SYNC_OUT_A; 13525914d285SOlivier Moysan 13535914d285SOlivier Moysan if (of_property_match_string(args.np, "compatible", 13545914d285SOlivier Moysan "st,stm32-sai-sub-b") >= 0) 13555914d285SOlivier Moysan sai->synco = STM_SAI_SYNC_OUT_B; 13565914d285SOlivier Moysan 13575914d285SOlivier Moysan if (!sai->synco) { 13585914d285SOlivier Moysan dev_err(&pdev->dev, "Unknown SAI sub-block\n"); 13595914d285SOlivier Moysan of_node_put(args.np); 13605914d285SOlivier Moysan return -EINVAL; 13615914d285SOlivier Moysan } 13625914d285SOlivier Moysan } 13635914d285SOlivier Moysan 13645914d285SOlivier Moysan dev_dbg(&pdev->dev, "%s synchronized with %s\n", 13655914d285SOlivier Moysan pdev->name, args.np->full_name); 13665914d285SOlivier Moysan } 13675914d285SOlivier Moysan 13685914d285SOlivier Moysan of_node_put(args.np); 13693e086edfSolivier moysan sai->sai_ck = devm_clk_get(&pdev->dev, "sai_ck"); 13703e086edfSolivier moysan if (IS_ERR(sai->sai_ck)) { 1371602fdadcSolivier moysan dev_err(&pdev->dev, "Missing kernel clock sai_ck\n"); 13723e086edfSolivier moysan return PTR_ERR(sai->sai_ck); 13733e086edfSolivier moysan } 13743e086edfSolivier moysan 13758307b2afSOlivier Moysan if (STM_SAI_IS_F4(sai->pdata)) 13768307b2afSOlivier Moysan return 0; 13778307b2afSOlivier Moysan 13788307b2afSOlivier Moysan /* Register mclk provider if requested */ 13798307b2afSOlivier Moysan if (of_find_property(np, "#clock-cells", NULL)) { 13808307b2afSOlivier Moysan ret = stm32_sai_add_mclk_provider(sai); 13818307b2afSOlivier Moysan if (ret < 0) 13828307b2afSOlivier Moysan return ret; 13838307b2afSOlivier Moysan } else { 13848307b2afSOlivier Moysan sai->sai_mclk = devm_clk_get(&pdev->dev, "MCLK"); 13858307b2afSOlivier Moysan if (IS_ERR(sai->sai_mclk)) { 13868307b2afSOlivier Moysan if (PTR_ERR(sai->sai_mclk) != -ENOENT) 13878307b2afSOlivier Moysan return PTR_ERR(sai->sai_mclk); 13888307b2afSOlivier Moysan sai->sai_mclk = NULL; 13898307b2afSOlivier Moysan } 13908307b2afSOlivier Moysan } 13918307b2afSOlivier Moysan 13923e086edfSolivier moysan return 0; 13933e086edfSolivier moysan } 13943e086edfSolivier moysan 13953e086edfSolivier moysan static int stm32_sai_sub_dais_init(struct platform_device *pdev, 13963e086edfSolivier moysan struct stm32_sai_sub_data *sai) 13973e086edfSolivier moysan { 13983e086edfSolivier moysan sai->cpu_dai_drv = devm_kzalloc(&pdev->dev, 13993e086edfSolivier moysan sizeof(struct snd_soc_dai_driver), 14003e086edfSolivier moysan GFP_KERNEL); 14013e086edfSolivier moysan if (!sai->cpu_dai_drv) 14023e086edfSolivier moysan return -ENOMEM; 14033e086edfSolivier moysan 14043e086edfSolivier moysan sai->cpu_dai_drv->name = dev_name(&pdev->dev); 14053e086edfSolivier moysan if (STM_SAI_IS_PLAYBACK(sai)) { 14063e086edfSolivier moysan memcpy(sai->cpu_dai_drv, &stm32_sai_playback_dai, 14073e086edfSolivier moysan sizeof(stm32_sai_playback_dai)); 14083e086edfSolivier moysan sai->cpu_dai_drv->playback.stream_name = sai->cpu_dai_drv->name; 14093e086edfSolivier moysan } else { 14103e086edfSolivier moysan memcpy(sai->cpu_dai_drv, &stm32_sai_capture_dai, 14113e086edfSolivier moysan sizeof(stm32_sai_capture_dai)); 14123e086edfSolivier moysan sai->cpu_dai_drv->capture.stream_name = sai->cpu_dai_drv->name; 14133e086edfSolivier moysan } 14143e086edfSolivier moysan 14153e086edfSolivier moysan return 0; 14163e086edfSolivier moysan } 14173e086edfSolivier moysan 14183e086edfSolivier moysan static int stm32_sai_sub_probe(struct platform_device *pdev) 14193e086edfSolivier moysan { 14203e086edfSolivier moysan struct stm32_sai_sub_data *sai; 14213e086edfSolivier moysan const struct of_device_id *of_id; 14226eb17d70SOlivier Moysan const struct snd_dmaengine_pcm_config *conf = &stm32_sai_pcm_config; 14233e086edfSolivier moysan int ret; 14243e086edfSolivier moysan 14253e086edfSolivier moysan sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL); 14263e086edfSolivier moysan if (!sai) 14273e086edfSolivier moysan return -ENOMEM; 14283e086edfSolivier moysan 14293e086edfSolivier moysan of_id = of_match_device(stm32_sai_sub_ids, &pdev->dev); 14303e086edfSolivier moysan if (!of_id) 14313e086edfSolivier moysan return -EINVAL; 14323e086edfSolivier moysan sai->id = (uintptr_t)of_id->data; 14333e086edfSolivier moysan 14343e086edfSolivier moysan sai->pdev = pdev; 1435187e01d0Solivier moysan mutex_init(&sai->ctrl_lock); 14363e086edfSolivier moysan platform_set_drvdata(pdev, sai); 14373e086edfSolivier moysan 14383e086edfSolivier moysan sai->pdata = dev_get_drvdata(pdev->dev.parent); 14393e086edfSolivier moysan if (!sai->pdata) { 14403e086edfSolivier moysan dev_err(&pdev->dev, "Parent device data not available\n"); 14413e086edfSolivier moysan return -EINVAL; 14423e086edfSolivier moysan } 14433e086edfSolivier moysan 14443e086edfSolivier moysan ret = stm32_sai_sub_parse_of(pdev, sai); 14453e086edfSolivier moysan if (ret) 14463e086edfSolivier moysan return ret; 14473e086edfSolivier moysan 14483e086edfSolivier moysan ret = stm32_sai_sub_dais_init(pdev, sai); 14493e086edfSolivier moysan if (ret) 14503e086edfSolivier moysan return ret; 14513e086edfSolivier moysan 14523e086edfSolivier moysan ret = devm_request_irq(&pdev->dev, sai->pdata->irq, stm32_sai_isr, 14533e086edfSolivier moysan IRQF_SHARED, dev_name(&pdev->dev), sai); 14543e086edfSolivier moysan if (ret) { 1455602fdadcSolivier moysan dev_err(&pdev->dev, "IRQ request returned %d\n", ret); 14563e086edfSolivier moysan return ret; 14573e086edfSolivier moysan } 14583e086edfSolivier moysan 14593e086edfSolivier moysan ret = devm_snd_soc_register_component(&pdev->dev, &stm32_component, 14603e086edfSolivier moysan sai->cpu_dai_drv, 1); 14613e086edfSolivier moysan if (ret) 14623e086edfSolivier moysan return ret; 14633e086edfSolivier moysan 14646eb17d70SOlivier Moysan if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) 14656eb17d70SOlivier Moysan conf = &stm32_sai_pcm_config_spdif; 14666eb17d70SOlivier Moysan 14676eb17d70SOlivier Moysan ret = devm_snd_dmaengine_pcm_register(&pdev->dev, conf, 0); 14683e086edfSolivier moysan if (ret) { 1469602fdadcSolivier moysan dev_err(&pdev->dev, "Could not register pcm dma\n"); 14703e086edfSolivier moysan return ret; 14713e086edfSolivier moysan } 14723e086edfSolivier moysan 14733e086edfSolivier moysan return 0; 14743e086edfSolivier moysan } 14753e086edfSolivier moysan 14763e086edfSolivier moysan static struct platform_driver stm32_sai_sub_driver = { 14773e086edfSolivier moysan .driver = { 14783e086edfSolivier moysan .name = "st,stm32-sai-sub", 14793e086edfSolivier moysan .of_match_table = stm32_sai_sub_ids, 14803e086edfSolivier moysan }, 14813e086edfSolivier moysan .probe = stm32_sai_sub_probe, 14823e086edfSolivier moysan }; 14833e086edfSolivier moysan 14843e086edfSolivier moysan module_platform_driver(stm32_sai_sub_driver); 14853e086edfSolivier moysan 14863e086edfSolivier moysan MODULE_DESCRIPTION("STM32 Soc SAI sub-block Interface"); 1487602fdadcSolivier moysan MODULE_AUTHOR("Olivier Moysan <olivier.moysan@st.com>"); 14883e086edfSolivier moysan MODULE_ALIAS("platform:st,stm32-sai-sub"); 14893e086edfSolivier moysan MODULE_LICENSE("GPL v2"); 1490