13e086edfSolivier moysan /* 23e086edfSolivier moysan * STM32 ALSA SoC Digital Audio Interface (SAI) driver. 33e086edfSolivier moysan * 43e086edfSolivier moysan * Copyright (C) 2016, STMicroelectronics - All Rights Reserved 53e086edfSolivier moysan * Author(s): Olivier Moysan <olivier.moysan@st.com> for STMicroelectronics. 63e086edfSolivier moysan * 73e086edfSolivier moysan * License terms: GPL V2.0. 83e086edfSolivier moysan * 93e086edfSolivier moysan * This program is free software; you can redistribute it and/or modify it 103e086edfSolivier moysan * under the terms of the GNU General Public License version 2 as published by 113e086edfSolivier moysan * the Free Software Foundation. 123e086edfSolivier moysan * 133e086edfSolivier moysan * This program is distributed in the hope that it will be useful, but 143e086edfSolivier moysan * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 153e086edfSolivier moysan * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more 163e086edfSolivier moysan * details. 173e086edfSolivier moysan */ 183e086edfSolivier moysan 193e086edfSolivier moysan #include <linux/clk.h> 203e086edfSolivier moysan #include <linux/kernel.h> 213e086edfSolivier moysan #include <linux/module.h> 223e086edfSolivier moysan #include <linux/of_irq.h> 233e086edfSolivier moysan #include <linux/of_platform.h> 243e086edfSolivier moysan #include <linux/regmap.h> 253e086edfSolivier moysan 263e086edfSolivier moysan #include <sound/core.h> 273e086edfSolivier moysan #include <sound/dmaengine_pcm.h> 283e086edfSolivier moysan #include <sound/pcm_params.h> 293e086edfSolivier moysan 303e086edfSolivier moysan #include "stm32_sai.h" 313e086edfSolivier moysan 323e086edfSolivier moysan #define SAI_FREE_PROTOCOL 0x0 333e086edfSolivier moysan 343e086edfSolivier moysan #define SAI_SLOT_SIZE_AUTO 0x0 353e086edfSolivier moysan #define SAI_SLOT_SIZE_16 0x1 363e086edfSolivier moysan #define SAI_SLOT_SIZE_32 0x2 373e086edfSolivier moysan 383e086edfSolivier moysan #define SAI_DATASIZE_8 0x2 393e086edfSolivier moysan #define SAI_DATASIZE_10 0x3 403e086edfSolivier moysan #define SAI_DATASIZE_16 0x4 413e086edfSolivier moysan #define SAI_DATASIZE_20 0x5 423e086edfSolivier moysan #define SAI_DATASIZE_24 0x6 433e086edfSolivier moysan #define SAI_DATASIZE_32 0x7 443e086edfSolivier moysan 453e086edfSolivier moysan #define STM_SAI_FIFO_SIZE 8 463e086edfSolivier moysan #define STM_SAI_DAI_NAME_SIZE 15 473e086edfSolivier moysan 483e086edfSolivier moysan #define STM_SAI_IS_PLAYBACK(ip) ((ip)->dir == SNDRV_PCM_STREAM_PLAYBACK) 493e086edfSolivier moysan #define STM_SAI_IS_CAPTURE(ip) ((ip)->dir == SNDRV_PCM_STREAM_CAPTURE) 503e086edfSolivier moysan 513e086edfSolivier moysan #define STM_SAI_A_ID 0x0 523e086edfSolivier moysan #define STM_SAI_B_ID 0x1 533e086edfSolivier moysan 5403e78a24Solivier moysan #define STM_SAI_IS_SUB_A(x) ((x)->id == STM_SAI_A_ID) 5503e78a24Solivier moysan #define STM_SAI_IS_SUB_B(x) ((x)->id == STM_SAI_B_ID) 563e086edfSolivier moysan #define STM_SAI_BLOCK_NAME(x) (((x)->id == STM_SAI_A_ID) ? "A" : "B") 573e086edfSolivier moysan 583e086edfSolivier moysan /** 593e086edfSolivier moysan * struct stm32_sai_sub_data - private data of SAI sub block (block A or B) 603e086edfSolivier moysan * @pdev: device data pointer 613e086edfSolivier moysan * @regmap: SAI register map pointer 6203e78a24Solivier moysan * @regmap_config: SAI sub block register map configuration pointer 633e086edfSolivier moysan * @dma_params: dma configuration data for rx or tx channel 643e086edfSolivier moysan * @cpu_dai_drv: DAI driver data pointer 653e086edfSolivier moysan * @cpu_dai: DAI runtime data pointer 663e086edfSolivier moysan * @substream: PCM substream data pointer 673e086edfSolivier moysan * @pdata: SAI block parent data pointer 683e086edfSolivier moysan * @sai_ck: kernel clock feeding the SAI clock generator 693e086edfSolivier moysan * @phys_addr: SAI registers physical base address 703e086edfSolivier moysan * @mclk_rate: SAI block master clock frequency (Hz). set at init 713e086edfSolivier moysan * @id: SAI sub block id corresponding to sub-block A or B 723e086edfSolivier moysan * @dir: SAI block direction (playback or capture). set at init 733e086edfSolivier moysan * @master: SAI block mode flag. (true=master, false=slave) set at init 743e086edfSolivier moysan * @fmt: SAI block format. relevant only for custom protocols. set at init 753e086edfSolivier moysan * @sync: SAI block synchronization mode. (none, internal or external) 763e086edfSolivier moysan * @fs_length: frame synchronization length. depends on protocol settings 773e086edfSolivier moysan * @slots: rx or tx slot number 783e086edfSolivier moysan * @slot_width: rx or tx slot width in bits 793e086edfSolivier moysan * @slot_mask: rx or tx active slots mask. set at init or at runtime 803e086edfSolivier moysan * @data_size: PCM data width. corresponds to PCM substream width. 813e086edfSolivier moysan */ 823e086edfSolivier moysan struct stm32_sai_sub_data { 833e086edfSolivier moysan struct platform_device *pdev; 843e086edfSolivier moysan struct regmap *regmap; 8503e78a24Solivier moysan const struct regmap_config *regmap_config; 863e086edfSolivier moysan struct snd_dmaengine_dai_dma_data dma_params; 873e086edfSolivier moysan struct snd_soc_dai_driver *cpu_dai_drv; 883e086edfSolivier moysan struct snd_soc_dai *cpu_dai; 893e086edfSolivier moysan struct snd_pcm_substream *substream; 903e086edfSolivier moysan struct stm32_sai_data *pdata; 913e086edfSolivier moysan struct clk *sai_ck; 923e086edfSolivier moysan dma_addr_t phys_addr; 933e086edfSolivier moysan unsigned int mclk_rate; 943e086edfSolivier moysan unsigned int id; 953e086edfSolivier moysan int dir; 963e086edfSolivier moysan bool master; 973e086edfSolivier moysan int fmt; 983e086edfSolivier moysan int sync; 993e086edfSolivier moysan int fs_length; 1003e086edfSolivier moysan int slots; 1013e086edfSolivier moysan int slot_width; 1023e086edfSolivier moysan int slot_mask; 1033e086edfSolivier moysan int data_size; 1043e086edfSolivier moysan }; 1053e086edfSolivier moysan 1063e086edfSolivier moysan enum stm32_sai_fifo_th { 1073e086edfSolivier moysan STM_SAI_FIFO_TH_EMPTY, 1083e086edfSolivier moysan STM_SAI_FIFO_TH_QUARTER, 1093e086edfSolivier moysan STM_SAI_FIFO_TH_HALF, 1103e086edfSolivier moysan STM_SAI_FIFO_TH_3_QUARTER, 1113e086edfSolivier moysan STM_SAI_FIFO_TH_FULL, 1123e086edfSolivier moysan }; 1133e086edfSolivier moysan 1143e086edfSolivier moysan static bool stm32_sai_sub_readable_reg(struct device *dev, unsigned int reg) 1153e086edfSolivier moysan { 1163e086edfSolivier moysan switch (reg) { 1173e086edfSolivier moysan case STM_SAI_CR1_REGX: 1183e086edfSolivier moysan case STM_SAI_CR2_REGX: 1193e086edfSolivier moysan case STM_SAI_FRCR_REGX: 1203e086edfSolivier moysan case STM_SAI_SLOTR_REGX: 1213e086edfSolivier moysan case STM_SAI_IMR_REGX: 1223e086edfSolivier moysan case STM_SAI_SR_REGX: 1233e086edfSolivier moysan case STM_SAI_CLRFR_REGX: 1243e086edfSolivier moysan case STM_SAI_DR_REGX: 12503e78a24Solivier moysan case STM_SAI_PDMCR_REGX: 12603e78a24Solivier moysan case STM_SAI_PDMLY_REGX: 1273e086edfSolivier moysan return true; 1283e086edfSolivier moysan default: 1293e086edfSolivier moysan return false; 1303e086edfSolivier moysan } 1313e086edfSolivier moysan } 1323e086edfSolivier moysan 1333e086edfSolivier moysan static bool stm32_sai_sub_volatile_reg(struct device *dev, unsigned int reg) 1343e086edfSolivier moysan { 1353e086edfSolivier moysan switch (reg) { 1363e086edfSolivier moysan case STM_SAI_DR_REGX: 1373e086edfSolivier moysan return true; 1383e086edfSolivier moysan default: 1393e086edfSolivier moysan return false; 1403e086edfSolivier moysan } 1413e086edfSolivier moysan } 1423e086edfSolivier moysan 1433e086edfSolivier moysan static bool stm32_sai_sub_writeable_reg(struct device *dev, unsigned int reg) 1443e086edfSolivier moysan { 1453e086edfSolivier moysan switch (reg) { 1463e086edfSolivier moysan case STM_SAI_CR1_REGX: 1473e086edfSolivier moysan case STM_SAI_CR2_REGX: 1483e086edfSolivier moysan case STM_SAI_FRCR_REGX: 1493e086edfSolivier moysan case STM_SAI_SLOTR_REGX: 1503e086edfSolivier moysan case STM_SAI_IMR_REGX: 1513e086edfSolivier moysan case STM_SAI_SR_REGX: 1523e086edfSolivier moysan case STM_SAI_CLRFR_REGX: 1533e086edfSolivier moysan case STM_SAI_DR_REGX: 15403e78a24Solivier moysan case STM_SAI_PDMCR_REGX: 15503e78a24Solivier moysan case STM_SAI_PDMLY_REGX: 1563e086edfSolivier moysan return true; 1573e086edfSolivier moysan default: 1583e086edfSolivier moysan return false; 1593e086edfSolivier moysan } 1603e086edfSolivier moysan } 1613e086edfSolivier moysan 16203e78a24Solivier moysan static const struct regmap_config stm32_sai_sub_regmap_config_f4 = { 1633e086edfSolivier moysan .reg_bits = 32, 1643e086edfSolivier moysan .reg_stride = 4, 1653e086edfSolivier moysan .val_bits = 32, 1663e086edfSolivier moysan .max_register = STM_SAI_DR_REGX, 1673e086edfSolivier moysan .readable_reg = stm32_sai_sub_readable_reg, 1683e086edfSolivier moysan .volatile_reg = stm32_sai_sub_volatile_reg, 1693e086edfSolivier moysan .writeable_reg = stm32_sai_sub_writeable_reg, 1703e086edfSolivier moysan .fast_io = true, 1713e086edfSolivier moysan }; 1723e086edfSolivier moysan 17303e78a24Solivier moysan static const struct regmap_config stm32_sai_sub_regmap_config_h7 = { 17403e78a24Solivier moysan .reg_bits = 32, 17503e78a24Solivier moysan .reg_stride = 4, 17603e78a24Solivier moysan .val_bits = 32, 17703e78a24Solivier moysan .max_register = STM_SAI_PDMLY_REGX, 17803e78a24Solivier moysan .readable_reg = stm32_sai_sub_readable_reg, 17903e78a24Solivier moysan .volatile_reg = stm32_sai_sub_volatile_reg, 18003e78a24Solivier moysan .writeable_reg = stm32_sai_sub_writeable_reg, 18103e78a24Solivier moysan .fast_io = true, 18203e78a24Solivier moysan }; 18303e78a24Solivier moysan 1843e086edfSolivier moysan static irqreturn_t stm32_sai_isr(int irq, void *devid) 1853e086edfSolivier moysan { 1863e086edfSolivier moysan struct stm32_sai_sub_data *sai = (struct stm32_sai_sub_data *)devid; 1873e086edfSolivier moysan struct platform_device *pdev = sai->pdev; 1883e086edfSolivier moysan unsigned int sr, imr, flags; 1893e086edfSolivier moysan snd_pcm_state_t status = SNDRV_PCM_STATE_RUNNING; 1903e086edfSolivier moysan 1913e086edfSolivier moysan regmap_read(sai->regmap, STM_SAI_IMR_REGX, &imr); 1923e086edfSolivier moysan regmap_read(sai->regmap, STM_SAI_SR_REGX, &sr); 1933e086edfSolivier moysan 1943e086edfSolivier moysan flags = sr & imr; 1953e086edfSolivier moysan if (!flags) 1963e086edfSolivier moysan return IRQ_NONE; 1973e086edfSolivier moysan 1983e086edfSolivier moysan regmap_update_bits(sai->regmap, STM_SAI_CLRFR_REGX, SAI_XCLRFR_MASK, 1993e086edfSolivier moysan SAI_XCLRFR_MASK); 2003e086edfSolivier moysan 201d807cdfbSOlivier Moysan if (!sai->substream) { 202d807cdfbSOlivier Moysan dev_err(&pdev->dev, "Device stopped. Spurious IRQ 0x%x\n", sr); 203d807cdfbSOlivier Moysan return IRQ_NONE; 204d807cdfbSOlivier Moysan } 205d807cdfbSOlivier Moysan 2063e086edfSolivier moysan if (flags & SAI_XIMR_OVRUDRIE) { 207602fdadcSolivier moysan dev_err(&pdev->dev, "IRQ %s\n", 2083e086edfSolivier moysan STM_SAI_IS_PLAYBACK(sai) ? "underrun" : "overrun"); 2093e086edfSolivier moysan status = SNDRV_PCM_STATE_XRUN; 2103e086edfSolivier moysan } 2113e086edfSolivier moysan 2123e086edfSolivier moysan if (flags & SAI_XIMR_MUTEDETIE) 213602fdadcSolivier moysan dev_dbg(&pdev->dev, "IRQ mute detected\n"); 2143e086edfSolivier moysan 2153e086edfSolivier moysan if (flags & SAI_XIMR_WCKCFGIE) { 216602fdadcSolivier moysan dev_err(&pdev->dev, "IRQ wrong clock configuration\n"); 2173e086edfSolivier moysan status = SNDRV_PCM_STATE_DISCONNECTED; 2183e086edfSolivier moysan } 2193e086edfSolivier moysan 2203e086edfSolivier moysan if (flags & SAI_XIMR_CNRDYIE) 221602fdadcSolivier moysan dev_err(&pdev->dev, "IRQ Codec not ready\n"); 2223e086edfSolivier moysan 2233e086edfSolivier moysan if (flags & SAI_XIMR_AFSDETIE) { 224602fdadcSolivier moysan dev_err(&pdev->dev, "IRQ Anticipated frame synchro\n"); 2253e086edfSolivier moysan status = SNDRV_PCM_STATE_XRUN; 2263e086edfSolivier moysan } 2273e086edfSolivier moysan 2283e086edfSolivier moysan if (flags & SAI_XIMR_LFSDETIE) { 229602fdadcSolivier moysan dev_err(&pdev->dev, "IRQ Late frame synchro\n"); 2303e086edfSolivier moysan status = SNDRV_PCM_STATE_XRUN; 2313e086edfSolivier moysan } 2323e086edfSolivier moysan 2333e086edfSolivier moysan if (status != SNDRV_PCM_STATE_RUNNING) { 234d807cdfbSOlivier Moysan snd_pcm_stream_lock(sai->substream); 235d807cdfbSOlivier Moysan snd_pcm_stop(sai->substream, SNDRV_PCM_STATE_XRUN); 236d807cdfbSOlivier Moysan snd_pcm_stream_unlock(sai->substream); 2373e086edfSolivier moysan } 2383e086edfSolivier moysan 2393e086edfSolivier moysan return IRQ_HANDLED; 2403e086edfSolivier moysan } 2413e086edfSolivier moysan 2423e086edfSolivier moysan static int stm32_sai_set_sysclk(struct snd_soc_dai *cpu_dai, 2433e086edfSolivier moysan int clk_id, unsigned int freq, int dir) 2443e086edfSolivier moysan { 2453e086edfSolivier moysan struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 246701a6ec3Solivier moysan int ret; 2473e086edfSolivier moysan 2483e086edfSolivier moysan if ((dir == SND_SOC_CLOCK_OUT) && sai->master) { 249701a6ec3Solivier moysan ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, 250701a6ec3Solivier moysan SAI_XCR1_NODIV, 251701a6ec3Solivier moysan (unsigned int)~SAI_XCR1_NODIV); 252701a6ec3Solivier moysan if (ret < 0) 253701a6ec3Solivier moysan return ret; 254701a6ec3Solivier moysan 2553e086edfSolivier moysan sai->mclk_rate = freq; 2563e086edfSolivier moysan dev_dbg(cpu_dai->dev, "SAI MCLK frequency is %uHz\n", freq); 2573e086edfSolivier moysan } 2583e086edfSolivier moysan 2593e086edfSolivier moysan return 0; 2603e086edfSolivier moysan } 2613e086edfSolivier moysan 2623e086edfSolivier moysan static int stm32_sai_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask, 2633e086edfSolivier moysan u32 rx_mask, int slots, int slot_width) 2643e086edfSolivier moysan { 2653e086edfSolivier moysan struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 2663e086edfSolivier moysan int slotr, slotr_mask, slot_size; 2673e086edfSolivier moysan 268602fdadcSolivier moysan dev_dbg(cpu_dai->dev, "Masks tx/rx:%#x/%#x, slots:%d, width:%d\n", 2693e086edfSolivier moysan tx_mask, rx_mask, slots, slot_width); 2703e086edfSolivier moysan 2713e086edfSolivier moysan switch (slot_width) { 2723e086edfSolivier moysan case 16: 2733e086edfSolivier moysan slot_size = SAI_SLOT_SIZE_16; 2743e086edfSolivier moysan break; 2753e086edfSolivier moysan case 32: 2763e086edfSolivier moysan slot_size = SAI_SLOT_SIZE_32; 2773e086edfSolivier moysan break; 2783e086edfSolivier moysan default: 2793e086edfSolivier moysan slot_size = SAI_SLOT_SIZE_AUTO; 2803e086edfSolivier moysan break; 2813e086edfSolivier moysan } 2823e086edfSolivier moysan 2833e086edfSolivier moysan slotr = SAI_XSLOTR_SLOTSZ_SET(slot_size) | 2843e086edfSolivier moysan SAI_XSLOTR_NBSLOT_SET(slots - 1); 2853e086edfSolivier moysan slotr_mask = SAI_XSLOTR_SLOTSZ_MASK | SAI_XSLOTR_NBSLOT_MASK; 2863e086edfSolivier moysan 2873e086edfSolivier moysan /* tx/rx mask set in machine init, if slot number defined in DT */ 2883e086edfSolivier moysan if (STM_SAI_IS_PLAYBACK(sai)) { 2893e086edfSolivier moysan sai->slot_mask = tx_mask; 2903e086edfSolivier moysan slotr |= SAI_XSLOTR_SLOTEN_SET(tx_mask); 2913e086edfSolivier moysan } 2923e086edfSolivier moysan 2933e086edfSolivier moysan if (STM_SAI_IS_CAPTURE(sai)) { 2943e086edfSolivier moysan sai->slot_mask = rx_mask; 2953e086edfSolivier moysan slotr |= SAI_XSLOTR_SLOTEN_SET(rx_mask); 2963e086edfSolivier moysan } 2973e086edfSolivier moysan 2983e086edfSolivier moysan slotr_mask |= SAI_XSLOTR_SLOTEN_MASK; 2993e086edfSolivier moysan 3003e086edfSolivier moysan regmap_update_bits(sai->regmap, STM_SAI_SLOTR_REGX, slotr_mask, slotr); 3013e086edfSolivier moysan 3023e086edfSolivier moysan sai->slot_width = slot_width; 3033e086edfSolivier moysan sai->slots = slots; 3043e086edfSolivier moysan 3053e086edfSolivier moysan return 0; 3063e086edfSolivier moysan } 3073e086edfSolivier moysan 3083e086edfSolivier moysan static int stm32_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) 3093e086edfSolivier moysan { 3103e086edfSolivier moysan struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 31161fb4ff7SOlivier Moysan int cr1, frcr = 0; 31261fb4ff7SOlivier Moysan int cr1_mask, frcr_mask = 0; 3133e086edfSolivier moysan int ret; 3143e086edfSolivier moysan 3153e086edfSolivier moysan dev_dbg(cpu_dai->dev, "fmt %x\n", fmt); 3163e086edfSolivier moysan 31761fb4ff7SOlivier Moysan cr1_mask = SAI_XCR1_PRTCFG_MASK; 31861fb4ff7SOlivier Moysan cr1 = SAI_XCR1_PRTCFG_SET(SAI_FREE_PROTOCOL); 31961fb4ff7SOlivier Moysan 3203e086edfSolivier moysan switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 3213e086edfSolivier moysan /* SCK active high for all protocols */ 3223e086edfSolivier moysan case SND_SOC_DAIFMT_I2S: 3233e086edfSolivier moysan cr1 |= SAI_XCR1_CKSTR; 3243e086edfSolivier moysan frcr |= SAI_XFRCR_FSOFF | SAI_XFRCR_FSDEF; 3253e086edfSolivier moysan break; 3263e086edfSolivier moysan /* Left justified */ 3273e086edfSolivier moysan case SND_SOC_DAIFMT_MSB: 3283e086edfSolivier moysan frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSDEF; 3293e086edfSolivier moysan break; 3303e086edfSolivier moysan /* Right justified */ 3313e086edfSolivier moysan case SND_SOC_DAIFMT_LSB: 3323e086edfSolivier moysan frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSDEF; 3333e086edfSolivier moysan break; 3343e086edfSolivier moysan case SND_SOC_DAIFMT_DSP_A: 3353e086edfSolivier moysan frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSOFF; 3363e086edfSolivier moysan break; 3373e086edfSolivier moysan case SND_SOC_DAIFMT_DSP_B: 3383e086edfSolivier moysan frcr |= SAI_XFRCR_FSPOL; 3393e086edfSolivier moysan break; 3403e086edfSolivier moysan default: 3413e086edfSolivier moysan dev_err(cpu_dai->dev, "Unsupported protocol %#x\n", 3423e086edfSolivier moysan fmt & SND_SOC_DAIFMT_FORMAT_MASK); 3433e086edfSolivier moysan return -EINVAL; 3443e086edfSolivier moysan } 3453e086edfSolivier moysan 34661fb4ff7SOlivier Moysan cr1_mask |= SAI_XCR1_CKSTR; 3473e086edfSolivier moysan frcr_mask |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSOFF | 3483e086edfSolivier moysan SAI_XFRCR_FSDEF; 3493e086edfSolivier moysan 3503e086edfSolivier moysan /* DAI clock strobing. Invert setting previously set */ 3513e086edfSolivier moysan switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 3523e086edfSolivier moysan case SND_SOC_DAIFMT_NB_NF: 3533e086edfSolivier moysan break; 3543e086edfSolivier moysan case SND_SOC_DAIFMT_IB_NF: 3553e086edfSolivier moysan cr1 ^= SAI_XCR1_CKSTR; 3563e086edfSolivier moysan break; 3573e086edfSolivier moysan case SND_SOC_DAIFMT_NB_IF: 3583e086edfSolivier moysan frcr ^= SAI_XFRCR_FSPOL; 3593e086edfSolivier moysan break; 3603e086edfSolivier moysan case SND_SOC_DAIFMT_IB_IF: 3613e086edfSolivier moysan /* Invert fs & sck */ 3623e086edfSolivier moysan cr1 ^= SAI_XCR1_CKSTR; 3633e086edfSolivier moysan frcr ^= SAI_XFRCR_FSPOL; 3643e086edfSolivier moysan break; 3653e086edfSolivier moysan default: 3663e086edfSolivier moysan dev_err(cpu_dai->dev, "Unsupported strobing %#x\n", 3673e086edfSolivier moysan fmt & SND_SOC_DAIFMT_INV_MASK); 3683e086edfSolivier moysan return -EINVAL; 3693e086edfSolivier moysan } 3703e086edfSolivier moysan cr1_mask |= SAI_XCR1_CKSTR; 3713e086edfSolivier moysan frcr_mask |= SAI_XFRCR_FSPOL; 3723e086edfSolivier moysan 3733e086edfSolivier moysan regmap_update_bits(sai->regmap, STM_SAI_FRCR_REGX, frcr_mask, frcr); 3743e086edfSolivier moysan 3753e086edfSolivier moysan /* DAI clock master masks */ 3763e086edfSolivier moysan switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 3773e086edfSolivier moysan case SND_SOC_DAIFMT_CBM_CFM: 3783e086edfSolivier moysan /* codec is master */ 3793e086edfSolivier moysan cr1 |= SAI_XCR1_SLAVE; 3803e086edfSolivier moysan sai->master = false; 3813e086edfSolivier moysan break; 3823e086edfSolivier moysan case SND_SOC_DAIFMT_CBS_CFS: 3833e086edfSolivier moysan sai->master = true; 3843e086edfSolivier moysan break; 3853e086edfSolivier moysan default: 3863e086edfSolivier moysan dev_err(cpu_dai->dev, "Unsupported mode %#x\n", 3873e086edfSolivier moysan fmt & SND_SOC_DAIFMT_MASTER_MASK); 3883e086edfSolivier moysan return -EINVAL; 3893e086edfSolivier moysan } 3903e086edfSolivier moysan cr1_mask |= SAI_XCR1_SLAVE; 3913e086edfSolivier moysan 392701a6ec3Solivier moysan /* do not generate master by default */ 393701a6ec3Solivier moysan cr1 |= SAI_XCR1_NODIV; 394701a6ec3Solivier moysan cr1_mask |= SAI_XCR1_NODIV; 395701a6ec3Solivier moysan 3963e086edfSolivier moysan ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, cr1_mask, cr1); 3973e086edfSolivier moysan if (ret < 0) { 3983e086edfSolivier moysan dev_err(cpu_dai->dev, "Failed to update CR1 register\n"); 3993e086edfSolivier moysan return ret; 4003e086edfSolivier moysan } 4013e086edfSolivier moysan 4023e086edfSolivier moysan sai->fmt = fmt; 4033e086edfSolivier moysan 4043e086edfSolivier moysan return 0; 4053e086edfSolivier moysan } 4063e086edfSolivier moysan 4073e086edfSolivier moysan static int stm32_sai_startup(struct snd_pcm_substream *substream, 4083e086edfSolivier moysan struct snd_soc_dai *cpu_dai) 4093e086edfSolivier moysan { 4103e086edfSolivier moysan struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 4113e086edfSolivier moysan int imr, cr2, ret; 4123e086edfSolivier moysan 4133e086edfSolivier moysan sai->substream = substream; 4143e086edfSolivier moysan 4153e086edfSolivier moysan ret = clk_prepare_enable(sai->sai_ck); 4163e086edfSolivier moysan if (ret < 0) { 417602fdadcSolivier moysan dev_err(cpu_dai->dev, "Failed to enable clock: %d\n", ret); 4183e086edfSolivier moysan return ret; 4193e086edfSolivier moysan } 4203e086edfSolivier moysan 4213e086edfSolivier moysan /* Enable ITs */ 4223e086edfSolivier moysan 4233e086edfSolivier moysan regmap_update_bits(sai->regmap, STM_SAI_CLRFR_REGX, 4243e086edfSolivier moysan SAI_XCLRFR_MASK, SAI_XCLRFR_MASK); 4253e086edfSolivier moysan 4263e086edfSolivier moysan imr = SAI_XIMR_OVRUDRIE; 4273e086edfSolivier moysan if (STM_SAI_IS_CAPTURE(sai)) { 4283e086edfSolivier moysan regmap_read(sai->regmap, STM_SAI_CR2_REGX, &cr2); 4293e086edfSolivier moysan if (cr2 & SAI_XCR2_MUTECNT_MASK) 4303e086edfSolivier moysan imr |= SAI_XIMR_MUTEDETIE; 4313e086edfSolivier moysan } 4323e086edfSolivier moysan 4333e086edfSolivier moysan if (sai->master) 4343e086edfSolivier moysan imr |= SAI_XIMR_WCKCFGIE; 4353e086edfSolivier moysan else 4363e086edfSolivier moysan imr |= SAI_XIMR_AFSDETIE | SAI_XIMR_LFSDETIE; 4373e086edfSolivier moysan 4383e086edfSolivier moysan regmap_update_bits(sai->regmap, STM_SAI_IMR_REGX, 4393e086edfSolivier moysan SAI_XIMR_MASK, imr); 4403e086edfSolivier moysan 4413e086edfSolivier moysan return 0; 4423e086edfSolivier moysan } 4433e086edfSolivier moysan 4443e086edfSolivier moysan static int stm32_sai_set_config(struct snd_soc_dai *cpu_dai, 4453e086edfSolivier moysan struct snd_pcm_substream *substream, 4463e086edfSolivier moysan struct snd_pcm_hw_params *params) 4473e086edfSolivier moysan { 4483e086edfSolivier moysan struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 4493e086edfSolivier moysan int cr1, cr1_mask, ret; 4503e086edfSolivier moysan 451a4529d2bSOlivier Moysan /* 452a4529d2bSOlivier Moysan * DMA bursts increment is set to 4 words. 453a4529d2bSOlivier Moysan * SAI fifo threshold is set to half fifo, to keep enough space 454a4529d2bSOlivier Moysan * for DMA incoming bursts. 455a4529d2bSOlivier Moysan */ 4563e086edfSolivier moysan regmap_update_bits(sai->regmap, STM_SAI_CR2_REGX, 4573e086edfSolivier moysan SAI_XCR2_FFLUSH | SAI_XCR2_FTH_MASK, 458a4529d2bSOlivier Moysan SAI_XCR2_FFLUSH | 459a4529d2bSOlivier Moysan SAI_XCR2_FTH_SET(STM_SAI_FIFO_TH_HALF)); 4603e086edfSolivier moysan 4613e086edfSolivier moysan /* Mode, data format and channel config */ 46261fb4ff7SOlivier Moysan cr1_mask = SAI_XCR1_DS_MASK; 4633e086edfSolivier moysan switch (params_format(params)) { 4643e086edfSolivier moysan case SNDRV_PCM_FORMAT_S8: 4653e086edfSolivier moysan cr1 |= SAI_XCR1_DS_SET(SAI_DATASIZE_8); 4663e086edfSolivier moysan break; 4673e086edfSolivier moysan case SNDRV_PCM_FORMAT_S16_LE: 4683e086edfSolivier moysan cr1 |= SAI_XCR1_DS_SET(SAI_DATASIZE_16); 4693e086edfSolivier moysan break; 4703e086edfSolivier moysan case SNDRV_PCM_FORMAT_S32_LE: 4713e086edfSolivier moysan cr1 |= SAI_XCR1_DS_SET(SAI_DATASIZE_32); 4723e086edfSolivier moysan break; 4733e086edfSolivier moysan default: 4743e086edfSolivier moysan dev_err(cpu_dai->dev, "Data format not supported"); 4753e086edfSolivier moysan return -EINVAL; 4763e086edfSolivier moysan } 4773e086edfSolivier moysan 4783e086edfSolivier moysan cr1_mask |= SAI_XCR1_MONO; 4793e086edfSolivier moysan if ((sai->slots == 2) && (params_channels(params) == 1)) 4803e086edfSolivier moysan cr1 |= SAI_XCR1_MONO; 4813e086edfSolivier moysan 4823e086edfSolivier moysan ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, cr1_mask, cr1); 4833e086edfSolivier moysan if (ret < 0) { 4843e086edfSolivier moysan dev_err(cpu_dai->dev, "Failed to update CR1 register\n"); 4853e086edfSolivier moysan return ret; 4863e086edfSolivier moysan } 4873e086edfSolivier moysan 4883e086edfSolivier moysan return 0; 4893e086edfSolivier moysan } 4903e086edfSolivier moysan 4913e086edfSolivier moysan static int stm32_sai_set_slots(struct snd_soc_dai *cpu_dai) 4923e086edfSolivier moysan { 4933e086edfSolivier moysan struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 4943e086edfSolivier moysan int slotr, slot_sz; 4953e086edfSolivier moysan 4963e086edfSolivier moysan regmap_read(sai->regmap, STM_SAI_SLOTR_REGX, &slotr); 4973e086edfSolivier moysan 4983e086edfSolivier moysan /* 4993e086edfSolivier moysan * If SLOTSZ is set to auto in SLOTR, align slot width on data size 5003e086edfSolivier moysan * By default slot width = data size, if not forced from DT 5013e086edfSolivier moysan */ 5023e086edfSolivier moysan slot_sz = slotr & SAI_XSLOTR_SLOTSZ_MASK; 5033e086edfSolivier moysan if (slot_sz == SAI_XSLOTR_SLOTSZ_SET(SAI_SLOT_SIZE_AUTO)) 5043e086edfSolivier moysan sai->slot_width = sai->data_size; 5053e086edfSolivier moysan 5063e086edfSolivier moysan if (sai->slot_width < sai->data_size) { 5073e086edfSolivier moysan dev_err(cpu_dai->dev, 5083e086edfSolivier moysan "Data size %d larger than slot width\n", 5093e086edfSolivier moysan sai->data_size); 5103e086edfSolivier moysan return -EINVAL; 5113e086edfSolivier moysan } 5123e086edfSolivier moysan 5133e086edfSolivier moysan /* Slot number is set to 2, if not specified in DT */ 5143e086edfSolivier moysan if (!sai->slots) 5153e086edfSolivier moysan sai->slots = 2; 5163e086edfSolivier moysan 5173e086edfSolivier moysan /* The number of slots in the audio frame is equal to NBSLOT[3:0] + 1*/ 5183e086edfSolivier moysan regmap_update_bits(sai->regmap, STM_SAI_SLOTR_REGX, 5193e086edfSolivier moysan SAI_XSLOTR_NBSLOT_MASK, 5203e086edfSolivier moysan SAI_XSLOTR_NBSLOT_SET((sai->slots - 1))); 5213e086edfSolivier moysan 5223e086edfSolivier moysan /* Set default slots mask if not already set from DT */ 5233e086edfSolivier moysan if (!(slotr & SAI_XSLOTR_SLOTEN_MASK)) { 5243e086edfSolivier moysan sai->slot_mask = (1 << sai->slots) - 1; 5253e086edfSolivier moysan regmap_update_bits(sai->regmap, 5263e086edfSolivier moysan STM_SAI_SLOTR_REGX, SAI_XSLOTR_SLOTEN_MASK, 5273e086edfSolivier moysan SAI_XSLOTR_SLOTEN_SET(sai->slot_mask)); 5283e086edfSolivier moysan } 5293e086edfSolivier moysan 530602fdadcSolivier moysan dev_dbg(cpu_dai->dev, "Slots %d, slot width %d\n", 5313e086edfSolivier moysan sai->slots, sai->slot_width); 5323e086edfSolivier moysan 5333e086edfSolivier moysan return 0; 5343e086edfSolivier moysan } 5353e086edfSolivier moysan 5363e086edfSolivier moysan static void stm32_sai_set_frame(struct snd_soc_dai *cpu_dai) 5373e086edfSolivier moysan { 5383e086edfSolivier moysan struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 5393e086edfSolivier moysan int fs_active, offset, format; 5403e086edfSolivier moysan int frcr, frcr_mask; 5413e086edfSolivier moysan 5423e086edfSolivier moysan format = sai->fmt & SND_SOC_DAIFMT_FORMAT_MASK; 5433e086edfSolivier moysan sai->fs_length = sai->slot_width * sai->slots; 5443e086edfSolivier moysan 5453e086edfSolivier moysan fs_active = sai->fs_length / 2; 5463e086edfSolivier moysan if ((format == SND_SOC_DAIFMT_DSP_A) || 5473e086edfSolivier moysan (format == SND_SOC_DAIFMT_DSP_B)) 5483e086edfSolivier moysan fs_active = 1; 5493e086edfSolivier moysan 5503e086edfSolivier moysan frcr = SAI_XFRCR_FRL_SET((sai->fs_length - 1)); 5513e086edfSolivier moysan frcr |= SAI_XFRCR_FSALL_SET((fs_active - 1)); 5523e086edfSolivier moysan frcr_mask = SAI_XFRCR_FRL_MASK | SAI_XFRCR_FSALL_MASK; 5533e086edfSolivier moysan 554602fdadcSolivier moysan dev_dbg(cpu_dai->dev, "Frame length %d, frame active %d\n", 5553e086edfSolivier moysan sai->fs_length, fs_active); 5563e086edfSolivier moysan 5573e086edfSolivier moysan regmap_update_bits(sai->regmap, STM_SAI_FRCR_REGX, frcr_mask, frcr); 5583e086edfSolivier moysan 5593e086edfSolivier moysan if ((sai->fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_LSB) { 5603e086edfSolivier moysan offset = sai->slot_width - sai->data_size; 5613e086edfSolivier moysan 5623e086edfSolivier moysan regmap_update_bits(sai->regmap, STM_SAI_SLOTR_REGX, 5633e086edfSolivier moysan SAI_XSLOTR_FBOFF_MASK, 5643e086edfSolivier moysan SAI_XSLOTR_FBOFF_SET(offset)); 5653e086edfSolivier moysan } 5663e086edfSolivier moysan } 5673e086edfSolivier moysan 5683e086edfSolivier moysan static int stm32_sai_configure_clock(struct snd_soc_dai *cpu_dai, 5693e086edfSolivier moysan struct snd_pcm_hw_params *params) 5703e086edfSolivier moysan { 5713e086edfSolivier moysan struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 5723e086edfSolivier moysan int cr1, mask, div = 0; 57303e78a24Solivier moysan int sai_clk_rate, mclk_ratio, den, ret; 57403e78a24Solivier moysan int version = sai->pdata->conf->version; 5753e086edfSolivier moysan 5763e086edfSolivier moysan if (!sai->mclk_rate) { 5773e086edfSolivier moysan dev_err(cpu_dai->dev, "Mclk rate is null\n"); 5783e086edfSolivier moysan return -EINVAL; 5793e086edfSolivier moysan } 5803e086edfSolivier moysan 5813e086edfSolivier moysan if (!(params_rate(params) % 11025)) 5823e086edfSolivier moysan clk_set_parent(sai->sai_ck, sai->pdata->clk_x11k); 5833e086edfSolivier moysan else 5843e086edfSolivier moysan clk_set_parent(sai->sai_ck, sai->pdata->clk_x8k); 5853e086edfSolivier moysan sai_clk_rate = clk_get_rate(sai->sai_ck); 5863e086edfSolivier moysan 58703e78a24Solivier moysan if (STM_SAI_IS_F4(sai->pdata)) { 5883e086edfSolivier moysan /* 5893e086edfSolivier moysan * mclk_rate = 256 * fs 5903e086edfSolivier moysan * MCKDIV = 0 if sai_ck < 3/2 * mclk_rate 5913e086edfSolivier moysan * MCKDIV = sai_ck / (2 * mclk_rate) otherwise 5923e086edfSolivier moysan */ 5933e086edfSolivier moysan if (2 * sai_clk_rate >= 3 * sai->mclk_rate) 59403e78a24Solivier moysan div = DIV_ROUND_CLOSEST(sai_clk_rate, 59503e78a24Solivier moysan 2 * sai->mclk_rate); 59603e78a24Solivier moysan } else { 59703e78a24Solivier moysan /* 59803e78a24Solivier moysan * TDM mode : 59903e78a24Solivier moysan * mclk on 60003e78a24Solivier moysan * MCKDIV = sai_ck / (ws x 256) (NOMCK=0. OSR=0) 60103e78a24Solivier moysan * MCKDIV = sai_ck / (ws x 512) (NOMCK=0. OSR=1) 60203e78a24Solivier moysan * mclk off 60303e78a24Solivier moysan * MCKDIV = sai_ck / (frl x ws) (NOMCK=1) 60403e78a24Solivier moysan * Note: NOMCK/NODIV correspond to same bit. 60503e78a24Solivier moysan */ 60603e78a24Solivier moysan if (sai->mclk_rate) { 60703e78a24Solivier moysan mclk_ratio = sai->mclk_rate / params_rate(params); 60803e78a24Solivier moysan if (mclk_ratio != 256) { 60903e78a24Solivier moysan if (mclk_ratio == 512) { 61003e78a24Solivier moysan mask = SAI_XCR1_OSR; 61103e78a24Solivier moysan cr1 = SAI_XCR1_OSR; 61203e78a24Solivier moysan } else { 61303e78a24Solivier moysan dev_err(cpu_dai->dev, 61403e78a24Solivier moysan "Wrong mclk ratio %d\n", 61503e78a24Solivier moysan mclk_ratio); 61603e78a24Solivier moysan return -EINVAL; 61703e78a24Solivier moysan } 61803e78a24Solivier moysan } 61903e78a24Solivier moysan div = DIV_ROUND_CLOSEST(sai_clk_rate, sai->mclk_rate); 62003e78a24Solivier moysan } else { 62103e78a24Solivier moysan /* mclk-fs not set, master clock not active. NOMCK=1 */ 62203e78a24Solivier moysan den = sai->fs_length * params_rate(params); 62303e78a24Solivier moysan div = DIV_ROUND_CLOSEST(sai_clk_rate, den); 62403e78a24Solivier moysan } 62503e78a24Solivier moysan } 6263e086edfSolivier moysan 62703e78a24Solivier moysan if (div > SAI_XCR1_MCKDIV_MAX(version)) { 6283e086edfSolivier moysan dev_err(cpu_dai->dev, "Divider %d out of range\n", div); 6293e086edfSolivier moysan return -EINVAL; 6303e086edfSolivier moysan } 6313e086edfSolivier moysan dev_dbg(cpu_dai->dev, "SAI clock %d, divider %d\n", sai_clk_rate, div); 6323e086edfSolivier moysan 63303e78a24Solivier moysan mask = SAI_XCR1_MCKDIV_MASK(SAI_XCR1_MCKDIV_WIDTH(version)); 6343e086edfSolivier moysan cr1 = SAI_XCR1_MCKDIV_SET(div); 6353e086edfSolivier moysan ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, mask, cr1); 6363e086edfSolivier moysan if (ret < 0) { 6373e086edfSolivier moysan dev_err(cpu_dai->dev, "Failed to update CR1 register\n"); 6383e086edfSolivier moysan return ret; 6393e086edfSolivier moysan } 6403e086edfSolivier moysan 6413e086edfSolivier moysan return 0; 6423e086edfSolivier moysan } 6433e086edfSolivier moysan 6443e086edfSolivier moysan static int stm32_sai_hw_params(struct snd_pcm_substream *substream, 6453e086edfSolivier moysan struct snd_pcm_hw_params *params, 6463e086edfSolivier moysan struct snd_soc_dai *cpu_dai) 6473e086edfSolivier moysan { 6483e086edfSolivier moysan struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 6493e086edfSolivier moysan int ret; 6503e086edfSolivier moysan 6513e086edfSolivier moysan sai->data_size = params_width(params); 6523e086edfSolivier moysan 6533e086edfSolivier moysan ret = stm32_sai_set_slots(cpu_dai); 6543e086edfSolivier moysan if (ret < 0) 6553e086edfSolivier moysan return ret; 6563e086edfSolivier moysan stm32_sai_set_frame(cpu_dai); 6573e086edfSolivier moysan 6583e086edfSolivier moysan ret = stm32_sai_set_config(cpu_dai, substream, params); 6593e086edfSolivier moysan if (ret) 6603e086edfSolivier moysan return ret; 6613e086edfSolivier moysan 6623e086edfSolivier moysan if (sai->master) 6633e086edfSolivier moysan ret = stm32_sai_configure_clock(cpu_dai, params); 6643e086edfSolivier moysan 6653e086edfSolivier moysan return ret; 6663e086edfSolivier moysan } 6673e086edfSolivier moysan 6683e086edfSolivier moysan static int stm32_sai_trigger(struct snd_pcm_substream *substream, int cmd, 6693e086edfSolivier moysan struct snd_soc_dai *cpu_dai) 6703e086edfSolivier moysan { 6713e086edfSolivier moysan struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 6723e086edfSolivier moysan int ret; 6733e086edfSolivier moysan 6743e086edfSolivier moysan switch (cmd) { 6753e086edfSolivier moysan case SNDRV_PCM_TRIGGER_START: 6763e086edfSolivier moysan case SNDRV_PCM_TRIGGER_RESUME: 6773e086edfSolivier moysan case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 6783e086edfSolivier moysan dev_dbg(cpu_dai->dev, "Enable DMA and SAI\n"); 6793e086edfSolivier moysan 6803e086edfSolivier moysan regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, 6813e086edfSolivier moysan SAI_XCR1_DMAEN, SAI_XCR1_DMAEN); 6823e086edfSolivier moysan 6833e086edfSolivier moysan /* Enable SAI */ 6843e086edfSolivier moysan ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, 6853e086edfSolivier moysan SAI_XCR1_SAIEN, SAI_XCR1_SAIEN); 6863e086edfSolivier moysan if (ret < 0) 6873e086edfSolivier moysan dev_err(cpu_dai->dev, "Failed to update CR1 register\n"); 6883e086edfSolivier moysan break; 6893e086edfSolivier moysan case SNDRV_PCM_TRIGGER_SUSPEND: 6903e086edfSolivier moysan case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 6913e086edfSolivier moysan case SNDRV_PCM_TRIGGER_STOP: 6923e086edfSolivier moysan dev_dbg(cpu_dai->dev, "Disable DMA and SAI\n"); 6933e086edfSolivier moysan 69447a8907dSOlivier Moysan regmap_update_bits(sai->regmap, STM_SAI_IMR_REGX, 69547a8907dSOlivier Moysan SAI_XIMR_MASK, 0); 69647a8907dSOlivier Moysan 6973e086edfSolivier moysan regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, 6983e086edfSolivier moysan SAI_XCR1_SAIEN, 6993e086edfSolivier moysan (unsigned int)~SAI_XCR1_SAIEN); 7004fa17938Solivier moysan 7014fa17938Solivier moysan ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, 7024fa17938Solivier moysan SAI_XCR1_DMAEN, 7034fa17938Solivier moysan (unsigned int)~SAI_XCR1_DMAEN); 7043e086edfSolivier moysan if (ret < 0) 7053e086edfSolivier moysan dev_err(cpu_dai->dev, "Failed to update CR1 register\n"); 7063e086edfSolivier moysan break; 7073e086edfSolivier moysan default: 7083e086edfSolivier moysan return -EINVAL; 7093e086edfSolivier moysan } 7103e086edfSolivier moysan 7113e086edfSolivier moysan return ret; 7123e086edfSolivier moysan } 7133e086edfSolivier moysan 7143e086edfSolivier moysan static void stm32_sai_shutdown(struct snd_pcm_substream *substream, 7153e086edfSolivier moysan struct snd_soc_dai *cpu_dai) 7163e086edfSolivier moysan { 7173e086edfSolivier moysan struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 7183e086edfSolivier moysan 7193e086edfSolivier moysan regmap_update_bits(sai->regmap, STM_SAI_IMR_REGX, SAI_XIMR_MASK, 0); 7203e086edfSolivier moysan 721701a6ec3Solivier moysan regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, SAI_XCR1_NODIV, 722701a6ec3Solivier moysan SAI_XCR1_NODIV); 723701a6ec3Solivier moysan 7243e086edfSolivier moysan clk_disable_unprepare(sai->sai_ck); 7253e086edfSolivier moysan sai->substream = NULL; 7263e086edfSolivier moysan } 7273e086edfSolivier moysan 7283e086edfSolivier moysan static int stm32_sai_dai_probe(struct snd_soc_dai *cpu_dai) 7293e086edfSolivier moysan { 7303e086edfSolivier moysan struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev); 73161fb4ff7SOlivier Moysan int cr1 = 0, cr1_mask; 7323e086edfSolivier moysan 7333e086edfSolivier moysan sai->dma_params.addr = (dma_addr_t)(sai->phys_addr + STM_SAI_DR_REGX); 734a4529d2bSOlivier Moysan /* 735a4529d2bSOlivier Moysan * DMA supports 4, 8 or 16 burst sizes. Burst size 4 is the best choice, 736a4529d2bSOlivier Moysan * as it allows bytes, half-word and words transfers. (See DMA fifos 737a4529d2bSOlivier Moysan * constraints). 738a4529d2bSOlivier Moysan */ 739a4529d2bSOlivier Moysan sai->dma_params.maxburst = 4; 7403e086edfSolivier moysan /* Buswidth will be set by framework at runtime */ 7413e086edfSolivier moysan sai->dma_params.addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED; 7423e086edfSolivier moysan 7433e086edfSolivier moysan if (STM_SAI_IS_PLAYBACK(sai)) 7443e086edfSolivier moysan snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params, NULL); 7453e086edfSolivier moysan else 7463e086edfSolivier moysan snd_soc_dai_init_dma_data(cpu_dai, NULL, &sai->dma_params); 7473e086edfSolivier moysan 74861fb4ff7SOlivier Moysan cr1_mask = SAI_XCR1_RX_TX; 74961fb4ff7SOlivier Moysan if (STM_SAI_IS_CAPTURE(sai)) 75061fb4ff7SOlivier Moysan cr1 |= SAI_XCR1_RX_TX; 75161fb4ff7SOlivier Moysan 75261fb4ff7SOlivier Moysan return regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, cr1_mask, cr1); 7533e086edfSolivier moysan } 7543e086edfSolivier moysan 7553e086edfSolivier moysan static const struct snd_soc_dai_ops stm32_sai_pcm_dai_ops = { 7563e086edfSolivier moysan .set_sysclk = stm32_sai_set_sysclk, 7573e086edfSolivier moysan .set_fmt = stm32_sai_set_dai_fmt, 7583e086edfSolivier moysan .set_tdm_slot = stm32_sai_set_dai_tdm_slot, 7593e086edfSolivier moysan .startup = stm32_sai_startup, 7603e086edfSolivier moysan .hw_params = stm32_sai_hw_params, 7613e086edfSolivier moysan .trigger = stm32_sai_trigger, 7623e086edfSolivier moysan .shutdown = stm32_sai_shutdown, 7633e086edfSolivier moysan }; 7643e086edfSolivier moysan 7653e086edfSolivier moysan static const struct snd_pcm_hardware stm32_sai_pcm_hw = { 7663e086edfSolivier moysan .info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP, 7673e086edfSolivier moysan .buffer_bytes_max = 8 * PAGE_SIZE, 7683e086edfSolivier moysan .period_bytes_min = 1024, /* 5ms at 48kHz */ 7693e086edfSolivier moysan .period_bytes_max = PAGE_SIZE, 7703e086edfSolivier moysan .periods_min = 2, 7713e086edfSolivier moysan .periods_max = 8, 7723e086edfSolivier moysan }; 7733e086edfSolivier moysan 7743e086edfSolivier moysan static struct snd_soc_dai_driver stm32_sai_playback_dai[] = { 7753e086edfSolivier moysan { 7763e086edfSolivier moysan .probe = stm32_sai_dai_probe, 7773e086edfSolivier moysan .id = 1, /* avoid call to fmt_single_name() */ 7783e086edfSolivier moysan .playback = { 7793e086edfSolivier moysan .channels_min = 1, 7803e086edfSolivier moysan .channels_max = 2, 7813e086edfSolivier moysan .rate_min = 8000, 7823e086edfSolivier moysan .rate_max = 192000, 7833e086edfSolivier moysan .rates = SNDRV_PCM_RATE_CONTINUOUS, 7843e086edfSolivier moysan /* DMA does not support 24 bits transfers */ 7853e086edfSolivier moysan .formats = 7863e086edfSolivier moysan SNDRV_PCM_FMTBIT_S8 | 7873e086edfSolivier moysan SNDRV_PCM_FMTBIT_S16_LE | 7883e086edfSolivier moysan SNDRV_PCM_FMTBIT_S32_LE, 7893e086edfSolivier moysan }, 7903e086edfSolivier moysan .ops = &stm32_sai_pcm_dai_ops, 7913e086edfSolivier moysan } 7923e086edfSolivier moysan }; 7933e086edfSolivier moysan 7943e086edfSolivier moysan static struct snd_soc_dai_driver stm32_sai_capture_dai[] = { 7953e086edfSolivier moysan { 7963e086edfSolivier moysan .probe = stm32_sai_dai_probe, 7973e086edfSolivier moysan .id = 1, /* avoid call to fmt_single_name() */ 7983e086edfSolivier moysan .capture = { 7993e086edfSolivier moysan .channels_min = 1, 8003e086edfSolivier moysan .channels_max = 2, 8013e086edfSolivier moysan .rate_min = 8000, 8023e086edfSolivier moysan .rate_max = 192000, 8033e086edfSolivier moysan .rates = SNDRV_PCM_RATE_CONTINUOUS, 8043e086edfSolivier moysan /* DMA does not support 24 bits transfers */ 8053e086edfSolivier moysan .formats = 8063e086edfSolivier moysan SNDRV_PCM_FMTBIT_S8 | 8073e086edfSolivier moysan SNDRV_PCM_FMTBIT_S16_LE | 8083e086edfSolivier moysan SNDRV_PCM_FMTBIT_S32_LE, 8093e086edfSolivier moysan }, 8103e086edfSolivier moysan .ops = &stm32_sai_pcm_dai_ops, 8113e086edfSolivier moysan } 8123e086edfSolivier moysan }; 8133e086edfSolivier moysan 8143e086edfSolivier moysan static const struct snd_dmaengine_pcm_config stm32_sai_pcm_config = { 8153e086edfSolivier moysan .pcm_hardware = &stm32_sai_pcm_hw, 8163e086edfSolivier moysan .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, 8173e086edfSolivier moysan }; 8183e086edfSolivier moysan 8193e086edfSolivier moysan static const struct snd_soc_component_driver stm32_component = { 8203e086edfSolivier moysan .name = "stm32-sai", 8213e086edfSolivier moysan }; 8223e086edfSolivier moysan 8233e086edfSolivier moysan static const struct of_device_id stm32_sai_sub_ids[] = { 8243e086edfSolivier moysan { .compatible = "st,stm32-sai-sub-a", 8253e086edfSolivier moysan .data = (void *)STM_SAI_A_ID}, 8263e086edfSolivier moysan { .compatible = "st,stm32-sai-sub-b", 8273e086edfSolivier moysan .data = (void *)STM_SAI_B_ID}, 8283e086edfSolivier moysan {} 8293e086edfSolivier moysan }; 8303e086edfSolivier moysan MODULE_DEVICE_TABLE(of, stm32_sai_sub_ids); 8313e086edfSolivier moysan 8323e086edfSolivier moysan static int stm32_sai_sub_parse_of(struct platform_device *pdev, 8333e086edfSolivier moysan struct stm32_sai_sub_data *sai) 8343e086edfSolivier moysan { 8353e086edfSolivier moysan struct device_node *np = pdev->dev.of_node; 8363e086edfSolivier moysan struct resource *res; 8373e086edfSolivier moysan void __iomem *base; 8383e086edfSolivier moysan 8393e086edfSolivier moysan if (!np) 8403e086edfSolivier moysan return -ENODEV; 8413e086edfSolivier moysan 8423e086edfSolivier moysan res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 8433e086edfSolivier moysan base = devm_ioremap_resource(&pdev->dev, res); 8443e086edfSolivier moysan if (IS_ERR(base)) 8453e086edfSolivier moysan return PTR_ERR(base); 8463e086edfSolivier moysan 8473e086edfSolivier moysan sai->phys_addr = res->start; 84803e78a24Solivier moysan 84903e78a24Solivier moysan sai->regmap_config = &stm32_sai_sub_regmap_config_f4; 85003e78a24Solivier moysan /* Note: PDM registers not available for H7 sub-block B */ 85103e78a24Solivier moysan if (STM_SAI_IS_H7(sai->pdata) && STM_SAI_IS_SUB_A(sai)) 85203e78a24Solivier moysan sai->regmap_config = &stm32_sai_sub_regmap_config_h7; 85303e78a24Solivier moysan 85403e78a24Solivier moysan sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "sai_ck", 85503e78a24Solivier moysan base, sai->regmap_config); 85603e78a24Solivier moysan if (IS_ERR(sai->regmap)) { 85703e78a24Solivier moysan dev_err(&pdev->dev, "Failed to initialize MMIO\n"); 85803e78a24Solivier moysan return PTR_ERR(sai->regmap); 85903e78a24Solivier moysan } 8603e086edfSolivier moysan 8613e086edfSolivier moysan /* Get direction property */ 8623e086edfSolivier moysan if (of_property_match_string(np, "dma-names", "tx") >= 0) { 8633e086edfSolivier moysan sai->dir = SNDRV_PCM_STREAM_PLAYBACK; 8643e086edfSolivier moysan } else if (of_property_match_string(np, "dma-names", "rx") >= 0) { 8653e086edfSolivier moysan sai->dir = SNDRV_PCM_STREAM_CAPTURE; 8663e086edfSolivier moysan } else { 8673e086edfSolivier moysan dev_err(&pdev->dev, "Unsupported direction\n"); 8683e086edfSolivier moysan return -EINVAL; 8693e086edfSolivier moysan } 8703e086edfSolivier moysan 8713e086edfSolivier moysan sai->sai_ck = devm_clk_get(&pdev->dev, "sai_ck"); 8723e086edfSolivier moysan if (IS_ERR(sai->sai_ck)) { 873602fdadcSolivier moysan dev_err(&pdev->dev, "Missing kernel clock sai_ck\n"); 8743e086edfSolivier moysan return PTR_ERR(sai->sai_ck); 8753e086edfSolivier moysan } 8763e086edfSolivier moysan 8773e086edfSolivier moysan return 0; 8783e086edfSolivier moysan } 8793e086edfSolivier moysan 8803e086edfSolivier moysan static int stm32_sai_sub_dais_init(struct platform_device *pdev, 8813e086edfSolivier moysan struct stm32_sai_sub_data *sai) 8823e086edfSolivier moysan { 8833e086edfSolivier moysan sai->cpu_dai_drv = devm_kzalloc(&pdev->dev, 8843e086edfSolivier moysan sizeof(struct snd_soc_dai_driver), 8853e086edfSolivier moysan GFP_KERNEL); 8863e086edfSolivier moysan if (!sai->cpu_dai_drv) 8873e086edfSolivier moysan return -ENOMEM; 8883e086edfSolivier moysan 8893e086edfSolivier moysan sai->cpu_dai_drv->name = dev_name(&pdev->dev); 8903e086edfSolivier moysan if (STM_SAI_IS_PLAYBACK(sai)) { 8913e086edfSolivier moysan memcpy(sai->cpu_dai_drv, &stm32_sai_playback_dai, 8923e086edfSolivier moysan sizeof(stm32_sai_playback_dai)); 8933e086edfSolivier moysan sai->cpu_dai_drv->playback.stream_name = sai->cpu_dai_drv->name; 8943e086edfSolivier moysan } else { 8953e086edfSolivier moysan memcpy(sai->cpu_dai_drv, &stm32_sai_capture_dai, 8963e086edfSolivier moysan sizeof(stm32_sai_capture_dai)); 8973e086edfSolivier moysan sai->cpu_dai_drv->capture.stream_name = sai->cpu_dai_drv->name; 8983e086edfSolivier moysan } 8993e086edfSolivier moysan 9003e086edfSolivier moysan return 0; 9013e086edfSolivier moysan } 9023e086edfSolivier moysan 9033e086edfSolivier moysan static int stm32_sai_sub_probe(struct platform_device *pdev) 9043e086edfSolivier moysan { 9053e086edfSolivier moysan struct stm32_sai_sub_data *sai; 9063e086edfSolivier moysan const struct of_device_id *of_id; 9073e086edfSolivier moysan int ret; 9083e086edfSolivier moysan 9093e086edfSolivier moysan sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL); 9103e086edfSolivier moysan if (!sai) 9113e086edfSolivier moysan return -ENOMEM; 9123e086edfSolivier moysan 9133e086edfSolivier moysan of_id = of_match_device(stm32_sai_sub_ids, &pdev->dev); 9143e086edfSolivier moysan if (!of_id) 9153e086edfSolivier moysan return -EINVAL; 9163e086edfSolivier moysan sai->id = (uintptr_t)of_id->data; 9173e086edfSolivier moysan 9183e086edfSolivier moysan sai->pdev = pdev; 9193e086edfSolivier moysan platform_set_drvdata(pdev, sai); 9203e086edfSolivier moysan 9213e086edfSolivier moysan sai->pdata = dev_get_drvdata(pdev->dev.parent); 9223e086edfSolivier moysan if (!sai->pdata) { 9233e086edfSolivier moysan dev_err(&pdev->dev, "Parent device data not available\n"); 9243e086edfSolivier moysan return -EINVAL; 9253e086edfSolivier moysan } 9263e086edfSolivier moysan 9273e086edfSolivier moysan ret = stm32_sai_sub_parse_of(pdev, sai); 9283e086edfSolivier moysan if (ret) 9293e086edfSolivier moysan return ret; 9303e086edfSolivier moysan 9313e086edfSolivier moysan ret = stm32_sai_sub_dais_init(pdev, sai); 9323e086edfSolivier moysan if (ret) 9333e086edfSolivier moysan return ret; 9343e086edfSolivier moysan 9353e086edfSolivier moysan ret = devm_request_irq(&pdev->dev, sai->pdata->irq, stm32_sai_isr, 9363e086edfSolivier moysan IRQF_SHARED, dev_name(&pdev->dev), sai); 9373e086edfSolivier moysan if (ret) { 938602fdadcSolivier moysan dev_err(&pdev->dev, "IRQ request returned %d\n", ret); 9393e086edfSolivier moysan return ret; 9403e086edfSolivier moysan } 9413e086edfSolivier moysan 9423e086edfSolivier moysan ret = devm_snd_soc_register_component(&pdev->dev, &stm32_component, 9433e086edfSolivier moysan sai->cpu_dai_drv, 1); 9443e086edfSolivier moysan if (ret) 9453e086edfSolivier moysan return ret; 9463e086edfSolivier moysan 9473e086edfSolivier moysan ret = devm_snd_dmaengine_pcm_register(&pdev->dev, 9483e086edfSolivier moysan &stm32_sai_pcm_config, 0); 9493e086edfSolivier moysan if (ret) { 950602fdadcSolivier moysan dev_err(&pdev->dev, "Could not register pcm dma\n"); 9513e086edfSolivier moysan return ret; 9523e086edfSolivier moysan } 9533e086edfSolivier moysan 9543e086edfSolivier moysan return 0; 9553e086edfSolivier moysan } 9563e086edfSolivier moysan 9573e086edfSolivier moysan static struct platform_driver stm32_sai_sub_driver = { 9583e086edfSolivier moysan .driver = { 9593e086edfSolivier moysan .name = "st,stm32-sai-sub", 9603e086edfSolivier moysan .of_match_table = stm32_sai_sub_ids, 9613e086edfSolivier moysan }, 9623e086edfSolivier moysan .probe = stm32_sai_sub_probe, 9633e086edfSolivier moysan }; 9643e086edfSolivier moysan 9653e086edfSolivier moysan module_platform_driver(stm32_sai_sub_driver); 9663e086edfSolivier moysan 9673e086edfSolivier moysan MODULE_DESCRIPTION("STM32 Soc SAI sub-block Interface"); 968602fdadcSolivier moysan MODULE_AUTHOR("Olivier Moysan <olivier.moysan@st.com>"); 9693e086edfSolivier moysan MODULE_ALIAS("platform:st,stm32-sai-sub"); 9703e086edfSolivier moysan MODULE_LICENSE("GPL v2"); 971