13e086edfSolivier moysan /* 23e086edfSolivier moysan * STM32 ALSA SoC Digital Audio Interface (SAI) driver. 33e086edfSolivier moysan * 43e086edfSolivier moysan * Copyright (C) 2016, STMicroelectronics - All Rights Reserved 53e086edfSolivier moysan * Author(s): Olivier Moysan <olivier.moysan@st.com> for STMicroelectronics. 63e086edfSolivier moysan * 73e086edfSolivier moysan * License terms: GPL V2.0. 83e086edfSolivier moysan * 93e086edfSolivier moysan * This program is free software; you can redistribute it and/or modify it 103e086edfSolivier moysan * under the terms of the GNU General Public License version 2 as published by 113e086edfSolivier moysan * the Free Software Foundation. 123e086edfSolivier moysan * 133e086edfSolivier moysan * This program is distributed in the hope that it will be useful, but 143e086edfSolivier moysan * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 153e086edfSolivier moysan * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more 163e086edfSolivier moysan * details. 173e086edfSolivier moysan */ 183e086edfSolivier moysan 193e086edfSolivier moysan #include <linux/clk.h> 208307b2afSOlivier Moysan #include <linux/clk-provider.h> 213e086edfSolivier moysan #include <linux/kernel.h> 223e086edfSolivier moysan #include <linux/module.h> 233e086edfSolivier moysan #include <linux/of_irq.h> 243e086edfSolivier moysan #include <linux/of_platform.h> 253e086edfSolivier moysan #include <linux/regmap.h> 263e086edfSolivier moysan 276eb17d70SOlivier Moysan #include <sound/asoundef.h> 283e086edfSolivier moysan #include <sound/core.h> 293e086edfSolivier moysan #include <sound/dmaengine_pcm.h> 303e086edfSolivier moysan #include <sound/pcm_params.h> 313e086edfSolivier moysan 323e086edfSolivier moysan #include "stm32_sai.h" 333e086edfSolivier moysan 343e086edfSolivier moysan #define SAI_FREE_PROTOCOL 0x0 356eb17d70SOlivier Moysan #define SAI_SPDIF_PROTOCOL 0x1 363e086edfSolivier moysan 373e086edfSolivier moysan #define SAI_SLOT_SIZE_AUTO 0x0 383e086edfSolivier moysan #define SAI_SLOT_SIZE_16 0x1 393e086edfSolivier moysan #define SAI_SLOT_SIZE_32 0x2 403e086edfSolivier moysan 413e086edfSolivier moysan #define SAI_DATASIZE_8 0x2 423e086edfSolivier moysan #define SAI_DATASIZE_10 0x3 433e086edfSolivier moysan #define SAI_DATASIZE_16 0x4 443e086edfSolivier moysan #define SAI_DATASIZE_20 0x5 453e086edfSolivier moysan #define SAI_DATASIZE_24 0x6 463e086edfSolivier moysan #define SAI_DATASIZE_32 0x7 473e086edfSolivier moysan 483e086edfSolivier moysan #define STM_SAI_DAI_NAME_SIZE 15 493e086edfSolivier moysan 503e086edfSolivier moysan #define STM_SAI_IS_PLAYBACK(ip) ((ip)->dir == SNDRV_PCM_STREAM_PLAYBACK) 513e086edfSolivier moysan #define STM_SAI_IS_CAPTURE(ip) ((ip)->dir == SNDRV_PCM_STREAM_CAPTURE) 523e086edfSolivier moysan 533e086edfSolivier moysan #define STM_SAI_A_ID 0x0 543e086edfSolivier moysan #define STM_SAI_B_ID 0x1 553e086edfSolivier moysan 5603e78a24Solivier moysan #define STM_SAI_IS_SUB_A(x) ((x)->id == STM_SAI_A_ID) 5703e78a24Solivier moysan #define STM_SAI_IS_SUB_B(x) ((x)->id == STM_SAI_B_ID) 583e086edfSolivier moysan #define STM_SAI_BLOCK_NAME(x) (((x)->id == STM_SAI_A_ID) ? "A" : "B") 593e086edfSolivier moysan 605914d285SOlivier Moysan #define SAI_SYNC_NONE 0x0 615914d285SOlivier Moysan #define SAI_SYNC_INTERNAL 0x1 625914d285SOlivier Moysan #define SAI_SYNC_EXTERNAL 0x2 635914d285SOlivier Moysan 646eb17d70SOlivier Moysan #define STM_SAI_PROTOCOL_IS_SPDIF(ip) ((ip)->spdif) 651d9c95c1SOlivier Moysan #define STM_SAI_HAS_SPDIF(x) ((x)->pdata->conf.has_spdif_pdm) 661d9c95c1SOlivier Moysan #define STM_SAI_HAS_PDM(x) ((x)->pdata->conf.has_spdif_pdm) 675914d285SOlivier Moysan #define STM_SAI_HAS_EXT_SYNC(x) (!STM_SAI_IS_F4(sai->pdata)) 685914d285SOlivier Moysan 696eb17d70SOlivier Moysan #define SAI_IEC60958_BLOCK_FRAMES 192 706eb17d70SOlivier Moysan #define SAI_IEC60958_STATUS_BYTES 24 716eb17d70SOlivier Moysan 728307b2afSOlivier Moysan #define SAI_MCLK_NAME_LEN 32 73e37c2deaSOlivier Moysan #define SAI_RATE_11K 11025 748307b2afSOlivier Moysan 753e086edfSolivier moysan /** 763e086edfSolivier moysan * struct stm32_sai_sub_data - private data of SAI sub block (block A or B) 773e086edfSolivier moysan * @pdev: device data pointer 783e086edfSolivier moysan * @regmap: SAI register map pointer 7903e78a24Solivier moysan * @regmap_config: SAI sub block register map configuration pointer 803e086edfSolivier moysan * @dma_params: dma configuration data for rx or tx channel 813e086edfSolivier moysan * @cpu_dai_drv: DAI driver data pointer 823e086edfSolivier moysan * @cpu_dai: DAI runtime data pointer 833e086edfSolivier moysan * @substream: PCM substream data pointer 843e086edfSolivier moysan * @pdata: SAI block parent data pointer 855914d285SOlivier Moysan * @np_sync_provider: synchronization provider node 863e086edfSolivier moysan * @sai_ck: kernel clock feeding the SAI clock generator 878307b2afSOlivier Moysan * @sai_mclk: master clock from SAI mclk provider 883e086edfSolivier moysan * @phys_addr: SAI registers physical base address 893e086edfSolivier moysan * @mclk_rate: SAI block master clock frequency (Hz). set at init 903e086edfSolivier moysan * @id: SAI sub block id corresponding to sub-block A or B 913e086edfSolivier moysan * @dir: SAI block direction (playback or capture). set at init 923e086edfSolivier moysan * @master: SAI block mode flag. (true=master, false=slave) set at init 936eb17d70SOlivier Moysan * @spdif: SAI S/PDIF iec60958 mode flag. set at init 943e086edfSolivier moysan * @fmt: SAI block format. relevant only for custom protocols. set at init 953e086edfSolivier moysan * @sync: SAI block synchronization mode. (none, internal or external) 965914d285SOlivier Moysan * @synco: SAI block ext sync source (provider setting). (none, sub-block A/B) 975914d285SOlivier Moysan * @synci: SAI block ext sync source (client setting). (SAI sync provider index) 983e086edfSolivier moysan * @fs_length: frame synchronization length. depends on protocol settings 993e086edfSolivier moysan * @slots: rx or tx slot number 1003e086edfSolivier moysan * @slot_width: rx or tx slot width in bits 1013e086edfSolivier moysan * @slot_mask: rx or tx active slots mask. set at init or at runtime 1023e086edfSolivier moysan * @data_size: PCM data width. corresponds to PCM substream width. 1036eb17d70SOlivier Moysan * @spdif_frm_cnt: S/PDIF playback frame counter 1045f8a1000SOlivier Moysan * @iec958: iec958 data 105187e01d0Solivier moysan * @ctrl_lock: control lock 10626f98e82SOlivier Moysan * @irq_lock: prevent race condition with IRQ 1073e086edfSolivier moysan */ 1083e086edfSolivier moysan struct stm32_sai_sub_data { 1093e086edfSolivier moysan struct platform_device *pdev; 1103e086edfSolivier moysan struct regmap *regmap; 11103e78a24Solivier moysan const struct regmap_config *regmap_config; 1123e086edfSolivier moysan struct snd_dmaengine_dai_dma_data dma_params; 1138f8a5488SArnaud Pouliquen struct snd_soc_dai_driver cpu_dai_drv; 1143e086edfSolivier moysan struct snd_soc_dai *cpu_dai; 1153e086edfSolivier moysan struct snd_pcm_substream *substream; 1163e086edfSolivier moysan struct stm32_sai_data *pdata; 1175914d285SOlivier Moysan struct device_node *np_sync_provider; 1183e086edfSolivier moysan struct clk *sai_ck; 1198307b2afSOlivier Moysan struct clk *sai_mclk; 1203e086edfSolivier moysan dma_addr_t phys_addr; 1213e086edfSolivier moysan unsigned int mclk_rate; 1223e086edfSolivier moysan unsigned int id; 1233e086edfSolivier moysan int dir; 1243e086edfSolivier moysan bool master; 1256eb17d70SOlivier Moysan bool spdif; 1263e086edfSolivier moysan int fmt; 1273e086edfSolivier moysan int sync; 1285914d285SOlivier Moysan int synco; 1295914d285SOlivier Moysan int synci; 1303e086edfSolivier moysan int fs_length; 1313e086edfSolivier moysan int slots; 1323e086edfSolivier moysan int slot_width; 1333e086edfSolivier moysan int slot_mask; 1343e086edfSolivier moysan int data_size; 1356eb17d70SOlivier Moysan unsigned int spdif_frm_cnt; 136187e01d0Solivier moysan struct snd_aes_iec958 iec958; 137187e01d0Solivier moysan struct mutex ctrl_lock; /* protect resources accessed by controls */ 13826f98e82SOlivier Moysan spinlock_t irq_lock; /* used to prevent race condition with IRQ */ 1393e086edfSolivier moysan }; 1403e086edfSolivier moysan 1413e086edfSolivier moysan enum stm32_sai_fifo_th { 1423e086edfSolivier moysan STM_SAI_FIFO_TH_EMPTY, 1433e086edfSolivier moysan STM_SAI_FIFO_TH_QUARTER, 1443e086edfSolivier moysan STM_SAI_FIFO_TH_HALF, 1453e086edfSolivier moysan STM_SAI_FIFO_TH_3_QUARTER, 1463e086edfSolivier moysan STM_SAI_FIFO_TH_FULL, 1473e086edfSolivier moysan }; 1483e086edfSolivier moysan 1493e086edfSolivier moysan static bool stm32_sai_sub_readable_reg(struct device *dev, unsigned int reg) 1503e086edfSolivier moysan { 1513e086edfSolivier moysan switch (reg) { 1523e086edfSolivier moysan case STM_SAI_CR1_REGX: 1533e086edfSolivier moysan case STM_SAI_CR2_REGX: 1543e086edfSolivier moysan case STM_SAI_FRCR_REGX: 1553e086edfSolivier moysan case STM_SAI_SLOTR_REGX: 1563e086edfSolivier moysan case STM_SAI_IMR_REGX: 1573e086edfSolivier moysan case STM_SAI_SR_REGX: 1583e086edfSolivier moysan case STM_SAI_CLRFR_REGX: 1593e086edfSolivier moysan case STM_SAI_DR_REGX: 16003e78a24Solivier moysan case STM_SAI_PDMCR_REGX: 16103e78a24Solivier moysan case STM_SAI_PDMLY_REGX: 1623e086edfSolivier moysan return true; 1633e086edfSolivier moysan default: 1643e086edfSolivier moysan return false; 1653e086edfSolivier moysan } 1663e086edfSolivier moysan } 1673e086edfSolivier moysan 1683e086edfSolivier moysan static bool stm32_sai_sub_volatile_reg(struct device *dev, unsigned int reg) 1693e086edfSolivier moysan { 1703e086edfSolivier moysan switch (reg) { 1713e086edfSolivier moysan case STM_SAI_DR_REGX: 172cf881773SOlivier Moysan case STM_SAI_SR_REGX: 1733e086edfSolivier moysan return true; 1743e086edfSolivier moysan default: 1753e086edfSolivier moysan return false; 1763e086edfSolivier moysan } 1773e086edfSolivier moysan } 1783e086edfSolivier moysan 1793e086edfSolivier moysan static bool stm32_sai_sub_writeable_reg(struct device *dev, unsigned int reg) 1803e086edfSolivier moysan { 1813e086edfSolivier moysan switch (reg) { 1823e086edfSolivier moysan case STM_SAI_CR1_REGX: 1833e086edfSolivier moysan case STM_SAI_CR2_REGX: 1843e086edfSolivier moysan case STM_SAI_FRCR_REGX: 1853e086edfSolivier moysan case STM_SAI_SLOTR_REGX: 1863e086edfSolivier moysan case STM_SAI_IMR_REGX: 1873e086edfSolivier moysan case STM_SAI_CLRFR_REGX: 1883e086edfSolivier moysan case STM_SAI_DR_REGX: 18903e78a24Solivier moysan case STM_SAI_PDMCR_REGX: 19003e78a24Solivier moysan case STM_SAI_PDMLY_REGX: 1913e086edfSolivier moysan return true; 1923e086edfSolivier moysan default: 1933e086edfSolivier moysan return false; 1943e086edfSolivier moysan } 1953e086edfSolivier moysan } 1963e086edfSolivier moysan 19703e78a24Solivier moysan static const struct regmap_config stm32_sai_sub_regmap_config_f4 = { 1983e086edfSolivier moysan .reg_bits = 32, 1993e086edfSolivier moysan .reg_stride = 4, 2003e086edfSolivier moysan .val_bits = 32, 2013e086edfSolivier moysan .max_register = STM_SAI_DR_REGX, 2023e086edfSolivier moysan .readable_reg = stm32_sai_sub_readable_reg, 2033e086edfSolivier moysan .volatile_reg = stm32_sai_sub_volatile_reg, 2043e086edfSolivier moysan .writeable_reg = stm32_sai_sub_writeable_reg, 2053e086edfSolivier moysan .fast_io = true, 206cf881773SOlivier Moysan .cache_type = REGCACHE_FLAT, 2073e086edfSolivier moysan }; 2083e086edfSolivier moysan 20903e78a24Solivier moysan static const struct regmap_config stm32_sai_sub_regmap_config_h7 = { 21003e78a24Solivier moysan .reg_bits = 32, 21103e78a24Solivier moysan .reg_stride = 4, 21203e78a24Solivier moysan .val_bits = 32, 21303e78a24Solivier moysan .max_register = STM_SAI_PDMLY_REGX, 21403e78a24Solivier moysan .readable_reg = stm32_sai_sub_readable_reg, 21503e78a24Solivier moysan .volatile_reg = stm32_sai_sub_volatile_reg, 21603e78a24Solivier moysan .writeable_reg = stm32_sai_sub_writeable_reg, 21703e78a24Solivier moysan .fast_io = true, 218cf881773SOlivier Moysan .cache_type = REGCACHE_FLAT, 21903e78a24Solivier moysan }; 22003e78a24Solivier moysan 221187e01d0Solivier moysan static int snd_pcm_iec958_info(struct snd_kcontrol *kcontrol, 222187e01d0Solivier moysan struct snd_ctl_elem_info *uinfo) 223187e01d0Solivier moysan { 224187e01d0Solivier moysan uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 225187e01d0Solivier moysan uinfo->count = 1; 226187e01d0Solivier moysan 227187e01d0Solivier moysan return 0; 228187e01d0Solivier moysan } 229187e01d0Solivier moysan 230187e01d0Solivier moysan static int snd_pcm_iec958_get(struct snd_kcontrol *kcontrol, 231187e01d0Solivier moysan struct snd_ctl_elem_value *uctl) 232187e01d0Solivier moysan { 233187e01d0Solivier moysan struct stm32_sai_sub_data *sai = snd_kcontrol_chip(kcontrol); 234187e01d0Solivier moysan 235187e01d0Solivier moysan mutex_lock(&sai->ctrl_lock); 236187e01d0Solivier moysan memcpy(uctl->value.iec958.status, sai->iec958.status, 4); 237187e01d0Solivier moysan mutex_unlock(&sai->ctrl_lock); 238187e01d0Solivier moysan 239187e01d0Solivier moysan return 0; 240187e01d0Solivier moysan } 241187e01d0Solivier moysan 242187e01d0Solivier moysan static int snd_pcm_iec958_put(struct snd_kcontrol *kcontrol, 243187e01d0Solivier moysan struct snd_ctl_elem_value *uctl) 244187e01d0Solivier moysan { 245187e01d0Solivier moysan struct stm32_sai_sub_data *sai = snd_kcontrol_chip(kcontrol); 246187e01d0Solivier moysan 247187e01d0Solivier moysan mutex_lock(&sai->ctrl_lock); 248187e01d0Solivier moysan memcpy(sai->iec958.status, uctl->value.iec958.status, 4); 249187e01d0Solivier moysan mutex_unlock(&sai->ctrl_lock); 250187e01d0Solivier moysan 251187e01d0Solivier moysan return 0; 252187e01d0Solivier moysan } 253187e01d0Solivier moysan 254187e01d0Solivier moysan static const struct snd_kcontrol_new iec958_ctls = { 255187e01d0Solivier moysan .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE | 256187e01d0Solivier moysan SNDRV_CTL_ELEM_ACCESS_VOLATILE), 257187e01d0Solivier moysan .iface = SNDRV_CTL_ELEM_IFACE_PCM, 258187e01d0Solivier moysan .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT), 259187e01d0Solivier moysan .info = snd_pcm_iec958_info, 260187e01d0Solivier moysan .get = snd_pcm_iec958_get, 261187e01d0Solivier moysan .put = snd_pcm_iec958_put, 262187e01d0Solivier moysan }; 263187e01d0Solivier moysan 2648307b2afSOlivier Moysan struct stm32_sai_mclk_data { 2658307b2afSOlivier Moysan struct clk_hw hw; 2668307b2afSOlivier Moysan unsigned long freq; 2678307b2afSOlivier Moysan struct stm32_sai_sub_data *sai_data; 2688307b2afSOlivier Moysan }; 2698307b2afSOlivier Moysan 2708307b2afSOlivier Moysan #define to_mclk_data(_hw) container_of(_hw, struct stm32_sai_mclk_data, hw) 2718307b2afSOlivier Moysan #define STM32_SAI_MAX_CLKS 1 2728307b2afSOlivier Moysan 2738307b2afSOlivier Moysan static int stm32_sai_get_clk_div(struct stm32_sai_sub_data *sai, 2748307b2afSOlivier Moysan unsigned long input_rate, 2758307b2afSOlivier Moysan unsigned long output_rate) 2768307b2afSOlivier Moysan { 2771d9c95c1SOlivier Moysan int version = sai->pdata->conf.version; 2788307b2afSOlivier Moysan int div; 2798307b2afSOlivier Moysan 2808307b2afSOlivier Moysan div = DIV_ROUND_CLOSEST(input_rate, output_rate); 2818307b2afSOlivier Moysan if (div > SAI_XCR1_MCKDIV_MAX(version)) { 2828307b2afSOlivier Moysan dev_err(&sai->pdev->dev, "Divider %d out of range\n", div); 2838307b2afSOlivier Moysan return -EINVAL; 2848307b2afSOlivier Moysan } 2858307b2afSOlivier Moysan dev_dbg(&sai->pdev->dev, "SAI divider %d\n", div); 2868307b2afSOlivier Moysan 2878307b2afSOlivier Moysan if (input_rate % div) 2888307b2afSOlivier Moysan dev_dbg(&sai->pdev->dev, 2898307b2afSOlivier Moysan "Rate not accurate. requested (%ld), actual (%ld)\n", 2908307b2afSOlivier Moysan output_rate, input_rate / div); 2918307b2afSOlivier Moysan 2928307b2afSOlivier Moysan return div; 2938307b2afSOlivier Moysan } 2948307b2afSOlivier Moysan 2958307b2afSOlivier Moysan static int stm32_sai_set_clk_div(struct stm32_sai_sub_data *sai, 2968307b2afSOlivier Moysan unsigned int div) 2978307b2afSOlivier Moysan { 2981d9c95c1SOlivier Moysan int version = sai->pdata->conf.version; 2998307b2afSOlivier Moysan int ret, cr1, mask; 3008307b2afSOlivier Moysan 3018307b2afSOlivier Moysan if (div > SAI_XCR1_MCKDIV_MAX(version)) { 3028307b2afSOlivier Moysan dev_err(&sai->pdev->dev, "Divider %d out of range\n", div); 3038307b2afSOlivier Moysan return -EINVAL; 3048307b2afSOlivier Moysan } 3058307b2afSOlivier Moysan 3068307b2afSOlivier Moysan mask = SAI_XCR1_MCKDIV_MASK(SAI_XCR1_MCKDIV_WIDTH(version)); 3078307b2afSOlivier Moysan cr1 = SAI_XCR1_MCKDIV_SET(div); 3088307b2afSOlivier Moysan ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, mask, cr1); 3098307b2afSOlivier Moysan if (ret < 0) 3108307b2afSOlivier Moysan dev_err(&sai->pdev->dev, "Failed to update CR1 register\n"); 3118307b2afSOlivier Moysan 3128307b2afSOlivier Moysan return ret; 3138307b2afSOlivier Moysan } 3148307b2afSOlivier Moysan 315e37c2deaSOlivier Moysan static int stm32_sai_set_parent_clock(struct stm32_sai_sub_data *sai, 316e37c2deaSOlivier Moysan unsigned int rate) 317e37c2deaSOlivier Moysan { 318e37c2deaSOlivier Moysan struct platform_device *pdev = sai->pdev; 319e37c2deaSOlivier Moysan struct clk *parent_clk = sai->pdata->clk_x8k; 320e37c2deaSOlivier Moysan int ret; 321e37c2deaSOlivier Moysan 322e37c2deaSOlivier Moysan if (!(rate % SAI_RATE_11K)) 323e37c2deaSOlivier Moysan parent_clk = sai->pdata->clk_x11k; 324e37c2deaSOlivier Moysan 325e37c2deaSOlivier Moysan ret = clk_set_parent(sai->sai_ck, parent_clk); 326e37c2deaSOlivier Moysan if (ret) 327e37c2deaSOlivier Moysan dev_err(&pdev->dev, " Error %d setting sai_ck parent clock. %s", 328e37c2deaSOlivier Moysan ret, ret == -EBUSY ? 329e37c2deaSOlivier Moysan "Active stream rates conflict\n" : "\n"); 330e37c2deaSOlivier Moysan 331e37c2deaSOlivier Moysan return ret; 332e37c2deaSOlivier Moysan } 333e37c2deaSOlivier Moysan 3348307b2afSOlivier Moysan static long stm32_sai_mclk_round_rate(struct clk_hw *hw, unsigned long rate, 3358307b2afSOlivier Moysan unsigned long *prate) 3368307b2afSOlivier Moysan { 3378307b2afSOlivier Moysan struct stm32_sai_mclk_data *mclk = to_mclk_data(hw); 3388307b2afSOlivier Moysan struct stm32_sai_sub_data *sai = mclk->sai_data; 3398307b2afSOlivier Moysan int div; 3408307b2afSOlivier Moysan 3418307b2afSOlivier Moysan div = stm32_sai_get_clk_div(sai, *prate, rate); 3428307b2afSOlivier Moysan if (div < 0) 3438307b2afSOlivier Moysan return div; 3448307b2afSOlivier Moysan 3458307b2afSOlivier Moysan mclk->freq = *prate / div; 3468307b2afSOlivier Moysan 3478307b2afSOlivier Moysan return mclk->freq; 3488307b2afSOlivier Moysan } 3498307b2afSOlivier Moysan 3508307b2afSOlivier Moysan static unsigned long stm32_sai_mclk_recalc_rate(struct clk_hw *hw, 3518307b2afSOlivier Moysan unsigned long parent_rate) 3528307b2afSOlivier Moysan { 3538307b2afSOlivier Moysan struct stm32_sai_mclk_data *mclk = to_mclk_data(hw); 3548307b2afSOlivier Moysan 3558307b2afSOlivier Moysan return mclk->freq; 3568307b2afSOlivier Moysan } 3578307b2afSOlivier Moysan 3588307b2afSOlivier Moysan static int stm32_sai_mclk_set_rate(struct clk_hw *hw, unsigned long rate, 3598307b2afSOlivier Moysan unsigned long parent_rate) 3608307b2afSOlivier Moysan { 3618307b2afSOlivier Moysan struct stm32_sai_mclk_data *mclk = to_mclk_data(hw); 3628307b2afSOlivier Moysan struct stm32_sai_sub_data *sai = mclk->sai_data; 3636b27e277SColin Ian King int div, ret; 3648307b2afSOlivier Moysan 3658307b2afSOlivier Moysan div = stm32_sai_get_clk_div(sai, parent_rate, rate); 3668307b2afSOlivier Moysan if (div < 0) 3678307b2afSOlivier Moysan return div; 3688307b2afSOlivier Moysan 3698307b2afSOlivier Moysan ret = stm32_sai_set_clk_div(sai, div); 3708307b2afSOlivier Moysan if (ret) 3718307b2afSOlivier Moysan return ret; 3728307b2afSOlivier Moysan 3738307b2afSOlivier Moysan mclk->freq = rate; 3748307b2afSOlivier Moysan 3758307b2afSOlivier Moysan return 0; 3768307b2afSOlivier Moysan } 3778307b2afSOlivier Moysan 3788307b2afSOlivier Moysan static int stm32_sai_mclk_enable(struct clk_hw *hw) 3798307b2afSOlivier Moysan { 3808307b2afSOlivier Moysan struct stm32_sai_mclk_data *mclk = to_mclk_data(hw); 3818307b2afSOlivier Moysan struct stm32_sai_sub_data *sai = mclk->sai_data; 3828307b2afSOlivier Moysan 3838307b2afSOlivier Moysan dev_dbg(&sai->pdev->dev, "Enable master clock\n"); 3848307b2afSOlivier Moysan 3858307b2afSOlivier Moysan return regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, 3868307b2afSOlivier Moysan SAI_XCR1_MCKEN, SAI_XCR1_MCKEN); 3878307b2afSOlivier Moysan } 3888307b2afSOlivier Moysan 3898307b2afSOlivier Moysan static void stm32_sai_mclk_disable(struct clk_hw *hw) 3908307b2afSOlivier Moysan { 3918307b2afSOlivier Moysan struct stm32_sai_mclk_data *mclk = to_mclk_data(hw); 3928307b2afSOlivier Moysan struct stm32_sai_sub_data *sai = mclk->sai_data; 3938307b2afSOlivier Moysan 3948307b2afSOlivier Moysan dev_dbg(&sai->pdev->dev, "Disable master clock\n"); 3958307b2afSOlivier Moysan 3968307b2afSOlivier Moysan regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, SAI_XCR1_MCKEN, 0); 3978307b2afSOlivier Moysan } 3988307b2afSOlivier Moysan 3998307b2afSOlivier Moysan static const struct clk_ops mclk_ops = { 4008307b2afSOlivier Moysan .enable = stm32_sai_mclk_enable, 4018307b2afSOlivier Moysan .disable = stm32_sai_mclk_disable, 4028307b2afSOlivier Moysan .recalc_rate = stm32_sai_mclk_recalc_rate, 4038307b2afSOlivier Moysan .round_rate = stm32_sai_mclk_round_rate, 4048307b2afSOlivier Moysan .set_rate = stm32_sai_mclk_set_rate, 4058307b2afSOlivier Moysan }; 4068307b2afSOlivier Moysan 4078307b2afSOlivier Moysan static int stm32_sai_add_mclk_provider(struct stm32_sai_sub_data *sai) 4088307b2afSOlivier Moysan { 4098307b2afSOlivier Moysan struct clk_hw *hw; 4108307b2afSOlivier Moysan struct stm32_sai_mclk_data *mclk; 4118307b2afSOlivier Moysan struct device *dev = &sai->pdev->dev; 4128307b2afSOlivier Moysan const char *pname = __clk_get_name(sai->sai_ck); 4138307b2afSOlivier Moysan char *mclk_name, *p, *s = (char *)pname; 4148307b2afSOlivier Moysan int ret, i = 0; 4158307b2afSOlivier Moysan 416496fa3baSWei Yongjun mclk = devm_kzalloc(dev, sizeof(*mclk), GFP_KERNEL); 4178307b2afSOlivier Moysan if (!mclk) 4188307b2afSOlivier Moysan return -ENOMEM; 4198307b2afSOlivier Moysan 4208307b2afSOlivier Moysan mclk_name = devm_kcalloc(dev, sizeof(char), 4218307b2afSOlivier Moysan SAI_MCLK_NAME_LEN, GFP_KERNEL); 4228307b2afSOlivier Moysan if (!mclk_name) 4238307b2afSOlivier Moysan return -ENOMEM; 4248307b2afSOlivier Moysan 4258307b2afSOlivier Moysan /* 4268307b2afSOlivier Moysan * Forge mclk clock name from parent clock name and suffix. 4278307b2afSOlivier Moysan * String after "_" char is stripped in parent name. 4288307b2afSOlivier Moysan */ 4298307b2afSOlivier Moysan p = mclk_name; 4306be0f96dSOlivier Moysan while (*s && *s != '_' && (i < (SAI_MCLK_NAME_LEN - 7))) { 4318307b2afSOlivier Moysan *p++ = *s++; 4328307b2afSOlivier Moysan i++; 4338307b2afSOlivier Moysan } 4346be0f96dSOlivier Moysan STM_SAI_IS_SUB_A(sai) ? strcat(p, "a_mclk") : strcat(p, "b_mclk"); 4358307b2afSOlivier Moysan 4368307b2afSOlivier Moysan mclk->hw.init = CLK_HW_INIT(mclk_name, pname, &mclk_ops, 0); 4378307b2afSOlivier Moysan mclk->sai_data = sai; 4388307b2afSOlivier Moysan hw = &mclk->hw; 4398307b2afSOlivier Moysan 4408307b2afSOlivier Moysan dev_dbg(dev, "Register master clock %s\n", mclk_name); 4418307b2afSOlivier Moysan ret = devm_clk_hw_register(&sai->pdev->dev, hw); 4428307b2afSOlivier Moysan if (ret) { 4438307b2afSOlivier Moysan dev_err(dev, "mclk register returned %d\n", ret); 4448307b2afSOlivier Moysan return ret; 4458307b2afSOlivier Moysan } 4468307b2afSOlivier Moysan sai->sai_mclk = hw->clk; 4478307b2afSOlivier Moysan 4488307b2afSOlivier Moysan /* register mclk provider */ 4498307b2afSOlivier Moysan return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw); 4508307b2afSOlivier Moysan } 4518307b2afSOlivier Moysan 4523e086edfSolivier moysan static irqreturn_t stm32_sai_isr(int irq, void *devid) 4533e086edfSolivier moysan { 4543e086edfSolivier moysan struct stm32_sai_sub_data *sai = (struct stm32_sai_sub_data *)devid; 4553e086edfSolivier moysan struct platform_device *pdev = sai->pdev; 4563e086edfSolivier moysan unsigned int sr, imr, flags; 4573e086edfSolivier moysan snd_pcm_state_t status = SNDRV_PCM_STATE_RUNNING; 4583e086edfSolivier moysan 4593e086edfSolivier moysan regmap_read(sai->regmap, STM_SAI_IMR_REGX, &imr); 4603e086edfSolivier moysan regmap_read(sai->regmap, STM_SAI_SR_REGX, &sr); 4613e086edfSolivier moysan 4623e086edfSolivier moysan flags = sr & imr; 4633e086edfSolivier moysan if (!flags) 4643e086edfSolivier moysan return IRQ_NONE; 4653e086edfSolivier moysan 466cf881773SOlivier Moysan regmap_write_bits(sai->regmap, STM_SAI_CLRFR_REGX, SAI_XCLRFR_MASK, 4673e086edfSolivier moysan SAI_XCLRFR_MASK); 4683e086edfSolivier moysan 469d807cdfbSOlivier Moysan if (!sai->substream) { 470d807cdfbSOlivier Moysan dev_err(&pdev->dev, "Device stopped. Spurious IRQ 0x%x\n", sr); 471d807cdfbSOlivier Moysan return IRQ_NONE; 472d807cdfbSOlivier Moysan } 473d807cdfbSOlivier Moysan 4743e086edfSolivier moysan if (flags & SAI_XIMR_OVRUDRIE) { 475602fdadcSolivier moysan dev_err(&pdev->dev, "IRQ %s\n", 4763e086edfSolivier moysan STM_SAI_IS_PLAYBACK(sai) ? "underrun" : "overrun"); 4773e086edfSolivier moysan status = SNDRV_PCM_STATE_XRUN; 4783e086edfSolivier moysan } 4793e086edfSolivier moysan 4803e086edfSolivier moysan if (flags & SAI_XIMR_MUTEDETIE) 481602fdadcSolivier moysan dev_dbg(&pdev->dev, "IRQ mute detected\n"); 4823e086edfSolivier moysan 4833e086edfSolivier moysan if (flags & SAI_XIMR_WCKCFGIE) { 484602fdadcSolivier moysan dev_err(&pdev->dev, "IRQ wrong clock configuration\n"); 4853e086edfSolivier moysan status = SNDRV_PCM_STATE_DISCONNECTED; 4863e086edfSolivier moysan } 4873e086edfSolivier moysan 4883e086edfSolivier moysan if (flags & SAI_XIMR_CNRDYIE) 489602fdadcSolivier moysan dev_err(&pdev->dev, "IRQ Codec not ready\n"); 4903e086edfSolivier moysan 4913e086edfSolivier moysan if (flags & SAI_XIMR_AFSDETIE) { 492602fdadcSolivier moysan dev_err(&pdev->dev, "IRQ Anticipated frame synchro\n"); 4933e086edfSolivier moysan status = SNDRV_PCM_STATE_XRUN; 4943e086edfSolivier moysan } 4953e086edfSolivier moysan 4963e086edfSolivier moysan if (flags & SAI_XIMR_LFSDETIE) { 497602fdadcSolivier moysan dev_err(&pdev->dev, "IRQ Late frame synchro\n"); 4983e086edfSolivier moysan status = SNDRV_PCM_STATE_XRUN; 4993e086edfSolivier moysan } 5003e086edfSolivier moysan 50126f98e82SOlivier Moysan spin_lock(&sai->irq_lock); 50226f98e82SOlivier Moysan if (status != SNDRV_PCM_STATE_RUNNING && sai->substream) 503b1625fbbSTakashi Iwai snd_pcm_stop_xrun(sai->substream); 50426f98e82SOlivier Moysan spin_unlock(&sai->irq_lock); 5053e086edfSolivier moysan 5063e086edfSolivier moysan return IRQ_HANDLED; 5073e086edfSolivier moysan } 5083e086edfSolivier moysan 5093e086edfSolivier moysan static int stm32_sai_set_sysclk(struct snd_soc_dai *cpu_dai, 5103e086edfSolivier moysan int clk_id, unsigned int freq, int dir) 5113e086edfSolivier moysan { 5123e086edfSolivier moysan struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 513701a6ec3Solivier moysan int ret; 5143e086edfSolivier moysan 515e37c2deaSOlivier Moysan if (dir == SND_SOC_CLOCK_OUT && sai->sai_mclk) { 516701a6ec3Solivier moysan ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, 517701a6ec3Solivier moysan SAI_XCR1_NODIV, 518701a6ec3Solivier moysan (unsigned int)~SAI_XCR1_NODIV); 519701a6ec3Solivier moysan if (ret < 0) 520701a6ec3Solivier moysan return ret; 521701a6ec3Solivier moysan 522e37c2deaSOlivier Moysan /* If master clock is used, set parent clock now */ 523e37c2deaSOlivier Moysan ret = stm32_sai_set_parent_clock(sai, freq); 524e37c2deaSOlivier Moysan if (ret) 525e37c2deaSOlivier Moysan return ret; 5268307b2afSOlivier Moysan 527e37c2deaSOlivier Moysan ret = clk_set_rate_exclusive(sai->sai_mclk, freq); 5288307b2afSOlivier Moysan if (ret) { 5298307b2afSOlivier Moysan dev_err(cpu_dai->dev, 530e37c2deaSOlivier Moysan ret == -EBUSY ? 531e37c2deaSOlivier Moysan "Active streams have incompatible rates" : 5328307b2afSOlivier Moysan "Could not set mclk rate\n"); 5338307b2afSOlivier Moysan return ret; 5348307b2afSOlivier Moysan } 535e37c2deaSOlivier Moysan 536e37c2deaSOlivier Moysan dev_dbg(cpu_dai->dev, "SAI MCLK frequency is %uHz\n", freq); 537e37c2deaSOlivier Moysan sai->mclk_rate = freq; 5383e086edfSolivier moysan } 5393e086edfSolivier moysan 5403e086edfSolivier moysan return 0; 5413e086edfSolivier moysan } 5423e086edfSolivier moysan 5433e086edfSolivier moysan static int stm32_sai_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask, 5443e086edfSolivier moysan u32 rx_mask, int slots, int slot_width) 5453e086edfSolivier moysan { 5463e086edfSolivier moysan struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 5473e086edfSolivier moysan int slotr, slotr_mask, slot_size; 5483e086edfSolivier moysan 5496eb17d70SOlivier Moysan if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { 5506eb17d70SOlivier Moysan dev_warn(cpu_dai->dev, "Slot setting relevant only for TDM\n"); 5516eb17d70SOlivier Moysan return 0; 5526eb17d70SOlivier Moysan } 5536eb17d70SOlivier Moysan 554602fdadcSolivier moysan dev_dbg(cpu_dai->dev, "Masks tx/rx:%#x/%#x, slots:%d, width:%d\n", 5553e086edfSolivier moysan tx_mask, rx_mask, slots, slot_width); 5563e086edfSolivier moysan 5573e086edfSolivier moysan switch (slot_width) { 5583e086edfSolivier moysan case 16: 5593e086edfSolivier moysan slot_size = SAI_SLOT_SIZE_16; 5603e086edfSolivier moysan break; 5613e086edfSolivier moysan case 32: 5623e086edfSolivier moysan slot_size = SAI_SLOT_SIZE_32; 5633e086edfSolivier moysan break; 5643e086edfSolivier moysan default: 5653e086edfSolivier moysan slot_size = SAI_SLOT_SIZE_AUTO; 5663e086edfSolivier moysan break; 5673e086edfSolivier moysan } 5683e086edfSolivier moysan 5693e086edfSolivier moysan slotr = SAI_XSLOTR_SLOTSZ_SET(slot_size) | 5703e086edfSolivier moysan SAI_XSLOTR_NBSLOT_SET(slots - 1); 5713e086edfSolivier moysan slotr_mask = SAI_XSLOTR_SLOTSZ_MASK | SAI_XSLOTR_NBSLOT_MASK; 5723e086edfSolivier moysan 5733e086edfSolivier moysan /* tx/rx mask set in machine init, if slot number defined in DT */ 5743e086edfSolivier moysan if (STM_SAI_IS_PLAYBACK(sai)) { 5753e086edfSolivier moysan sai->slot_mask = tx_mask; 5763e086edfSolivier moysan slotr |= SAI_XSLOTR_SLOTEN_SET(tx_mask); 5773e086edfSolivier moysan } 5783e086edfSolivier moysan 5793e086edfSolivier moysan if (STM_SAI_IS_CAPTURE(sai)) { 5803e086edfSolivier moysan sai->slot_mask = rx_mask; 5813e086edfSolivier moysan slotr |= SAI_XSLOTR_SLOTEN_SET(rx_mask); 5823e086edfSolivier moysan } 5833e086edfSolivier moysan 5843e086edfSolivier moysan slotr_mask |= SAI_XSLOTR_SLOTEN_MASK; 5853e086edfSolivier moysan 5863e086edfSolivier moysan regmap_update_bits(sai->regmap, STM_SAI_SLOTR_REGX, slotr_mask, slotr); 5873e086edfSolivier moysan 5883e086edfSolivier moysan sai->slot_width = slot_width; 5893e086edfSolivier moysan sai->slots = slots; 5903e086edfSolivier moysan 5913e086edfSolivier moysan return 0; 5923e086edfSolivier moysan } 5933e086edfSolivier moysan 5943e086edfSolivier moysan static int stm32_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) 5953e086edfSolivier moysan { 5963e086edfSolivier moysan struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 59761fb4ff7SOlivier Moysan int cr1, frcr = 0; 59861fb4ff7SOlivier Moysan int cr1_mask, frcr_mask = 0; 5993e086edfSolivier moysan int ret; 6003e086edfSolivier moysan 6013e086edfSolivier moysan dev_dbg(cpu_dai->dev, "fmt %x\n", fmt); 6023e086edfSolivier moysan 6036eb17d70SOlivier Moysan /* Do not generate master by default */ 6046eb17d70SOlivier Moysan cr1 = SAI_XCR1_NODIV; 6056eb17d70SOlivier Moysan cr1_mask = SAI_XCR1_NODIV; 6066eb17d70SOlivier Moysan 6076eb17d70SOlivier Moysan cr1_mask |= SAI_XCR1_PRTCFG_MASK; 6086eb17d70SOlivier Moysan if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { 6096eb17d70SOlivier Moysan cr1 |= SAI_XCR1_PRTCFG_SET(SAI_SPDIF_PROTOCOL); 6106eb17d70SOlivier Moysan goto conf_update; 6116eb17d70SOlivier Moysan } 6126eb17d70SOlivier Moysan 6136eb17d70SOlivier Moysan cr1 |= SAI_XCR1_PRTCFG_SET(SAI_FREE_PROTOCOL); 61461fb4ff7SOlivier Moysan 6153e086edfSolivier moysan switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 6163e086edfSolivier moysan /* SCK active high for all protocols */ 6173e086edfSolivier moysan case SND_SOC_DAIFMT_I2S: 6183e086edfSolivier moysan cr1 |= SAI_XCR1_CKSTR; 6193e086edfSolivier moysan frcr |= SAI_XFRCR_FSOFF | SAI_XFRCR_FSDEF; 6203e086edfSolivier moysan break; 6213e086edfSolivier moysan /* Left justified */ 6223e086edfSolivier moysan case SND_SOC_DAIFMT_MSB: 6233e086edfSolivier moysan frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSDEF; 6243e086edfSolivier moysan break; 6253e086edfSolivier moysan /* Right justified */ 6263e086edfSolivier moysan case SND_SOC_DAIFMT_LSB: 6273e086edfSolivier moysan frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSDEF; 6283e086edfSolivier moysan break; 6293e086edfSolivier moysan case SND_SOC_DAIFMT_DSP_A: 6303e086edfSolivier moysan frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSOFF; 6313e086edfSolivier moysan break; 6323e086edfSolivier moysan case SND_SOC_DAIFMT_DSP_B: 6333e086edfSolivier moysan frcr |= SAI_XFRCR_FSPOL; 6343e086edfSolivier moysan break; 6353e086edfSolivier moysan default: 6363e086edfSolivier moysan dev_err(cpu_dai->dev, "Unsupported protocol %#x\n", 6373e086edfSolivier moysan fmt & SND_SOC_DAIFMT_FORMAT_MASK); 6383e086edfSolivier moysan return -EINVAL; 6393e086edfSolivier moysan } 6403e086edfSolivier moysan 64161fb4ff7SOlivier Moysan cr1_mask |= SAI_XCR1_CKSTR; 6423e086edfSolivier moysan frcr_mask |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSOFF | 6433e086edfSolivier moysan SAI_XFRCR_FSDEF; 6443e086edfSolivier moysan 6453e086edfSolivier moysan /* DAI clock strobing. Invert setting previously set */ 6463e086edfSolivier moysan switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 6473e086edfSolivier moysan case SND_SOC_DAIFMT_NB_NF: 6483e086edfSolivier moysan break; 6493e086edfSolivier moysan case SND_SOC_DAIFMT_IB_NF: 6503e086edfSolivier moysan cr1 ^= SAI_XCR1_CKSTR; 6513e086edfSolivier moysan break; 6523e086edfSolivier moysan case SND_SOC_DAIFMT_NB_IF: 6533e086edfSolivier moysan frcr ^= SAI_XFRCR_FSPOL; 6543e086edfSolivier moysan break; 6553e086edfSolivier moysan case SND_SOC_DAIFMT_IB_IF: 6563e086edfSolivier moysan /* Invert fs & sck */ 6573e086edfSolivier moysan cr1 ^= SAI_XCR1_CKSTR; 6583e086edfSolivier moysan frcr ^= SAI_XFRCR_FSPOL; 6593e086edfSolivier moysan break; 6603e086edfSolivier moysan default: 6613e086edfSolivier moysan dev_err(cpu_dai->dev, "Unsupported strobing %#x\n", 6623e086edfSolivier moysan fmt & SND_SOC_DAIFMT_INV_MASK); 6633e086edfSolivier moysan return -EINVAL; 6643e086edfSolivier moysan } 6653e086edfSolivier moysan cr1_mask |= SAI_XCR1_CKSTR; 6663e086edfSolivier moysan frcr_mask |= SAI_XFRCR_FSPOL; 6673e086edfSolivier moysan 6683e086edfSolivier moysan regmap_update_bits(sai->regmap, STM_SAI_FRCR_REGX, frcr_mask, frcr); 6693e086edfSolivier moysan 6703e086edfSolivier moysan /* DAI clock master masks */ 6713e086edfSolivier moysan switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 6723e086edfSolivier moysan case SND_SOC_DAIFMT_CBM_CFM: 6733e086edfSolivier moysan /* codec is master */ 6743e086edfSolivier moysan cr1 |= SAI_XCR1_SLAVE; 6753e086edfSolivier moysan sai->master = false; 6763e086edfSolivier moysan break; 6773e086edfSolivier moysan case SND_SOC_DAIFMT_CBS_CFS: 6783e086edfSolivier moysan sai->master = true; 6793e086edfSolivier moysan break; 6803e086edfSolivier moysan default: 6813e086edfSolivier moysan dev_err(cpu_dai->dev, "Unsupported mode %#x\n", 6823e086edfSolivier moysan fmt & SND_SOC_DAIFMT_MASTER_MASK); 6833e086edfSolivier moysan return -EINVAL; 6843e086edfSolivier moysan } 6855914d285SOlivier Moysan 6865914d285SOlivier Moysan /* Set slave mode if sub-block is synchronized with another SAI */ 6875914d285SOlivier Moysan if (sai->sync) { 6885914d285SOlivier Moysan dev_dbg(cpu_dai->dev, "Synchronized SAI configured as slave\n"); 6895914d285SOlivier Moysan cr1 |= SAI_XCR1_SLAVE; 6905914d285SOlivier Moysan sai->master = false; 6915914d285SOlivier Moysan } 6925914d285SOlivier Moysan 6933e086edfSolivier moysan cr1_mask |= SAI_XCR1_SLAVE; 6943e086edfSolivier moysan 6956eb17d70SOlivier Moysan conf_update: 6963e086edfSolivier moysan ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, cr1_mask, cr1); 6973e086edfSolivier moysan if (ret < 0) { 6983e086edfSolivier moysan dev_err(cpu_dai->dev, "Failed to update CR1 register\n"); 6993e086edfSolivier moysan return ret; 7003e086edfSolivier moysan } 7013e086edfSolivier moysan 7023e086edfSolivier moysan sai->fmt = fmt; 7033e086edfSolivier moysan 7043e086edfSolivier moysan return 0; 7053e086edfSolivier moysan } 7063e086edfSolivier moysan 7073e086edfSolivier moysan static int stm32_sai_startup(struct snd_pcm_substream *substream, 7083e086edfSolivier moysan struct snd_soc_dai *cpu_dai) 7093e086edfSolivier moysan { 7103e086edfSolivier moysan struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 7113e086edfSolivier moysan int imr, cr2, ret; 71226f98e82SOlivier Moysan unsigned long flags; 7133e086edfSolivier moysan 71426f98e82SOlivier Moysan spin_lock_irqsave(&sai->irq_lock, flags); 7153e086edfSolivier moysan sai->substream = substream; 71626f98e82SOlivier Moysan spin_unlock_irqrestore(&sai->irq_lock, flags); 7173e086edfSolivier moysan 718b8468192SOlivier Moysan if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { 719b8468192SOlivier Moysan snd_pcm_hw_constraint_mask64(substream->runtime, 720b8468192SOlivier Moysan SNDRV_PCM_HW_PARAM_FORMAT, 721b8468192SOlivier Moysan SNDRV_PCM_FMTBIT_S32_LE); 722b8468192SOlivier Moysan snd_pcm_hw_constraint_single(substream->runtime, 723b8468192SOlivier Moysan SNDRV_PCM_HW_PARAM_CHANNELS, 2); 724b8468192SOlivier Moysan } 725b8468192SOlivier Moysan 7263e086edfSolivier moysan ret = clk_prepare_enable(sai->sai_ck); 7273e086edfSolivier moysan if (ret < 0) { 728602fdadcSolivier moysan dev_err(cpu_dai->dev, "Failed to enable clock: %d\n", ret); 7293e086edfSolivier moysan return ret; 7303e086edfSolivier moysan } 7313e086edfSolivier moysan 7323e086edfSolivier moysan /* Enable ITs */ 733cf881773SOlivier Moysan regmap_write_bits(sai->regmap, STM_SAI_CLRFR_REGX, 7343e086edfSolivier moysan SAI_XCLRFR_MASK, SAI_XCLRFR_MASK); 7353e086edfSolivier moysan 7363e086edfSolivier moysan imr = SAI_XIMR_OVRUDRIE; 7373e086edfSolivier moysan if (STM_SAI_IS_CAPTURE(sai)) { 7383e086edfSolivier moysan regmap_read(sai->regmap, STM_SAI_CR2_REGX, &cr2); 7393e086edfSolivier moysan if (cr2 & SAI_XCR2_MUTECNT_MASK) 7403e086edfSolivier moysan imr |= SAI_XIMR_MUTEDETIE; 7413e086edfSolivier moysan } 7423e086edfSolivier moysan 7433e086edfSolivier moysan if (sai->master) 7443e086edfSolivier moysan imr |= SAI_XIMR_WCKCFGIE; 7453e086edfSolivier moysan else 7463e086edfSolivier moysan imr |= SAI_XIMR_AFSDETIE | SAI_XIMR_LFSDETIE; 7473e086edfSolivier moysan 7483e086edfSolivier moysan regmap_update_bits(sai->regmap, STM_SAI_IMR_REGX, 7493e086edfSolivier moysan SAI_XIMR_MASK, imr); 7503e086edfSolivier moysan 7513e086edfSolivier moysan return 0; 7523e086edfSolivier moysan } 7533e086edfSolivier moysan 7543e086edfSolivier moysan static int stm32_sai_set_config(struct snd_soc_dai *cpu_dai, 7553e086edfSolivier moysan struct snd_pcm_substream *substream, 7563e086edfSolivier moysan struct snd_pcm_hw_params *params) 7573e086edfSolivier moysan { 7583e086edfSolivier moysan struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 7593e086edfSolivier moysan int cr1, cr1_mask, ret; 7603e086edfSolivier moysan 761a4529d2bSOlivier Moysan /* 762a4529d2bSOlivier Moysan * DMA bursts increment is set to 4 words. 763a4529d2bSOlivier Moysan * SAI fifo threshold is set to half fifo, to keep enough space 764a4529d2bSOlivier Moysan * for DMA incoming bursts. 765a4529d2bSOlivier Moysan */ 766cf881773SOlivier Moysan regmap_write_bits(sai->regmap, STM_SAI_CR2_REGX, 7673e086edfSolivier moysan SAI_XCR2_FFLUSH | SAI_XCR2_FTH_MASK, 768a4529d2bSOlivier Moysan SAI_XCR2_FFLUSH | 769a4529d2bSOlivier Moysan SAI_XCR2_FTH_SET(STM_SAI_FIFO_TH_HALF)); 7703e086edfSolivier moysan 7716eb17d70SOlivier Moysan /* DS bits in CR1 not set for SPDIF (size forced to 24 bits).*/ 7726eb17d70SOlivier Moysan if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { 7736eb17d70SOlivier Moysan sai->spdif_frm_cnt = 0; 7746eb17d70SOlivier Moysan return 0; 7756eb17d70SOlivier Moysan } 7766eb17d70SOlivier Moysan 7773e086edfSolivier moysan /* Mode, data format and channel config */ 77861fb4ff7SOlivier Moysan cr1_mask = SAI_XCR1_DS_MASK; 7793e086edfSolivier moysan switch (params_format(params)) { 7803e086edfSolivier moysan case SNDRV_PCM_FORMAT_S8: 7817e751e37Solivier moysan cr1 = SAI_XCR1_DS_SET(SAI_DATASIZE_8); 7823e086edfSolivier moysan break; 7833e086edfSolivier moysan case SNDRV_PCM_FORMAT_S16_LE: 7847e751e37Solivier moysan cr1 = SAI_XCR1_DS_SET(SAI_DATASIZE_16); 7853e086edfSolivier moysan break; 7863e086edfSolivier moysan case SNDRV_PCM_FORMAT_S32_LE: 7877e751e37Solivier moysan cr1 = SAI_XCR1_DS_SET(SAI_DATASIZE_32); 7883e086edfSolivier moysan break; 7893e086edfSolivier moysan default: 7903e086edfSolivier moysan dev_err(cpu_dai->dev, "Data format not supported"); 7913e086edfSolivier moysan return -EINVAL; 7923e086edfSolivier moysan } 7933e086edfSolivier moysan 7943e086edfSolivier moysan cr1_mask |= SAI_XCR1_MONO; 7953e086edfSolivier moysan if ((sai->slots == 2) && (params_channels(params) == 1)) 7963e086edfSolivier moysan cr1 |= SAI_XCR1_MONO; 7973e086edfSolivier moysan 7983e086edfSolivier moysan ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, cr1_mask, cr1); 7993e086edfSolivier moysan if (ret < 0) { 8003e086edfSolivier moysan dev_err(cpu_dai->dev, "Failed to update CR1 register\n"); 8013e086edfSolivier moysan return ret; 8023e086edfSolivier moysan } 8033e086edfSolivier moysan 8043e086edfSolivier moysan return 0; 8053e086edfSolivier moysan } 8063e086edfSolivier moysan 8073e086edfSolivier moysan static int stm32_sai_set_slots(struct snd_soc_dai *cpu_dai) 8083e086edfSolivier moysan { 8093e086edfSolivier moysan struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 8103e086edfSolivier moysan int slotr, slot_sz; 8113e086edfSolivier moysan 8123e086edfSolivier moysan regmap_read(sai->regmap, STM_SAI_SLOTR_REGX, &slotr); 8133e086edfSolivier moysan 8143e086edfSolivier moysan /* 8153e086edfSolivier moysan * If SLOTSZ is set to auto in SLOTR, align slot width on data size 8163e086edfSolivier moysan * By default slot width = data size, if not forced from DT 8173e086edfSolivier moysan */ 8183e086edfSolivier moysan slot_sz = slotr & SAI_XSLOTR_SLOTSZ_MASK; 8193e086edfSolivier moysan if (slot_sz == SAI_XSLOTR_SLOTSZ_SET(SAI_SLOT_SIZE_AUTO)) 8203e086edfSolivier moysan sai->slot_width = sai->data_size; 8213e086edfSolivier moysan 8223e086edfSolivier moysan if (sai->slot_width < sai->data_size) { 8233e086edfSolivier moysan dev_err(cpu_dai->dev, 8243e086edfSolivier moysan "Data size %d larger than slot width\n", 8253e086edfSolivier moysan sai->data_size); 8263e086edfSolivier moysan return -EINVAL; 8273e086edfSolivier moysan } 8283e086edfSolivier moysan 8293e086edfSolivier moysan /* Slot number is set to 2, if not specified in DT */ 8303e086edfSolivier moysan if (!sai->slots) 8313e086edfSolivier moysan sai->slots = 2; 8323e086edfSolivier moysan 8333e086edfSolivier moysan /* The number of slots in the audio frame is equal to NBSLOT[3:0] + 1*/ 8343e086edfSolivier moysan regmap_update_bits(sai->regmap, STM_SAI_SLOTR_REGX, 8353e086edfSolivier moysan SAI_XSLOTR_NBSLOT_MASK, 8363e086edfSolivier moysan SAI_XSLOTR_NBSLOT_SET((sai->slots - 1))); 8373e086edfSolivier moysan 8383e086edfSolivier moysan /* Set default slots mask if not already set from DT */ 8393e086edfSolivier moysan if (!(slotr & SAI_XSLOTR_SLOTEN_MASK)) { 8403e086edfSolivier moysan sai->slot_mask = (1 << sai->slots) - 1; 8413e086edfSolivier moysan regmap_update_bits(sai->regmap, 8423e086edfSolivier moysan STM_SAI_SLOTR_REGX, SAI_XSLOTR_SLOTEN_MASK, 8433e086edfSolivier moysan SAI_XSLOTR_SLOTEN_SET(sai->slot_mask)); 8443e086edfSolivier moysan } 8453e086edfSolivier moysan 846602fdadcSolivier moysan dev_dbg(cpu_dai->dev, "Slots %d, slot width %d\n", 8473e086edfSolivier moysan sai->slots, sai->slot_width); 8483e086edfSolivier moysan 8493e086edfSolivier moysan return 0; 8503e086edfSolivier moysan } 8513e086edfSolivier moysan 8523e086edfSolivier moysan static void stm32_sai_set_frame(struct snd_soc_dai *cpu_dai) 8533e086edfSolivier moysan { 8543e086edfSolivier moysan struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 8553e086edfSolivier moysan int fs_active, offset, format; 8563e086edfSolivier moysan int frcr, frcr_mask; 8573e086edfSolivier moysan 8583e086edfSolivier moysan format = sai->fmt & SND_SOC_DAIFMT_FORMAT_MASK; 8593e086edfSolivier moysan sai->fs_length = sai->slot_width * sai->slots; 8603e086edfSolivier moysan 8613e086edfSolivier moysan fs_active = sai->fs_length / 2; 8623e086edfSolivier moysan if ((format == SND_SOC_DAIFMT_DSP_A) || 8633e086edfSolivier moysan (format == SND_SOC_DAIFMT_DSP_B)) 8643e086edfSolivier moysan fs_active = 1; 8653e086edfSolivier moysan 8663e086edfSolivier moysan frcr = SAI_XFRCR_FRL_SET((sai->fs_length - 1)); 8673e086edfSolivier moysan frcr |= SAI_XFRCR_FSALL_SET((fs_active - 1)); 8683e086edfSolivier moysan frcr_mask = SAI_XFRCR_FRL_MASK | SAI_XFRCR_FSALL_MASK; 8693e086edfSolivier moysan 870602fdadcSolivier moysan dev_dbg(cpu_dai->dev, "Frame length %d, frame active %d\n", 8713e086edfSolivier moysan sai->fs_length, fs_active); 8723e086edfSolivier moysan 8733e086edfSolivier moysan regmap_update_bits(sai->regmap, STM_SAI_FRCR_REGX, frcr_mask, frcr); 8743e086edfSolivier moysan 8753e086edfSolivier moysan if ((sai->fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_LSB) { 8763e086edfSolivier moysan offset = sai->slot_width - sai->data_size; 8773e086edfSolivier moysan 8783e086edfSolivier moysan regmap_update_bits(sai->regmap, STM_SAI_SLOTR_REGX, 8793e086edfSolivier moysan SAI_XSLOTR_FBOFF_MASK, 8803e086edfSolivier moysan SAI_XSLOTR_FBOFF_SET(offset)); 8813e086edfSolivier moysan } 8823e086edfSolivier moysan } 8833e086edfSolivier moysan 884187e01d0Solivier moysan static void stm32_sai_init_iec958_status(struct stm32_sai_sub_data *sai) 885187e01d0Solivier moysan { 886187e01d0Solivier moysan unsigned char *cs = sai->iec958.status; 887187e01d0Solivier moysan 888187e01d0Solivier moysan cs[0] = IEC958_AES0_CON_NOT_COPYRIGHT | IEC958_AES0_CON_EMPHASIS_NONE; 889187e01d0Solivier moysan cs[1] = IEC958_AES1_CON_GENERAL; 890187e01d0Solivier moysan cs[2] = IEC958_AES2_CON_SOURCE_UNSPEC | IEC958_AES2_CON_CHANNEL_UNSPEC; 891187e01d0Solivier moysan cs[3] = IEC958_AES3_CON_CLOCK_1000PPM | IEC958_AES3_CON_FS_NOTID; 892187e01d0Solivier moysan } 893187e01d0Solivier moysan 894187e01d0Solivier moysan static void stm32_sai_set_iec958_status(struct stm32_sai_sub_data *sai, 895187e01d0Solivier moysan struct snd_pcm_runtime *runtime) 896187e01d0Solivier moysan { 897187e01d0Solivier moysan if (!runtime) 898187e01d0Solivier moysan return; 899187e01d0Solivier moysan 900187e01d0Solivier moysan /* Force the sample rate according to runtime rate */ 901187e01d0Solivier moysan mutex_lock(&sai->ctrl_lock); 902187e01d0Solivier moysan switch (runtime->rate) { 903187e01d0Solivier moysan case 22050: 904187e01d0Solivier moysan sai->iec958.status[3] = IEC958_AES3_CON_FS_22050; 905187e01d0Solivier moysan break; 906187e01d0Solivier moysan case 44100: 907187e01d0Solivier moysan sai->iec958.status[3] = IEC958_AES3_CON_FS_44100; 908187e01d0Solivier moysan break; 909187e01d0Solivier moysan case 88200: 910187e01d0Solivier moysan sai->iec958.status[3] = IEC958_AES3_CON_FS_88200; 911187e01d0Solivier moysan break; 912187e01d0Solivier moysan case 176400: 913187e01d0Solivier moysan sai->iec958.status[3] = IEC958_AES3_CON_FS_176400; 914187e01d0Solivier moysan break; 915187e01d0Solivier moysan case 24000: 916187e01d0Solivier moysan sai->iec958.status[3] = IEC958_AES3_CON_FS_24000; 917187e01d0Solivier moysan break; 918187e01d0Solivier moysan case 48000: 919187e01d0Solivier moysan sai->iec958.status[3] = IEC958_AES3_CON_FS_48000; 920187e01d0Solivier moysan break; 921187e01d0Solivier moysan case 96000: 922187e01d0Solivier moysan sai->iec958.status[3] = IEC958_AES3_CON_FS_96000; 923187e01d0Solivier moysan break; 924187e01d0Solivier moysan case 192000: 925187e01d0Solivier moysan sai->iec958.status[3] = IEC958_AES3_CON_FS_192000; 926187e01d0Solivier moysan break; 927187e01d0Solivier moysan case 32000: 928187e01d0Solivier moysan sai->iec958.status[3] = IEC958_AES3_CON_FS_32000; 929187e01d0Solivier moysan break; 930187e01d0Solivier moysan default: 931187e01d0Solivier moysan sai->iec958.status[3] = IEC958_AES3_CON_FS_NOTID; 932187e01d0Solivier moysan break; 933187e01d0Solivier moysan } 934187e01d0Solivier moysan mutex_unlock(&sai->ctrl_lock); 935187e01d0Solivier moysan } 936187e01d0Solivier moysan 9373e086edfSolivier moysan static int stm32_sai_configure_clock(struct snd_soc_dai *cpu_dai, 9383e086edfSolivier moysan struct snd_pcm_hw_params *params) 9393e086edfSolivier moysan { 9403e086edfSolivier moysan struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 94171d9537fSOlivier Moysan int div = 0, cr1 = 0; 9428307b2afSOlivier Moysan int sai_clk_rate, mclk_ratio, den; 9436eb17d70SOlivier Moysan unsigned int rate = params_rate(params); 944e37c2deaSOlivier Moysan int ret; 9453e086edfSolivier moysan 946e37c2deaSOlivier Moysan if (!sai->sai_mclk) { 947e37c2deaSOlivier Moysan ret = stm32_sai_set_parent_clock(sai, rate); 948e37c2deaSOlivier Moysan if (ret) 949e37c2deaSOlivier Moysan return ret; 950e37c2deaSOlivier Moysan } 9513e086edfSolivier moysan sai_clk_rate = clk_get_rate(sai->sai_ck); 9523e086edfSolivier moysan 95303e78a24Solivier moysan if (STM_SAI_IS_F4(sai->pdata)) { 9548307b2afSOlivier Moysan /* mclk on (NODIV=0) 9553e086edfSolivier moysan * mclk_rate = 256 * fs 9563e086edfSolivier moysan * MCKDIV = 0 if sai_ck < 3/2 * mclk_rate 9573e086edfSolivier moysan * MCKDIV = sai_ck / (2 * mclk_rate) otherwise 9588307b2afSOlivier Moysan * mclk off (NODIV=1) 9598307b2afSOlivier Moysan * MCKDIV ignored. sck = sai_ck 9603e086edfSolivier moysan */ 9618307b2afSOlivier Moysan if (!sai->mclk_rate) 9628307b2afSOlivier Moysan return 0; 9638307b2afSOlivier Moysan 9648307b2afSOlivier Moysan if (2 * sai_clk_rate >= 3 * sai->mclk_rate) { 9658307b2afSOlivier Moysan div = stm32_sai_get_clk_div(sai, sai_clk_rate, 96603e78a24Solivier moysan 2 * sai->mclk_rate); 9678307b2afSOlivier Moysan if (div < 0) 9688307b2afSOlivier Moysan return div; 9698307b2afSOlivier Moysan } 97003e78a24Solivier moysan } else { 97103e78a24Solivier moysan /* 97203e78a24Solivier moysan * TDM mode : 97303e78a24Solivier moysan * mclk on 97403e78a24Solivier moysan * MCKDIV = sai_ck / (ws x 256) (NOMCK=0. OSR=0) 97503e78a24Solivier moysan * MCKDIV = sai_ck / (ws x 512) (NOMCK=0. OSR=1) 97603e78a24Solivier moysan * mclk off 97703e78a24Solivier moysan * MCKDIV = sai_ck / (frl x ws) (NOMCK=1) 97803e78a24Solivier moysan * Note: NOMCK/NODIV correspond to same bit. 97903e78a24Solivier moysan */ 9806eb17d70SOlivier Moysan if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { 9818307b2afSOlivier Moysan div = stm32_sai_get_clk_div(sai, sai_clk_rate, 9828307b2afSOlivier Moysan rate * 128); 9838307b2afSOlivier Moysan if (div < 0) 9848307b2afSOlivier Moysan return div; 9856eb17d70SOlivier Moysan } else { 98603e78a24Solivier moysan if (sai->mclk_rate) { 9876eb17d70SOlivier Moysan mclk_ratio = sai->mclk_rate / rate; 98871d9537fSOlivier Moysan if (mclk_ratio == 512) { 98971d9537fSOlivier Moysan cr1 = SAI_XCR1_OSR; 99071d9537fSOlivier Moysan } else if (mclk_ratio != 256) { 99103e78a24Solivier moysan dev_err(cpu_dai->dev, 99203e78a24Solivier moysan "Wrong mclk ratio %d\n", 99303e78a24Solivier moysan mclk_ratio); 99403e78a24Solivier moysan return -EINVAL; 99503e78a24Solivier moysan } 99671d9537fSOlivier Moysan 99771d9537fSOlivier Moysan regmap_update_bits(sai->regmap, 99871d9537fSOlivier Moysan STM_SAI_CR1_REGX, 99971d9537fSOlivier Moysan SAI_XCR1_OSR, cr1); 100071d9537fSOlivier Moysan 10018307b2afSOlivier Moysan div = stm32_sai_get_clk_div(sai, sai_clk_rate, 10026eb17d70SOlivier Moysan sai->mclk_rate); 10038307b2afSOlivier Moysan if (div < 0) 10048307b2afSOlivier Moysan return div; 100503e78a24Solivier moysan } else { 10066eb17d70SOlivier Moysan /* mclk-fs not set, master clock not active */ 100703e78a24Solivier moysan den = sai->fs_length * params_rate(params); 10088307b2afSOlivier Moysan div = stm32_sai_get_clk_div(sai, sai_clk_rate, 10098307b2afSOlivier Moysan den); 10108307b2afSOlivier Moysan if (div < 0) 10118307b2afSOlivier Moysan return div; 101203e78a24Solivier moysan } 101303e78a24Solivier moysan } 10146eb17d70SOlivier Moysan } 10153e086edfSolivier moysan 10168307b2afSOlivier Moysan return stm32_sai_set_clk_div(sai, div); 10173e086edfSolivier moysan } 10183e086edfSolivier moysan 10193e086edfSolivier moysan static int stm32_sai_hw_params(struct snd_pcm_substream *substream, 10203e086edfSolivier moysan struct snd_pcm_hw_params *params, 10213e086edfSolivier moysan struct snd_soc_dai *cpu_dai) 10223e086edfSolivier moysan { 10233e086edfSolivier moysan struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 10243e086edfSolivier moysan int ret; 10253e086edfSolivier moysan 10263e086edfSolivier moysan sai->data_size = params_width(params); 10273e086edfSolivier moysan 1028187e01d0Solivier moysan if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { 1029187e01d0Solivier moysan /* Rate not already set in runtime structure */ 1030187e01d0Solivier moysan substream->runtime->rate = params_rate(params); 1031187e01d0Solivier moysan stm32_sai_set_iec958_status(sai, substream->runtime); 1032187e01d0Solivier moysan } else { 10333e086edfSolivier moysan ret = stm32_sai_set_slots(cpu_dai); 10343e086edfSolivier moysan if (ret < 0) 10353e086edfSolivier moysan return ret; 10363e086edfSolivier moysan stm32_sai_set_frame(cpu_dai); 10376eb17d70SOlivier Moysan } 10383e086edfSolivier moysan 10393e086edfSolivier moysan ret = stm32_sai_set_config(cpu_dai, substream, params); 10403e086edfSolivier moysan if (ret) 10413e086edfSolivier moysan return ret; 10423e086edfSolivier moysan 10433e086edfSolivier moysan if (sai->master) 10443e086edfSolivier moysan ret = stm32_sai_configure_clock(cpu_dai, params); 10453e086edfSolivier moysan 10463e086edfSolivier moysan return ret; 10473e086edfSolivier moysan } 10483e086edfSolivier moysan 10493e086edfSolivier moysan static int stm32_sai_trigger(struct snd_pcm_substream *substream, int cmd, 10503e086edfSolivier moysan struct snd_soc_dai *cpu_dai) 10513e086edfSolivier moysan { 10523e086edfSolivier moysan struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 10533e086edfSolivier moysan int ret; 10543e086edfSolivier moysan 10553e086edfSolivier moysan switch (cmd) { 10563e086edfSolivier moysan case SNDRV_PCM_TRIGGER_START: 10573e086edfSolivier moysan case SNDRV_PCM_TRIGGER_RESUME: 10583e086edfSolivier moysan case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 10593e086edfSolivier moysan dev_dbg(cpu_dai->dev, "Enable DMA and SAI\n"); 10603e086edfSolivier moysan 10613e086edfSolivier moysan regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, 10623e086edfSolivier moysan SAI_XCR1_DMAEN, SAI_XCR1_DMAEN); 10633e086edfSolivier moysan 10643e086edfSolivier moysan /* Enable SAI */ 10653e086edfSolivier moysan ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, 10663e086edfSolivier moysan SAI_XCR1_SAIEN, SAI_XCR1_SAIEN); 10673e086edfSolivier moysan if (ret < 0) 10683e086edfSolivier moysan dev_err(cpu_dai->dev, "Failed to update CR1 register\n"); 10693e086edfSolivier moysan break; 10703e086edfSolivier moysan case SNDRV_PCM_TRIGGER_SUSPEND: 10713e086edfSolivier moysan case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 10723e086edfSolivier moysan case SNDRV_PCM_TRIGGER_STOP: 10733e086edfSolivier moysan dev_dbg(cpu_dai->dev, "Disable DMA and SAI\n"); 10743e086edfSolivier moysan 107547a8907dSOlivier Moysan regmap_update_bits(sai->regmap, STM_SAI_IMR_REGX, 107647a8907dSOlivier Moysan SAI_XIMR_MASK, 0); 107747a8907dSOlivier Moysan 10783e086edfSolivier moysan regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, 10793e086edfSolivier moysan SAI_XCR1_SAIEN, 10803e086edfSolivier moysan (unsigned int)~SAI_XCR1_SAIEN); 10814fa17938Solivier moysan 10824fa17938Solivier moysan ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, 10834fa17938Solivier moysan SAI_XCR1_DMAEN, 10844fa17938Solivier moysan (unsigned int)~SAI_XCR1_DMAEN); 10853e086edfSolivier moysan if (ret < 0) 10863e086edfSolivier moysan dev_err(cpu_dai->dev, "Failed to update CR1 register\n"); 10876eb17d70SOlivier Moysan 10886eb17d70SOlivier Moysan if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) 10896eb17d70SOlivier Moysan sai->spdif_frm_cnt = 0; 10903e086edfSolivier moysan break; 10913e086edfSolivier moysan default: 10923e086edfSolivier moysan return -EINVAL; 10933e086edfSolivier moysan } 10943e086edfSolivier moysan 10953e086edfSolivier moysan return ret; 10963e086edfSolivier moysan } 10973e086edfSolivier moysan 10983e086edfSolivier moysan static void stm32_sai_shutdown(struct snd_pcm_substream *substream, 10993e086edfSolivier moysan struct snd_soc_dai *cpu_dai) 11003e086edfSolivier moysan { 11013e086edfSolivier moysan struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 110226f98e82SOlivier Moysan unsigned long flags; 11033e086edfSolivier moysan 11043e086edfSolivier moysan regmap_update_bits(sai->regmap, STM_SAI_IMR_REGX, SAI_XIMR_MASK, 0); 11053e086edfSolivier moysan 1106701a6ec3Solivier moysan regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, SAI_XCR1_NODIV, 1107701a6ec3Solivier moysan SAI_XCR1_NODIV); 1108701a6ec3Solivier moysan 1109e37c2deaSOlivier Moysan /* Release mclk rate only if rate was actually set */ 1110e37c2deaSOlivier Moysan if (sai->mclk_rate) { 11118307b2afSOlivier Moysan clk_rate_exclusive_put(sai->sai_mclk); 1112e37c2deaSOlivier Moysan sai->mclk_rate = 0; 1113e37c2deaSOlivier Moysan } 1114e37c2deaSOlivier Moysan 1115e37c2deaSOlivier Moysan clk_disable_unprepare(sai->sai_ck); 11168307b2afSOlivier Moysan 111726f98e82SOlivier Moysan spin_lock_irqsave(&sai->irq_lock, flags); 11183e086edfSolivier moysan sai->substream = NULL; 111926f98e82SOlivier Moysan spin_unlock_irqrestore(&sai->irq_lock, flags); 11203e086edfSolivier moysan } 11213e086edfSolivier moysan 1122187e01d0Solivier moysan static int stm32_sai_pcm_new(struct snd_soc_pcm_runtime *rtd, 1123187e01d0Solivier moysan struct snd_soc_dai *cpu_dai) 1124187e01d0Solivier moysan { 1125187e01d0Solivier moysan struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev); 11265f8a1000SOlivier Moysan struct snd_kcontrol_new knew = iec958_ctls; 1127187e01d0Solivier moysan 1128187e01d0Solivier moysan if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { 1129187e01d0Solivier moysan dev_dbg(&sai->pdev->dev, "%s: register iec controls", __func__); 11305f8a1000SOlivier Moysan knew.device = rtd->pcm->device; 11315f8a1000SOlivier Moysan return snd_ctl_add(rtd->pcm->card, snd_ctl_new1(&knew, sai)); 1132187e01d0Solivier moysan } 1133187e01d0Solivier moysan 1134187e01d0Solivier moysan return 0; 1135187e01d0Solivier moysan } 1136187e01d0Solivier moysan 11373e086edfSolivier moysan static int stm32_sai_dai_probe(struct snd_soc_dai *cpu_dai) 11383e086edfSolivier moysan { 11393e086edfSolivier moysan struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev); 1140d4180b4cSOlivier Moysan int cr1 = 0, cr1_mask, ret; 11413e086edfSolivier moysan 11428307b2afSOlivier Moysan sai->cpu_dai = cpu_dai; 11438307b2afSOlivier Moysan 11443e086edfSolivier moysan sai->dma_params.addr = (dma_addr_t)(sai->phys_addr + STM_SAI_DR_REGX); 1145a4529d2bSOlivier Moysan /* 1146a4529d2bSOlivier Moysan * DMA supports 4, 8 or 16 burst sizes. Burst size 4 is the best choice, 1147a4529d2bSOlivier Moysan * as it allows bytes, half-word and words transfers. (See DMA fifos 1148a4529d2bSOlivier Moysan * constraints). 1149a4529d2bSOlivier Moysan */ 1150a4529d2bSOlivier Moysan sai->dma_params.maxburst = 4; 11511d9c95c1SOlivier Moysan if (sai->pdata->conf.fifo_size < 8) 11521d9c95c1SOlivier Moysan sai->dma_params.maxburst = 1; 11533e086edfSolivier moysan /* Buswidth will be set by framework at runtime */ 11543e086edfSolivier moysan sai->dma_params.addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED; 11553e086edfSolivier moysan 11563e086edfSolivier moysan if (STM_SAI_IS_PLAYBACK(sai)) 11573e086edfSolivier moysan snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params, NULL); 11583e086edfSolivier moysan else 11593e086edfSolivier moysan snd_soc_dai_init_dma_data(cpu_dai, NULL, &sai->dma_params); 11603e086edfSolivier moysan 1161187e01d0Solivier moysan /* Next settings are not relevant for spdif mode */ 1162187e01d0Solivier moysan if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) 1163187e01d0Solivier moysan return 0; 1164187e01d0Solivier moysan 116561fb4ff7SOlivier Moysan cr1_mask = SAI_XCR1_RX_TX; 116661fb4ff7SOlivier Moysan if (STM_SAI_IS_CAPTURE(sai)) 116761fb4ff7SOlivier Moysan cr1 |= SAI_XCR1_RX_TX; 116861fb4ff7SOlivier Moysan 11695914d285SOlivier Moysan /* Configure synchronization */ 11705914d285SOlivier Moysan if (sai->sync == SAI_SYNC_EXTERNAL) { 11715914d285SOlivier Moysan /* Configure synchro client and provider */ 1172d4180b4cSOlivier Moysan ret = sai->pdata->set_sync(sai->pdata, sai->np_sync_provider, 11735914d285SOlivier Moysan sai->synco, sai->synci); 1174d4180b4cSOlivier Moysan if (ret) 1175d4180b4cSOlivier Moysan return ret; 11765914d285SOlivier Moysan } 11775914d285SOlivier Moysan 11785914d285SOlivier Moysan cr1_mask |= SAI_XCR1_SYNCEN_MASK; 11795914d285SOlivier Moysan cr1 |= SAI_XCR1_SYNCEN_SET(sai->sync); 11805914d285SOlivier Moysan 118161fb4ff7SOlivier Moysan return regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, cr1_mask, cr1); 11823e086edfSolivier moysan } 11833e086edfSolivier moysan 11843e086edfSolivier moysan static const struct snd_soc_dai_ops stm32_sai_pcm_dai_ops = { 11853e086edfSolivier moysan .set_sysclk = stm32_sai_set_sysclk, 11863e086edfSolivier moysan .set_fmt = stm32_sai_set_dai_fmt, 11873e086edfSolivier moysan .set_tdm_slot = stm32_sai_set_dai_tdm_slot, 11883e086edfSolivier moysan .startup = stm32_sai_startup, 11893e086edfSolivier moysan .hw_params = stm32_sai_hw_params, 11903e086edfSolivier moysan .trigger = stm32_sai_trigger, 11913e086edfSolivier moysan .shutdown = stm32_sai_shutdown, 11923e086edfSolivier moysan }; 11933e086edfSolivier moysan 11946eb17d70SOlivier Moysan static int stm32_sai_pcm_process_spdif(struct snd_pcm_substream *substream, 11956eb17d70SOlivier Moysan int channel, unsigned long hwoff, 11966eb17d70SOlivier Moysan void *buf, unsigned long bytes) 11976eb17d70SOlivier Moysan { 11986eb17d70SOlivier Moysan struct snd_pcm_runtime *runtime = substream->runtime; 11996eb17d70SOlivier Moysan struct snd_soc_pcm_runtime *rtd = substream->private_data; 12006eb17d70SOlivier Moysan struct snd_soc_dai *cpu_dai = rtd->cpu_dai; 12016eb17d70SOlivier Moysan struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev); 12026eb17d70SOlivier Moysan int *ptr = (int *)(runtime->dma_area + hwoff + 12036eb17d70SOlivier Moysan channel * (runtime->dma_bytes / runtime->channels)); 12046eb17d70SOlivier Moysan ssize_t cnt = bytes_to_samples(runtime, bytes); 12056eb17d70SOlivier Moysan unsigned int frm_cnt = sai->spdif_frm_cnt; 12066eb17d70SOlivier Moysan unsigned int byte; 12076eb17d70SOlivier Moysan unsigned int mask; 12086eb17d70SOlivier Moysan 12096eb17d70SOlivier Moysan do { 12106eb17d70SOlivier Moysan *ptr = ((*ptr >> 8) & 0x00ffffff); 12116eb17d70SOlivier Moysan 12126eb17d70SOlivier Moysan /* Set channel status bit */ 12136eb17d70SOlivier Moysan byte = frm_cnt >> 3; 12146eb17d70SOlivier Moysan mask = 1 << (frm_cnt - (byte << 3)); 1215187e01d0Solivier moysan if (sai->iec958.status[byte] & mask) 12166eb17d70SOlivier Moysan *ptr |= 0x04000000; 12176eb17d70SOlivier Moysan ptr++; 12186eb17d70SOlivier Moysan 12196eb17d70SOlivier Moysan if (!(cnt % 2)) 12206eb17d70SOlivier Moysan frm_cnt++; 12216eb17d70SOlivier Moysan 12226eb17d70SOlivier Moysan if (frm_cnt == SAI_IEC60958_BLOCK_FRAMES) 12236eb17d70SOlivier Moysan frm_cnt = 0; 12246eb17d70SOlivier Moysan } while (--cnt); 12256eb17d70SOlivier Moysan sai->spdif_frm_cnt = frm_cnt; 12266eb17d70SOlivier Moysan 12276eb17d70SOlivier Moysan return 0; 12286eb17d70SOlivier Moysan } 12296eb17d70SOlivier Moysan 12303e086edfSolivier moysan static const struct snd_pcm_hardware stm32_sai_pcm_hw = { 12313e086edfSolivier moysan .info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP, 12323e086edfSolivier moysan .buffer_bytes_max = 8 * PAGE_SIZE, 12333e086edfSolivier moysan .period_bytes_min = 1024, /* 5ms at 48kHz */ 12343e086edfSolivier moysan .period_bytes_max = PAGE_SIZE, 12353e086edfSolivier moysan .periods_min = 2, 12363e086edfSolivier moysan .periods_max = 8, 12373e086edfSolivier moysan }; 12383e086edfSolivier moysan 12398f8a5488SArnaud Pouliquen static struct snd_soc_dai_driver stm32_sai_playback_dai = { 12403e086edfSolivier moysan .probe = stm32_sai_dai_probe, 1241187e01d0Solivier moysan .pcm_new = stm32_sai_pcm_new, 12423e086edfSolivier moysan .id = 1, /* avoid call to fmt_single_name() */ 12433e086edfSolivier moysan .playback = { 12443e086edfSolivier moysan .channels_min = 1, 12453e086edfSolivier moysan .channels_max = 2, 12463e086edfSolivier moysan .rate_min = 8000, 12473e086edfSolivier moysan .rate_max = 192000, 12483e086edfSolivier moysan .rates = SNDRV_PCM_RATE_CONTINUOUS, 12493e086edfSolivier moysan /* DMA does not support 24 bits transfers */ 12503e086edfSolivier moysan .formats = 12513e086edfSolivier moysan SNDRV_PCM_FMTBIT_S8 | 12523e086edfSolivier moysan SNDRV_PCM_FMTBIT_S16_LE | 12533e086edfSolivier moysan SNDRV_PCM_FMTBIT_S32_LE, 12543e086edfSolivier moysan }, 12553e086edfSolivier moysan .ops = &stm32_sai_pcm_dai_ops, 12563e086edfSolivier moysan }; 12573e086edfSolivier moysan 12588f8a5488SArnaud Pouliquen static struct snd_soc_dai_driver stm32_sai_capture_dai = { 12593e086edfSolivier moysan .probe = stm32_sai_dai_probe, 12603e086edfSolivier moysan .id = 1, /* avoid call to fmt_single_name() */ 12613e086edfSolivier moysan .capture = { 12623e086edfSolivier moysan .channels_min = 1, 12633e086edfSolivier moysan .channels_max = 2, 12643e086edfSolivier moysan .rate_min = 8000, 12653e086edfSolivier moysan .rate_max = 192000, 12663e086edfSolivier moysan .rates = SNDRV_PCM_RATE_CONTINUOUS, 12673e086edfSolivier moysan /* DMA does not support 24 bits transfers */ 12683e086edfSolivier moysan .formats = 12693e086edfSolivier moysan SNDRV_PCM_FMTBIT_S8 | 12703e086edfSolivier moysan SNDRV_PCM_FMTBIT_S16_LE | 12713e086edfSolivier moysan SNDRV_PCM_FMTBIT_S32_LE, 12723e086edfSolivier moysan }, 12733e086edfSolivier moysan .ops = &stm32_sai_pcm_dai_ops, 12743e086edfSolivier moysan }; 12753e086edfSolivier moysan 12763e086edfSolivier moysan static const struct snd_dmaengine_pcm_config stm32_sai_pcm_config = { 12773e086edfSolivier moysan .pcm_hardware = &stm32_sai_pcm_hw, 12783e086edfSolivier moysan .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, 12793e086edfSolivier moysan }; 12803e086edfSolivier moysan 12816eb17d70SOlivier Moysan static const struct snd_dmaengine_pcm_config stm32_sai_pcm_config_spdif = { 12826eb17d70SOlivier Moysan .pcm_hardware = &stm32_sai_pcm_hw, 12836eb17d70SOlivier Moysan .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, 12846eb17d70SOlivier Moysan .process = stm32_sai_pcm_process_spdif, 12856eb17d70SOlivier Moysan }; 12866eb17d70SOlivier Moysan 12873e086edfSolivier moysan static const struct snd_soc_component_driver stm32_component = { 12883e086edfSolivier moysan .name = "stm32-sai", 12893e086edfSolivier moysan }; 12903e086edfSolivier moysan 12913e086edfSolivier moysan static const struct of_device_id stm32_sai_sub_ids[] = { 12923e086edfSolivier moysan { .compatible = "st,stm32-sai-sub-a", 12933e086edfSolivier moysan .data = (void *)STM_SAI_A_ID}, 12943e086edfSolivier moysan { .compatible = "st,stm32-sai-sub-b", 12953e086edfSolivier moysan .data = (void *)STM_SAI_B_ID}, 12963e086edfSolivier moysan {} 12973e086edfSolivier moysan }; 12983e086edfSolivier moysan MODULE_DEVICE_TABLE(of, stm32_sai_sub_ids); 12993e086edfSolivier moysan 13003e086edfSolivier moysan static int stm32_sai_sub_parse_of(struct platform_device *pdev, 13013e086edfSolivier moysan struct stm32_sai_sub_data *sai) 13023e086edfSolivier moysan { 13033e086edfSolivier moysan struct device_node *np = pdev->dev.of_node; 13043e086edfSolivier moysan struct resource *res; 13053e086edfSolivier moysan void __iomem *base; 13065914d285SOlivier Moysan struct of_phandle_args args; 13075914d285SOlivier Moysan int ret; 13083e086edfSolivier moysan 13093e086edfSolivier moysan if (!np) 13103e086edfSolivier moysan return -ENODEV; 13113e086edfSolivier moysan 13123e086edfSolivier moysan res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 13133e086edfSolivier moysan base = devm_ioremap_resource(&pdev->dev, res); 13143e086edfSolivier moysan if (IS_ERR(base)) 13153e086edfSolivier moysan return PTR_ERR(base); 13163e086edfSolivier moysan 13173e086edfSolivier moysan sai->phys_addr = res->start; 131803e78a24Solivier moysan 131903e78a24Solivier moysan sai->regmap_config = &stm32_sai_sub_regmap_config_f4; 13201d9c95c1SOlivier Moysan /* Note: PDM registers not available for sub-block B */ 13211d9c95c1SOlivier Moysan if (STM_SAI_HAS_PDM(sai) && STM_SAI_IS_SUB_A(sai)) 132203e78a24Solivier moysan sai->regmap_config = &stm32_sai_sub_regmap_config_h7; 132303e78a24Solivier moysan 132403e78a24Solivier moysan sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "sai_ck", 132503e78a24Solivier moysan base, sai->regmap_config); 132603e78a24Solivier moysan if (IS_ERR(sai->regmap)) { 132703e78a24Solivier moysan dev_err(&pdev->dev, "Failed to initialize MMIO\n"); 132803e78a24Solivier moysan return PTR_ERR(sai->regmap); 132903e78a24Solivier moysan } 13303e086edfSolivier moysan 13313e086edfSolivier moysan /* Get direction property */ 13323e086edfSolivier moysan if (of_property_match_string(np, "dma-names", "tx") >= 0) { 13333e086edfSolivier moysan sai->dir = SNDRV_PCM_STREAM_PLAYBACK; 13343e086edfSolivier moysan } else if (of_property_match_string(np, "dma-names", "rx") >= 0) { 13353e086edfSolivier moysan sai->dir = SNDRV_PCM_STREAM_CAPTURE; 13363e086edfSolivier moysan } else { 13373e086edfSolivier moysan dev_err(&pdev->dev, "Unsupported direction\n"); 13383e086edfSolivier moysan return -EINVAL; 13393e086edfSolivier moysan } 13403e086edfSolivier moysan 13416eb17d70SOlivier Moysan /* Get spdif iec60958 property */ 13426eb17d70SOlivier Moysan sai->spdif = false; 13436eb17d70SOlivier Moysan if (of_get_property(np, "st,iec60958", NULL)) { 13446eb17d70SOlivier Moysan if (!STM_SAI_HAS_SPDIF(sai) || 13456eb17d70SOlivier Moysan sai->dir == SNDRV_PCM_STREAM_CAPTURE) { 13466eb17d70SOlivier Moysan dev_err(&pdev->dev, "S/PDIF IEC60958 not supported\n"); 13476eb17d70SOlivier Moysan return -EINVAL; 13486eb17d70SOlivier Moysan } 1349187e01d0Solivier moysan stm32_sai_init_iec958_status(sai); 13506eb17d70SOlivier Moysan sai->spdif = true; 13516eb17d70SOlivier Moysan sai->master = true; 13526eb17d70SOlivier Moysan } 13536eb17d70SOlivier Moysan 13545914d285SOlivier Moysan /* Get synchronization property */ 13555914d285SOlivier Moysan args.np = NULL; 13565914d285SOlivier Moysan ret = of_parse_phandle_with_fixed_args(np, "st,sync", 1, 0, &args); 13575914d285SOlivier Moysan if (ret < 0 && ret != -ENOENT) { 13585914d285SOlivier Moysan dev_err(&pdev->dev, "Failed to get st,sync property\n"); 13595914d285SOlivier Moysan return ret; 13605914d285SOlivier Moysan } 13615914d285SOlivier Moysan 13625914d285SOlivier Moysan sai->sync = SAI_SYNC_NONE; 13635914d285SOlivier Moysan if (args.np) { 13645914d285SOlivier Moysan if (args.np == np) { 13655d585e1eSRob Herring dev_err(&pdev->dev, "%pOFn sync own reference\n", np); 13665914d285SOlivier Moysan of_node_put(args.np); 13675914d285SOlivier Moysan return -EINVAL; 13685914d285SOlivier Moysan } 13695914d285SOlivier Moysan 13705914d285SOlivier Moysan sai->np_sync_provider = of_get_parent(args.np); 13715914d285SOlivier Moysan if (!sai->np_sync_provider) { 13725d585e1eSRob Herring dev_err(&pdev->dev, "%pOFn parent node not found\n", 13735d585e1eSRob Herring np); 13745914d285SOlivier Moysan of_node_put(args.np); 13755914d285SOlivier Moysan return -ENODEV; 13765914d285SOlivier Moysan } 13775914d285SOlivier Moysan 13785914d285SOlivier Moysan sai->sync = SAI_SYNC_INTERNAL; 13795914d285SOlivier Moysan if (sai->np_sync_provider != sai->pdata->pdev->dev.of_node) { 13805914d285SOlivier Moysan if (!STM_SAI_HAS_EXT_SYNC(sai)) { 13815914d285SOlivier Moysan dev_err(&pdev->dev, 13825914d285SOlivier Moysan "External synchro not supported\n"); 13835914d285SOlivier Moysan of_node_put(args.np); 13845914d285SOlivier Moysan return -EINVAL; 13855914d285SOlivier Moysan } 13865914d285SOlivier Moysan sai->sync = SAI_SYNC_EXTERNAL; 13875914d285SOlivier Moysan 13885914d285SOlivier Moysan sai->synci = args.args[0]; 13895914d285SOlivier Moysan if (sai->synci < 1 || 13905914d285SOlivier Moysan (sai->synci > (SAI_GCR_SYNCIN_MAX + 1))) { 13915914d285SOlivier Moysan dev_err(&pdev->dev, "Wrong SAI index\n"); 13925914d285SOlivier Moysan of_node_put(args.np); 13935914d285SOlivier Moysan return -EINVAL; 13945914d285SOlivier Moysan } 13955914d285SOlivier Moysan 13965914d285SOlivier Moysan if (of_property_match_string(args.np, "compatible", 13975914d285SOlivier Moysan "st,stm32-sai-sub-a") >= 0) 13985914d285SOlivier Moysan sai->synco = STM_SAI_SYNC_OUT_A; 13995914d285SOlivier Moysan 14005914d285SOlivier Moysan if (of_property_match_string(args.np, "compatible", 14015914d285SOlivier Moysan "st,stm32-sai-sub-b") >= 0) 14025914d285SOlivier Moysan sai->synco = STM_SAI_SYNC_OUT_B; 14035914d285SOlivier Moysan 14045914d285SOlivier Moysan if (!sai->synco) { 14055914d285SOlivier Moysan dev_err(&pdev->dev, "Unknown SAI sub-block\n"); 14065914d285SOlivier Moysan of_node_put(args.np); 14075914d285SOlivier Moysan return -EINVAL; 14085914d285SOlivier Moysan } 14095914d285SOlivier Moysan } 14105914d285SOlivier Moysan 14115914d285SOlivier Moysan dev_dbg(&pdev->dev, "%s synchronized with %s\n", 14125914d285SOlivier Moysan pdev->name, args.np->full_name); 14135914d285SOlivier Moysan } 14145914d285SOlivier Moysan 14155914d285SOlivier Moysan of_node_put(args.np); 14163e086edfSolivier moysan sai->sai_ck = devm_clk_get(&pdev->dev, "sai_ck"); 14173e086edfSolivier moysan if (IS_ERR(sai->sai_ck)) { 1418602fdadcSolivier moysan dev_err(&pdev->dev, "Missing kernel clock sai_ck\n"); 14193e086edfSolivier moysan return PTR_ERR(sai->sai_ck); 14203e086edfSolivier moysan } 14213e086edfSolivier moysan 14228307b2afSOlivier Moysan if (STM_SAI_IS_F4(sai->pdata)) 14238307b2afSOlivier Moysan return 0; 14248307b2afSOlivier Moysan 14258307b2afSOlivier Moysan /* Register mclk provider if requested */ 14268307b2afSOlivier Moysan if (of_find_property(np, "#clock-cells", NULL)) { 14278307b2afSOlivier Moysan ret = stm32_sai_add_mclk_provider(sai); 14288307b2afSOlivier Moysan if (ret < 0) 14298307b2afSOlivier Moysan return ret; 14308307b2afSOlivier Moysan } else { 14318307b2afSOlivier Moysan sai->sai_mclk = devm_clk_get(&pdev->dev, "MCLK"); 14328307b2afSOlivier Moysan if (IS_ERR(sai->sai_mclk)) { 14338307b2afSOlivier Moysan if (PTR_ERR(sai->sai_mclk) != -ENOENT) 14348307b2afSOlivier Moysan return PTR_ERR(sai->sai_mclk); 14358307b2afSOlivier Moysan sai->sai_mclk = NULL; 14368307b2afSOlivier Moysan } 14378307b2afSOlivier Moysan } 14388307b2afSOlivier Moysan 14393e086edfSolivier moysan return 0; 14403e086edfSolivier moysan } 14413e086edfSolivier moysan 14423e086edfSolivier moysan static int stm32_sai_sub_probe(struct platform_device *pdev) 14433e086edfSolivier moysan { 14443e086edfSolivier moysan struct stm32_sai_sub_data *sai; 14453e086edfSolivier moysan const struct of_device_id *of_id; 14466eb17d70SOlivier Moysan const struct snd_dmaengine_pcm_config *conf = &stm32_sai_pcm_config; 14473e086edfSolivier moysan int ret; 14483e086edfSolivier moysan 14493e086edfSolivier moysan sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL); 14503e086edfSolivier moysan if (!sai) 14513e086edfSolivier moysan return -ENOMEM; 14523e086edfSolivier moysan 14533e086edfSolivier moysan of_id = of_match_device(stm32_sai_sub_ids, &pdev->dev); 14543e086edfSolivier moysan if (!of_id) 14553e086edfSolivier moysan return -EINVAL; 14563e086edfSolivier moysan sai->id = (uintptr_t)of_id->data; 14573e086edfSolivier moysan 14583e086edfSolivier moysan sai->pdev = pdev; 1459187e01d0Solivier moysan mutex_init(&sai->ctrl_lock); 146026f98e82SOlivier Moysan spin_lock_init(&sai->irq_lock); 14613e086edfSolivier moysan platform_set_drvdata(pdev, sai); 14623e086edfSolivier moysan 14633e086edfSolivier moysan sai->pdata = dev_get_drvdata(pdev->dev.parent); 14643e086edfSolivier moysan if (!sai->pdata) { 14653e086edfSolivier moysan dev_err(&pdev->dev, "Parent device data not available\n"); 14663e086edfSolivier moysan return -EINVAL; 14673e086edfSolivier moysan } 14683e086edfSolivier moysan 14693e086edfSolivier moysan ret = stm32_sai_sub_parse_of(pdev, sai); 14703e086edfSolivier moysan if (ret) 14713e086edfSolivier moysan return ret; 14723e086edfSolivier moysan 14738f8a5488SArnaud Pouliquen if (STM_SAI_IS_PLAYBACK(sai)) 14748f8a5488SArnaud Pouliquen sai->cpu_dai_drv = stm32_sai_playback_dai; 14758f8a5488SArnaud Pouliquen else 14768f8a5488SArnaud Pouliquen sai->cpu_dai_drv = stm32_sai_capture_dai; 14778f8a5488SArnaud Pouliquen sai->cpu_dai_drv.name = dev_name(&pdev->dev); 14783e086edfSolivier moysan 14793e086edfSolivier moysan ret = devm_request_irq(&pdev->dev, sai->pdata->irq, stm32_sai_isr, 14803e086edfSolivier moysan IRQF_SHARED, dev_name(&pdev->dev), sai); 14813e086edfSolivier moysan if (ret) { 1482602fdadcSolivier moysan dev_err(&pdev->dev, "IRQ request returned %d\n", ret); 14833e086edfSolivier moysan return ret; 14843e086edfSolivier moysan } 14853e086edfSolivier moysan 14863e086edfSolivier moysan ret = devm_snd_soc_register_component(&pdev->dev, &stm32_component, 14878f8a5488SArnaud Pouliquen &sai->cpu_dai_drv, 1); 14883e086edfSolivier moysan if (ret) 14893e086edfSolivier moysan return ret; 14903e086edfSolivier moysan 14916eb17d70SOlivier Moysan if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) 14926eb17d70SOlivier Moysan conf = &stm32_sai_pcm_config_spdif; 14936eb17d70SOlivier Moysan 14946eb17d70SOlivier Moysan ret = devm_snd_dmaengine_pcm_register(&pdev->dev, conf, 0); 14953e086edfSolivier moysan if (ret) { 1496602fdadcSolivier moysan dev_err(&pdev->dev, "Could not register pcm dma\n"); 14973e086edfSolivier moysan return ret; 14983e086edfSolivier moysan } 14993e086edfSolivier moysan 15003e086edfSolivier moysan return 0; 15013e086edfSolivier moysan } 15023e086edfSolivier moysan 1503cf881773SOlivier Moysan #ifdef CONFIG_PM_SLEEP 1504cf881773SOlivier Moysan static int stm32_sai_sub_suspend(struct device *dev) 1505cf881773SOlivier Moysan { 1506cf881773SOlivier Moysan struct stm32_sai_sub_data *sai = dev_get_drvdata(dev); 1507cf881773SOlivier Moysan 1508cf881773SOlivier Moysan regcache_cache_only(sai->regmap, true); 1509cf881773SOlivier Moysan regcache_mark_dirty(sai->regmap); 1510cf881773SOlivier Moysan return 0; 1511cf881773SOlivier Moysan } 1512cf881773SOlivier Moysan 1513cf881773SOlivier Moysan static int stm32_sai_sub_resume(struct device *dev) 1514cf881773SOlivier Moysan { 1515cf881773SOlivier Moysan struct stm32_sai_sub_data *sai = dev_get_drvdata(dev); 1516cf881773SOlivier Moysan 1517cf881773SOlivier Moysan regcache_cache_only(sai->regmap, false); 1518cf881773SOlivier Moysan return regcache_sync(sai->regmap); 1519cf881773SOlivier Moysan } 1520cf881773SOlivier Moysan #endif /* CONFIG_PM_SLEEP */ 1521cf881773SOlivier Moysan 1522cf881773SOlivier Moysan static const struct dev_pm_ops stm32_sai_sub_pm_ops = { 1523cf881773SOlivier Moysan SET_SYSTEM_SLEEP_PM_OPS(stm32_sai_sub_suspend, stm32_sai_sub_resume) 1524cf881773SOlivier Moysan }; 1525cf881773SOlivier Moysan 15263e086edfSolivier moysan static struct platform_driver stm32_sai_sub_driver = { 15273e086edfSolivier moysan .driver = { 15283e086edfSolivier moysan .name = "st,stm32-sai-sub", 15293e086edfSolivier moysan .of_match_table = stm32_sai_sub_ids, 1530cf881773SOlivier Moysan .pm = &stm32_sai_sub_pm_ops, 15313e086edfSolivier moysan }, 15323e086edfSolivier moysan .probe = stm32_sai_sub_probe, 15333e086edfSolivier moysan }; 15343e086edfSolivier moysan 15353e086edfSolivier moysan module_platform_driver(stm32_sai_sub_driver); 15363e086edfSolivier moysan 15373e086edfSolivier moysan MODULE_DESCRIPTION("STM32 Soc SAI sub-block Interface"); 1538602fdadcSolivier moysan MODULE_AUTHOR("Olivier Moysan <olivier.moysan@st.com>"); 15393e086edfSolivier moysan MODULE_ALIAS("platform:st,stm32-sai-sub"); 15403e086edfSolivier moysan MODULE_LICENSE("GPL v2"); 1541