1 /* 2 * STM32 ALSA SoC Digital Audio Interface (SAI) driver. 3 * 4 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved 5 * Author(s): Olivier Moysan <olivier.moysan@st.com> for STMicroelectronics. 6 * 7 * License terms: GPL V2.0. 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License version 2 as published by 11 * the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more 16 * details. 17 */ 18 19 /******************** SAI Register Map **************************************/ 20 21 /* common register */ 22 #define STM_SAI_GCR 0x00 23 24 /* Sub-block A&B registers offsets, relative to A&B sub-block addresses */ 25 #define STM_SAI_CR1_REGX 0x00 /* A offset: 0x04. B offset: 0x24 */ 26 #define STM_SAI_CR2_REGX 0x04 27 #define STM_SAI_FRCR_REGX 0x08 28 #define STM_SAI_SLOTR_REGX 0x0C 29 #define STM_SAI_IMR_REGX 0x10 30 #define STM_SAI_SR_REGX 0x14 31 #define STM_SAI_CLRFR_REGX 0x18 32 #define STM_SAI_DR_REGX 0x1C 33 34 /******************** Bit definition for SAI_GCR register *******************/ 35 #define SAI_GCR_SYNCIN_SHIFT 0 36 #define SAI_GCR_SYNCIN_MASK GENMASK(1, SAI_GCR_SYNCIN_SHIFT) 37 #define SAI_GCR_SYNCIN_SET(x) ((x) << SAI_GCR_SYNCIN_SHIFT) 38 39 #define SAI_GCR_SYNCOUT_SHIFT 4 40 #define SAI_GCR_SYNCOUT_MASK GENMASK(5, SAI_GCR_SYNCOUT_SHIFT) 41 #define SAI_GCR_SYNCOUT_SET(x) ((x) << SAI_GCR_SYNCOUT_SHIFT) 42 43 /******************* Bit definition for SAI_XCR1 register *******************/ 44 #define SAI_XCR1_RX_TX_SHIFT 0 45 #define SAI_XCR1_RX_TX BIT(SAI_XCR1_RX_TX_SHIFT) 46 #define SAI_XCR1_SLAVE_SHIFT 1 47 #define SAI_XCR1_SLAVE BIT(SAI_XCR1_SLAVE_SHIFT) 48 49 #define SAI_XCR1_PRTCFG_SHIFT 2 50 #define SAI_XCR1_PRTCFG_MASK GENMASK(3, SAI_XCR1_PRTCFG_SHIFT) 51 #define SAI_XCR1_PRTCFG_SET(x) ((x) << SAI_XCR1_PRTCFG_SHIFT) 52 53 #define SAI_XCR1_DS_SHIFT 5 54 #define SAI_XCR1_DS_MASK GENMASK(7, SAI_XCR1_DS_SHIFT) 55 #define SAI_XCR1_DS_SET(x) ((x) << SAI_XCR1_DS_SHIFT) 56 57 #define SAI_XCR1_LSBFIRST_SHIFT 8 58 #define SAI_XCR1_LSBFIRST BIT(SAI_XCR1_LSBFIRST_SHIFT) 59 #define SAI_XCR1_CKSTR_SHIFT 9 60 #define SAI_XCR1_CKSTR BIT(SAI_XCR1_CKSTR_SHIFT) 61 62 #define SAI_XCR1_SYNCEN_SHIFT 10 63 #define SAI_XCR1_SYNCEN_MASK GENMASK(11, SAI_XCR1_SYNCEN_SHIFT) 64 #define SAI_XCR1_SYNCEN_SET(x) ((x) << SAI_XCR1_SYNCEN_SHIFT) 65 66 #define SAI_XCR1_MONO_SHIFT 12 67 #define SAI_XCR1_MONO BIT(SAI_XCR1_MONO_SHIFT) 68 #define SAI_XCR1_OUTDRIV_SHIFT 13 69 #define SAI_XCR1_OUTDRIV BIT(SAI_XCR1_OUTDRIV_SHIFT) 70 #define SAI_XCR1_SAIEN_SHIFT 16 71 #define SAI_XCR1_SAIEN BIT(SAI_XCR1_SAIEN_SHIFT) 72 #define SAI_XCR1_DMAEN_SHIFT 17 73 #define SAI_XCR1_DMAEN BIT(SAI_XCR1_DMAEN_SHIFT) 74 #define SAI_XCR1_NODIV_SHIFT 19 75 #define SAI_XCR1_NODIV BIT(SAI_XCR1_NODIV_SHIFT) 76 77 #define SAI_XCR1_MCKDIV_SHIFT 20 78 #define SAI_XCR1_MCKDIV_WIDTH 4 79 #define SAI_XCR1_MCKDIV_MASK GENMASK(24, SAI_XCR1_MCKDIV_SHIFT) 80 #define SAI_XCR1_MCKDIV_SET(x) ((x) << SAI_XCR1_MCKDIV_SHIFT) 81 #define SAI_XCR1_MCKDIV_MAX ((1 << SAI_XCR1_MCKDIV_WIDTH) - 1) 82 83 #define SAI_XCR1_OSR_SHIFT 26 84 #define SAI_XCR1_OSR BIT(SAI_XCR1_OSR_SHIFT) 85 86 /******************* Bit definition for SAI_XCR2 register *******************/ 87 #define SAI_XCR2_FTH_SHIFT 0 88 #define SAI_XCR2_FTH_MASK GENMASK(2, SAI_XCR2_FTH_SHIFT) 89 #define SAI_XCR2_FTH_SET(x) ((x) << SAI_XCR2_FTH_SHIFT) 90 91 #define SAI_XCR2_FFLUSH_SHIFT 3 92 #define SAI_XCR2_FFLUSH BIT(SAI_XCR2_FFLUSH_SHIFT) 93 #define SAI_XCR2_TRIS_SHIFT 4 94 #define SAI_XCR2_TRIS BIT(SAI_XCR2_TRIS_SHIFT) 95 #define SAI_XCR2_MUTE_SHIFT 5 96 #define SAI_XCR2_MUTE BIT(SAI_XCR2_MUTE_SHIFT) 97 #define SAI_XCR2_MUTEVAL_SHIFT 6 98 #define SAI_XCR2_MUTEVAL BIT(SAI_XCR2_MUTEVAL_SHIFT) 99 100 #define SAI_XCR2_MUTECNT_SHIFT 7 101 #define SAI_XCR2_MUTECNT_MASK GENMASK(12, SAI_XCR2_MUTECNT_SHIFT) 102 #define SAI_XCR2_MUTECNT_SET(x) ((x) << SAI_XCR2_MUTECNT_SHIFT) 103 104 #define SAI_XCR2_CPL_SHIFT 13 105 #define SAI_XCR2_CPL BIT(SAI_XCR2_CPL_SHIFT) 106 107 #define SAI_XCR2_COMP_SHIFT 14 108 #define SAI_XCR2_COMP_MASK GENMASK(15, SAI_XCR2_COMP_SHIFT) 109 #define SAI_XCR2_COMP_SET(x) ((x) << SAI_XCR2_COMP_SHIFT) 110 111 /****************** Bit definition for SAI_XFRCR register *******************/ 112 #define SAI_XFRCR_FRL_SHIFT 0 113 #define SAI_XFRCR_FRL_MASK GENMASK(7, SAI_XFRCR_FRL_SHIFT) 114 #define SAI_XFRCR_FRL_SET(x) ((x) << SAI_XFRCR_FRL_SHIFT) 115 116 #define SAI_XFRCR_FSALL_SHIFT 8 117 #define SAI_XFRCR_FSALL_MASK GENMASK(14, SAI_XFRCR_FSALL_SHIFT) 118 #define SAI_XFRCR_FSALL_SET(x) ((x) << SAI_XFRCR_FSALL_SHIFT) 119 120 #define SAI_XFRCR_FSDEF_SHIFT 16 121 #define SAI_XFRCR_FSDEF BIT(SAI_XFRCR_FSDEF_SHIFT) 122 #define SAI_XFRCR_FSPOL_SHIFT 17 123 #define SAI_XFRCR_FSPOL BIT(SAI_XFRCR_FSPOL_SHIFT) 124 #define SAI_XFRCR_FSOFF_SHIFT 18 125 #define SAI_XFRCR_FSOFF BIT(SAI_XFRCR_FSOFF_SHIFT) 126 127 /****************** Bit definition for SAI_XSLOTR register ******************/ 128 129 #define SAI_XSLOTR_FBOFF_SHIFT 0 130 #define SAI_XSLOTR_FBOFF_MASK GENMASK(4, SAI_XSLOTR_FBOFF_SHIFT) 131 #define SAI_XSLOTR_FBOFF_SET(x) ((x) << SAI_XSLOTR_FBOFF_SHIFT) 132 133 #define SAI_XSLOTR_SLOTSZ_SHIFT 6 134 #define SAI_XSLOTR_SLOTSZ_MASK GENMASK(7, SAI_XSLOTR_SLOTSZ_SHIFT) 135 #define SAI_XSLOTR_SLOTSZ_SET(x) ((x) << SAI_XSLOTR_SLOTSZ_SHIFT) 136 137 #define SAI_XSLOTR_NBSLOT_SHIFT 8 138 #define SAI_XSLOTR_NBSLOT_MASK GENMASK(11, SAI_XSLOTR_NBSLOT_SHIFT) 139 #define SAI_XSLOTR_NBSLOT_SET(x) ((x) << SAI_XSLOTR_NBSLOT_SHIFT) 140 141 #define SAI_XSLOTR_SLOTEN_SHIFT 16 142 #define SAI_XSLOTR_SLOTEN_WIDTH 16 143 #define SAI_XSLOTR_SLOTEN_MASK GENMASK(31, SAI_XSLOTR_SLOTEN_SHIFT) 144 #define SAI_XSLOTR_SLOTEN_SET(x) ((x) << SAI_XSLOTR_SLOTEN_SHIFT) 145 146 /******************* Bit definition for SAI_XIMR register *******************/ 147 #define SAI_XIMR_OVRUDRIE BIT(0) 148 #define SAI_XIMR_MUTEDETIE BIT(1) 149 #define SAI_XIMR_WCKCFGIE BIT(2) 150 #define SAI_XIMR_FREQIE BIT(3) 151 #define SAI_XIMR_CNRDYIE BIT(4) 152 #define SAI_XIMR_AFSDETIE BIT(5) 153 #define SAI_XIMR_LFSDETIE BIT(6) 154 155 #define SAI_XIMR_SHIFT 0 156 #define SAI_XIMR_MASK GENMASK(6, SAI_XIMR_SHIFT) 157 158 /******************** Bit definition for SAI_XSR register *******************/ 159 #define SAI_XSR_OVRUDR BIT(0) 160 #define SAI_XSR_MUTEDET BIT(1) 161 #define SAI_XSR_WCKCFG BIT(2) 162 #define SAI_XSR_FREQ BIT(3) 163 #define SAI_XSR_CNRDY BIT(4) 164 #define SAI_XSR_AFSDET BIT(5) 165 #define SAI_XSR_LFSDET BIT(6) 166 167 #define SAI_XSR_SHIFT 0 168 #define SAI_XSR_MASK GENMASK(6, SAI_XSR_SHIFT) 169 170 /****************** Bit definition for SAI_XCLRFR register ******************/ 171 #define SAI_XCLRFR_COVRUDR BIT(0) 172 #define SAI_XCLRFR_CMUTEDET BIT(1) 173 #define SAI_XCLRFR_CWCKCFG BIT(2) 174 #define SAI_XCLRFR_CFREQ BIT(3) 175 #define SAI_XCLRFR_CCNRDY BIT(4) 176 #define SAI_XCLRFR_CAFSDET BIT(5) 177 #define SAI_XCLRFR_CLFSDET BIT(6) 178 179 #define SAI_XCLRFR_SHIFT 0 180 #define SAI_XCLRFR_MASK GENMASK(6, SAI_XCLRFR_SHIFT) 181 182 enum stm32_sai_version { 183 SAI_STM32F4 184 }; 185 186 /** 187 * struct stm32_sai_data - private data of SAI instance driver 188 * @pdev: device data pointer 189 * @clk_x8k: SAI parent clock for sampling frequencies multiple of 8kHz 190 * @clk_x11k: SAI parent clock for sampling frequencies multiple of 11kHz 191 * @version: SOC version 192 * @irq: SAI interrupt line 193 */ 194 struct stm32_sai_data { 195 struct platform_device *pdev; 196 struct clk *clk_x8k; 197 struct clk *clk_x11k; 198 int version; 199 int irq; 200 }; 201