1 /* 2 * STM32 ALSA SoC Digital Audio Interface (SAI) driver. 3 * 4 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved 5 * Author(s): Olivier Moysan <olivier.moysan@st.com> for STMicroelectronics. 6 * 7 * License terms: GPL V2.0. 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License version 2 as published by 11 * the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more 16 * details. 17 */ 18 19 #include <linux/bitfield.h> 20 21 /******************** SAI Register Map **************************************/ 22 23 /* Global configuration register */ 24 #define STM_SAI_GCR 0x00 25 26 /* Sub-block A&B registers offsets, relative to A&B sub-block addresses */ 27 #define STM_SAI_CR1_REGX 0x00 /* A offset: 0x04. B offset: 0x24 */ 28 #define STM_SAI_CR2_REGX 0x04 29 #define STM_SAI_FRCR_REGX 0x08 30 #define STM_SAI_SLOTR_REGX 0x0C 31 #define STM_SAI_IMR_REGX 0x10 32 #define STM_SAI_SR_REGX 0x14 33 #define STM_SAI_CLRFR_REGX 0x18 34 #define STM_SAI_DR_REGX 0x1C 35 36 /* Sub-block A registers, relative to sub-block A address */ 37 #define STM_SAI_PDMCR_REGX 0x40 38 #define STM_SAI_PDMLY_REGX 0x44 39 40 /******************** Bit definition for SAI_GCR register *******************/ 41 #define SAI_GCR_SYNCIN_SHIFT 0 42 #define SAI_GCR_SYNCIN_WDTH 2 43 #define SAI_GCR_SYNCIN_MASK GENMASK(1, SAI_GCR_SYNCIN_SHIFT) 44 #define SAI_GCR_SYNCIN_MAX FIELD_GET(SAI_GCR_SYNCIN_MASK,\ 45 SAI_GCR_SYNCIN_MASK) 46 47 #define SAI_GCR_SYNCOUT_SHIFT 4 48 #define SAI_GCR_SYNCOUT_MASK GENMASK(5, SAI_GCR_SYNCOUT_SHIFT) 49 50 /******************* Bit definition for SAI_XCR1 register *******************/ 51 #define SAI_XCR1_RX_TX_SHIFT 0 52 #define SAI_XCR1_RX_TX BIT(SAI_XCR1_RX_TX_SHIFT) 53 #define SAI_XCR1_SLAVE_SHIFT 1 54 #define SAI_XCR1_SLAVE BIT(SAI_XCR1_SLAVE_SHIFT) 55 56 #define SAI_XCR1_PRTCFG_SHIFT 2 57 #define SAI_XCR1_PRTCFG_MASK GENMASK(3, SAI_XCR1_PRTCFG_SHIFT) 58 #define SAI_XCR1_PRTCFG_SET(x) ((x) << SAI_XCR1_PRTCFG_SHIFT) 59 60 #define SAI_XCR1_DS_SHIFT 5 61 #define SAI_XCR1_DS_MASK GENMASK(7, SAI_XCR1_DS_SHIFT) 62 #define SAI_XCR1_DS_SET(x) ((x) << SAI_XCR1_DS_SHIFT) 63 64 #define SAI_XCR1_LSBFIRST_SHIFT 8 65 #define SAI_XCR1_LSBFIRST BIT(SAI_XCR1_LSBFIRST_SHIFT) 66 #define SAI_XCR1_CKSTR_SHIFT 9 67 #define SAI_XCR1_CKSTR BIT(SAI_XCR1_CKSTR_SHIFT) 68 69 #define SAI_XCR1_SYNCEN_SHIFT 10 70 #define SAI_XCR1_SYNCEN_MASK GENMASK(11, SAI_XCR1_SYNCEN_SHIFT) 71 #define SAI_XCR1_SYNCEN_SET(x) ((x) << SAI_XCR1_SYNCEN_SHIFT) 72 73 #define SAI_XCR1_MONO_SHIFT 12 74 #define SAI_XCR1_MONO BIT(SAI_XCR1_MONO_SHIFT) 75 #define SAI_XCR1_OUTDRIV_SHIFT 13 76 #define SAI_XCR1_OUTDRIV BIT(SAI_XCR1_OUTDRIV_SHIFT) 77 #define SAI_XCR1_SAIEN_SHIFT 16 78 #define SAI_XCR1_SAIEN BIT(SAI_XCR1_SAIEN_SHIFT) 79 #define SAI_XCR1_DMAEN_SHIFT 17 80 #define SAI_XCR1_DMAEN BIT(SAI_XCR1_DMAEN_SHIFT) 81 #define SAI_XCR1_NODIV_SHIFT 19 82 #define SAI_XCR1_NODIV BIT(SAI_XCR1_NODIV_SHIFT) 83 84 #define SAI_XCR1_MCKDIV_SHIFT 20 85 #define SAI_XCR1_MCKDIV_WIDTH(x) (((x) == SAI_STM32F4) ? 4 : 6) 86 #define SAI_XCR1_MCKDIV_MASK(x) GENMASK((SAI_XCR1_MCKDIV_SHIFT + (x) - 1),\ 87 SAI_XCR1_MCKDIV_SHIFT) 88 #define SAI_XCR1_MCKDIV_SET(x) ((x) << SAI_XCR1_MCKDIV_SHIFT) 89 #define SAI_XCR1_MCKDIV_MAX(x) ((1 << SAI_XCR1_MCKDIV_WIDTH(x)) - 1) 90 91 #define SAI_XCR1_OSR_SHIFT 26 92 #define SAI_XCR1_OSR BIT(SAI_XCR1_OSR_SHIFT) 93 94 /******************* Bit definition for SAI_XCR2 register *******************/ 95 #define SAI_XCR2_FTH_SHIFT 0 96 #define SAI_XCR2_FTH_MASK GENMASK(2, SAI_XCR2_FTH_SHIFT) 97 #define SAI_XCR2_FTH_SET(x) ((x) << SAI_XCR2_FTH_SHIFT) 98 99 #define SAI_XCR2_FFLUSH_SHIFT 3 100 #define SAI_XCR2_FFLUSH BIT(SAI_XCR2_FFLUSH_SHIFT) 101 #define SAI_XCR2_TRIS_SHIFT 4 102 #define SAI_XCR2_TRIS BIT(SAI_XCR2_TRIS_SHIFT) 103 #define SAI_XCR2_MUTE_SHIFT 5 104 #define SAI_XCR2_MUTE BIT(SAI_XCR2_MUTE_SHIFT) 105 #define SAI_XCR2_MUTEVAL_SHIFT 6 106 #define SAI_XCR2_MUTEVAL BIT(SAI_XCR2_MUTEVAL_SHIFT) 107 108 #define SAI_XCR2_MUTECNT_SHIFT 7 109 #define SAI_XCR2_MUTECNT_MASK GENMASK(12, SAI_XCR2_MUTECNT_SHIFT) 110 #define SAI_XCR2_MUTECNT_SET(x) ((x) << SAI_XCR2_MUTECNT_SHIFT) 111 112 #define SAI_XCR2_CPL_SHIFT 13 113 #define SAI_XCR2_CPL BIT(SAI_XCR2_CPL_SHIFT) 114 115 #define SAI_XCR2_COMP_SHIFT 14 116 #define SAI_XCR2_COMP_MASK GENMASK(15, SAI_XCR2_COMP_SHIFT) 117 #define SAI_XCR2_COMP_SET(x) ((x) << SAI_XCR2_COMP_SHIFT) 118 119 /****************** Bit definition for SAI_XFRCR register *******************/ 120 #define SAI_XFRCR_FRL_SHIFT 0 121 #define SAI_XFRCR_FRL_MASK GENMASK(7, SAI_XFRCR_FRL_SHIFT) 122 #define SAI_XFRCR_FRL_SET(x) ((x) << SAI_XFRCR_FRL_SHIFT) 123 124 #define SAI_XFRCR_FSALL_SHIFT 8 125 #define SAI_XFRCR_FSALL_MASK GENMASK(14, SAI_XFRCR_FSALL_SHIFT) 126 #define SAI_XFRCR_FSALL_SET(x) ((x) << SAI_XFRCR_FSALL_SHIFT) 127 128 #define SAI_XFRCR_FSDEF_SHIFT 16 129 #define SAI_XFRCR_FSDEF BIT(SAI_XFRCR_FSDEF_SHIFT) 130 #define SAI_XFRCR_FSPOL_SHIFT 17 131 #define SAI_XFRCR_FSPOL BIT(SAI_XFRCR_FSPOL_SHIFT) 132 #define SAI_XFRCR_FSOFF_SHIFT 18 133 #define SAI_XFRCR_FSOFF BIT(SAI_XFRCR_FSOFF_SHIFT) 134 135 /****************** Bit definition for SAI_XSLOTR register ******************/ 136 #define SAI_XSLOTR_FBOFF_SHIFT 0 137 #define SAI_XSLOTR_FBOFF_MASK GENMASK(4, SAI_XSLOTR_FBOFF_SHIFT) 138 #define SAI_XSLOTR_FBOFF_SET(x) ((x) << SAI_XSLOTR_FBOFF_SHIFT) 139 140 #define SAI_XSLOTR_SLOTSZ_SHIFT 6 141 #define SAI_XSLOTR_SLOTSZ_MASK GENMASK(7, SAI_XSLOTR_SLOTSZ_SHIFT) 142 #define SAI_XSLOTR_SLOTSZ_SET(x) ((x) << SAI_XSLOTR_SLOTSZ_SHIFT) 143 144 #define SAI_XSLOTR_NBSLOT_SHIFT 8 145 #define SAI_XSLOTR_NBSLOT_MASK GENMASK(11, SAI_XSLOTR_NBSLOT_SHIFT) 146 #define SAI_XSLOTR_NBSLOT_SET(x) ((x) << SAI_XSLOTR_NBSLOT_SHIFT) 147 148 #define SAI_XSLOTR_SLOTEN_SHIFT 16 149 #define SAI_XSLOTR_SLOTEN_WIDTH 16 150 #define SAI_XSLOTR_SLOTEN_MASK GENMASK(31, SAI_XSLOTR_SLOTEN_SHIFT) 151 #define SAI_XSLOTR_SLOTEN_SET(x) ((x) << SAI_XSLOTR_SLOTEN_SHIFT) 152 153 /******************* Bit definition for SAI_XIMR register *******************/ 154 #define SAI_XIMR_OVRUDRIE BIT(0) 155 #define SAI_XIMR_MUTEDETIE BIT(1) 156 #define SAI_XIMR_WCKCFGIE BIT(2) 157 #define SAI_XIMR_FREQIE BIT(3) 158 #define SAI_XIMR_CNRDYIE BIT(4) 159 #define SAI_XIMR_AFSDETIE BIT(5) 160 #define SAI_XIMR_LFSDETIE BIT(6) 161 162 #define SAI_XIMR_SHIFT 0 163 #define SAI_XIMR_MASK GENMASK(6, SAI_XIMR_SHIFT) 164 165 /******************** Bit definition for SAI_XSR register *******************/ 166 #define SAI_XSR_OVRUDR BIT(0) 167 #define SAI_XSR_MUTEDET BIT(1) 168 #define SAI_XSR_WCKCFG BIT(2) 169 #define SAI_XSR_FREQ BIT(3) 170 #define SAI_XSR_CNRDY BIT(4) 171 #define SAI_XSR_AFSDET BIT(5) 172 #define SAI_XSR_LFSDET BIT(6) 173 174 #define SAI_XSR_SHIFT 0 175 #define SAI_XSR_MASK GENMASK(6, SAI_XSR_SHIFT) 176 177 /****************** Bit definition for SAI_XCLRFR register ******************/ 178 #define SAI_XCLRFR_COVRUDR BIT(0) 179 #define SAI_XCLRFR_CMUTEDET BIT(1) 180 #define SAI_XCLRFR_CWCKCFG BIT(2) 181 #define SAI_XCLRFR_CFREQ BIT(3) 182 #define SAI_XCLRFR_CCNRDY BIT(4) 183 #define SAI_XCLRFR_CAFSDET BIT(5) 184 #define SAI_XCLRFR_CLFSDET BIT(6) 185 186 #define SAI_XCLRFR_SHIFT 0 187 #define SAI_XCLRFR_MASK GENMASK(6, SAI_XCLRFR_SHIFT) 188 189 /****************** Bit definition for SAI_PDMCR register ******************/ 190 #define SAI_PDMCR_PDMEN BIT(0) 191 192 #define SAI_PDMCR_MICNBR_SHIFT 4 193 #define SAI_PDMCR_MICNBR_MASK GENMASK(5, SAI_PDMCR_MICNBR_SHIFT) 194 #define SAI_PDMCR_MICNBR_SET(x) ((x) << SAI_PDMCR_MICNBR_SHIFT) 195 196 #define SAI_PDMCR_CKEN1 BIT(8) 197 #define SAI_PDMCR_CKEN2 BIT(9) 198 #define SAI_PDMCR_CKEN3 BIT(10) 199 #define SAI_PDMCR_CKEN4 BIT(11) 200 201 /****************** Bit definition for (SAI_PDMDLY register ****************/ 202 #define SAI_PDMDLY_1L_SHIFT 0 203 #define SAI_PDMDLY_1L_MASK GENMASK(2, SAI_PDMDLY_1L_SHIFT) 204 #define SAI_PDMDLY_1L_WIDTH 3 205 206 #define SAI_PDMDLY_1R_SHIFT 4 207 #define SAI_PDMDLY_1R_MASK GENMASK(6, SAI_PDMDLY_1R_SHIFT) 208 #define SAI_PDMDLY_1R_WIDTH 3 209 210 #define SAI_PDMDLY_2L_SHIFT 8 211 #define SAI_PDMDLY_2L_MASK GENMASK(10, SAI_PDMDLY_2L_SHIFT) 212 #define SAI_PDMDLY_2L_WIDTH 3 213 214 #define SAI_PDMDLY_2R_SHIFT 12 215 #define SAI_PDMDLY_2R_MASK GENMASK(14, SAI_PDMDLY_2R_SHIFT) 216 #define SAI_PDMDLY_2R_WIDTH 3 217 218 #define SAI_PDMDLY_3L_SHIFT 16 219 #define SAI_PDMDLY_3L_MASK GENMASK(18, SAI_PDMDLY_3L_SHIFT) 220 #define SAI_PDMDLY_3L_WIDTH 3 221 222 #define SAI_PDMDLY_3R_SHIFT 20 223 #define SAI_PDMDLY_3R_MASK GENMASK(22, SAI_PDMDLY_3R_SHIFT) 224 #define SAI_PDMDLY_3R_WIDTH 3 225 226 #define SAI_PDMDLY_4L_SHIFT 24 227 #define SAI_PDMDLY_4L_MASK GENMASK(26, SAI_PDMDLY_4L_SHIFT) 228 #define SAI_PDMDLY_4L_WIDTH 3 229 230 #define SAI_PDMDLY_4R_SHIFT 28 231 #define SAI_PDMDLY_4R_MASK GENMASK(30, SAI_PDMDLY_4R_SHIFT) 232 #define SAI_PDMDLY_4R_WIDTH 3 233 234 #define STM_SAI_IS_F4(ip) ((ip)->conf->version == SAI_STM32F4) 235 #define STM_SAI_IS_H7(ip) ((ip)->conf->version == SAI_STM32H7) 236 237 enum stm32_sai_syncout { 238 STM_SAI_SYNC_OUT_NONE, 239 STM_SAI_SYNC_OUT_A, 240 STM_SAI_SYNC_OUT_B, 241 }; 242 243 enum stm32_sai_version { 244 SAI_STM32F4, 245 SAI_STM32H7 246 }; 247 248 /** 249 * struct stm32_sai_conf - SAI configuration 250 * @version: SAI version 251 * @has_spdif: SAI S/PDIF support flag 252 */ 253 struct stm32_sai_conf { 254 int version; 255 bool has_spdif; 256 }; 257 258 /** 259 * struct stm32_sai_data - private data of SAI instance driver 260 * @pdev: device data pointer 261 * @base: common register bank virtual base address 262 * @pclk: SAI bus clock 263 * @clk_x8k: SAI parent clock for sampling frequencies multiple of 8kHz 264 * @clk_x11k: SAI parent clock for sampling frequencies multiple of 11kHz 265 * @version: SOC version 266 * @irq: SAI interrupt line 267 * @set_sync: pointer to synchro mode configuration callback 268 */ 269 struct stm32_sai_data { 270 struct platform_device *pdev; 271 void __iomem *base; 272 struct clk *pclk; 273 struct clk *clk_x8k; 274 struct clk *clk_x11k; 275 struct stm32_sai_conf *conf; 276 int irq; 277 int (*set_sync)(struct stm32_sai_data *sai, 278 struct device_node *np_provider, int synco, int synci); 279 }; 280