1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * STM32 ALSA SoC Digital Audio Interface (I2S) driver. 4 * 5 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved 6 * Author(s): Olivier Moysan <olivier.moysan@st.com> for STMicroelectronics. 7 */ 8 9 #include <linux/bitfield.h> 10 #include <linux/clk.h> 11 #include <linux/clk-provider.h> 12 #include <linux/delay.h> 13 #include <linux/module.h> 14 #include <linux/of_irq.h> 15 #include <linux/of_platform.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/regmap.h> 18 #include <linux/reset.h> 19 #include <linux/spinlock.h> 20 21 #include <sound/dmaengine_pcm.h> 22 #include <sound/pcm_params.h> 23 24 #define STM32_I2S_CR1_REG 0x0 25 #define STM32_I2S_CFG1_REG 0x08 26 #define STM32_I2S_CFG2_REG 0x0C 27 #define STM32_I2S_IER_REG 0x10 28 #define STM32_I2S_SR_REG 0x14 29 #define STM32_I2S_IFCR_REG 0x18 30 #define STM32_I2S_TXDR_REG 0X20 31 #define STM32_I2S_RXDR_REG 0x30 32 #define STM32_I2S_CGFR_REG 0X50 33 #define STM32_I2S_HWCFGR_REG 0x3F0 34 #define STM32_I2S_VERR_REG 0x3F4 35 #define STM32_I2S_IPIDR_REG 0x3F8 36 #define STM32_I2S_SIDR_REG 0x3FC 37 38 /* Bit definition for SPI2S_CR1 register */ 39 #define I2S_CR1_SPE BIT(0) 40 #define I2S_CR1_CSTART BIT(9) 41 #define I2S_CR1_CSUSP BIT(10) 42 #define I2S_CR1_HDDIR BIT(11) 43 #define I2S_CR1_SSI BIT(12) 44 #define I2S_CR1_CRC33_17 BIT(13) 45 #define I2S_CR1_RCRCI BIT(14) 46 #define I2S_CR1_TCRCI BIT(15) 47 48 /* Bit definition for SPI_CFG2 register */ 49 #define I2S_CFG2_IOSWP_SHIFT 15 50 #define I2S_CFG2_IOSWP BIT(I2S_CFG2_IOSWP_SHIFT) 51 #define I2S_CFG2_LSBFRST BIT(23) 52 #define I2S_CFG2_AFCNTR BIT(31) 53 54 /* Bit definition for SPI_CFG1 register */ 55 #define I2S_CFG1_FTHVL_SHIFT 5 56 #define I2S_CFG1_FTHVL_MASK GENMASK(8, I2S_CFG1_FTHVL_SHIFT) 57 #define I2S_CFG1_FTHVL_SET(x) ((x) << I2S_CFG1_FTHVL_SHIFT) 58 59 #define I2S_CFG1_TXDMAEN BIT(15) 60 #define I2S_CFG1_RXDMAEN BIT(14) 61 62 /* Bit definition for SPI2S_IER register */ 63 #define I2S_IER_RXPIE BIT(0) 64 #define I2S_IER_TXPIE BIT(1) 65 #define I2S_IER_DPXPIE BIT(2) 66 #define I2S_IER_EOTIE BIT(3) 67 #define I2S_IER_TXTFIE BIT(4) 68 #define I2S_IER_UDRIE BIT(5) 69 #define I2S_IER_OVRIE BIT(6) 70 #define I2S_IER_CRCEIE BIT(7) 71 #define I2S_IER_TIFREIE BIT(8) 72 #define I2S_IER_MODFIE BIT(9) 73 #define I2S_IER_TSERFIE BIT(10) 74 75 /* Bit definition for SPI2S_SR register */ 76 #define I2S_SR_RXP BIT(0) 77 #define I2S_SR_TXP BIT(1) 78 #define I2S_SR_DPXP BIT(2) 79 #define I2S_SR_EOT BIT(3) 80 #define I2S_SR_TXTF BIT(4) 81 #define I2S_SR_UDR BIT(5) 82 #define I2S_SR_OVR BIT(6) 83 #define I2S_SR_CRCERR BIT(7) 84 #define I2S_SR_TIFRE BIT(8) 85 #define I2S_SR_MODF BIT(9) 86 #define I2S_SR_TSERF BIT(10) 87 #define I2S_SR_SUSP BIT(11) 88 #define I2S_SR_TXC BIT(12) 89 #define I2S_SR_RXPLVL GENMASK(14, 13) 90 #define I2S_SR_RXWNE BIT(15) 91 92 #define I2S_SR_MASK GENMASK(15, 0) 93 94 /* Bit definition for SPI_IFCR register */ 95 #define I2S_IFCR_EOTC BIT(3) 96 #define I2S_IFCR_TXTFC BIT(4) 97 #define I2S_IFCR_UDRC BIT(5) 98 #define I2S_IFCR_OVRC BIT(6) 99 #define I2S_IFCR_CRCEC BIT(7) 100 #define I2S_IFCR_TIFREC BIT(8) 101 #define I2S_IFCR_MODFC BIT(9) 102 #define I2S_IFCR_TSERFC BIT(10) 103 #define I2S_IFCR_SUSPC BIT(11) 104 105 #define I2S_IFCR_MASK GENMASK(11, 3) 106 107 /* Bit definition for SPI_I2SCGFR register */ 108 #define I2S_CGFR_I2SMOD BIT(0) 109 110 #define I2S_CGFR_I2SCFG_SHIFT 1 111 #define I2S_CGFR_I2SCFG_MASK GENMASK(3, I2S_CGFR_I2SCFG_SHIFT) 112 #define I2S_CGFR_I2SCFG_SET(x) ((x) << I2S_CGFR_I2SCFG_SHIFT) 113 114 #define I2S_CGFR_I2SSTD_SHIFT 4 115 #define I2S_CGFR_I2SSTD_MASK GENMASK(5, I2S_CGFR_I2SSTD_SHIFT) 116 #define I2S_CGFR_I2SSTD_SET(x) ((x) << I2S_CGFR_I2SSTD_SHIFT) 117 118 #define I2S_CGFR_PCMSYNC BIT(7) 119 120 #define I2S_CGFR_DATLEN_SHIFT 8 121 #define I2S_CGFR_DATLEN_MASK GENMASK(9, I2S_CGFR_DATLEN_SHIFT) 122 #define I2S_CGFR_DATLEN_SET(x) ((x) << I2S_CGFR_DATLEN_SHIFT) 123 124 #define I2S_CGFR_CHLEN_SHIFT 10 125 #define I2S_CGFR_CHLEN BIT(I2S_CGFR_CHLEN_SHIFT) 126 #define I2S_CGFR_CKPOL BIT(11) 127 #define I2S_CGFR_FIXCH BIT(12) 128 #define I2S_CGFR_WSINV BIT(13) 129 #define I2S_CGFR_DATFMT BIT(14) 130 131 #define I2S_CGFR_I2SDIV_SHIFT 16 132 #define I2S_CGFR_I2SDIV_BIT_H 23 133 #define I2S_CGFR_I2SDIV_MASK GENMASK(I2S_CGFR_I2SDIV_BIT_H,\ 134 I2S_CGFR_I2SDIV_SHIFT) 135 #define I2S_CGFR_I2SDIV_SET(x) ((x) << I2S_CGFR_I2SDIV_SHIFT) 136 #define I2S_CGFR_I2SDIV_MAX ((1 << (I2S_CGFR_I2SDIV_BIT_H -\ 137 I2S_CGFR_I2SDIV_SHIFT)) - 1) 138 139 #define I2S_CGFR_ODD_SHIFT 24 140 #define I2S_CGFR_ODD BIT(I2S_CGFR_ODD_SHIFT) 141 #define I2S_CGFR_MCKOE BIT(25) 142 143 /* Registers below apply to I2S version 1.1 and more */ 144 145 /* Bit definition for SPI_HWCFGR register */ 146 #define I2S_HWCFGR_I2S_SUPPORT_MASK GENMASK(15, 12) 147 148 /* Bit definition for SPI_VERR register */ 149 #define I2S_VERR_MIN_MASK GENMASK(3, 0) 150 #define I2S_VERR_MAJ_MASK GENMASK(7, 4) 151 152 /* Bit definition for SPI_IPIDR register */ 153 #define I2S_IPIDR_ID_MASK GENMASK(31, 0) 154 155 /* Bit definition for SPI_SIDR register */ 156 #define I2S_SIDR_ID_MASK GENMASK(31, 0) 157 158 #define I2S_IPIDR_NUMBER 0x00130022 159 160 enum i2s_master_mode { 161 I2S_MS_NOT_SET, 162 I2S_MS_MASTER, 163 I2S_MS_SLAVE, 164 }; 165 166 enum i2s_mode { 167 I2S_I2SMOD_TX_SLAVE, 168 I2S_I2SMOD_RX_SLAVE, 169 I2S_I2SMOD_TX_MASTER, 170 I2S_I2SMOD_RX_MASTER, 171 I2S_I2SMOD_FD_SLAVE, 172 I2S_I2SMOD_FD_MASTER, 173 }; 174 175 enum i2s_fifo_th { 176 I2S_FIFO_TH_NONE, 177 I2S_FIFO_TH_ONE_QUARTER, 178 I2S_FIFO_TH_HALF, 179 I2S_FIFO_TH_THREE_QUARTER, 180 I2S_FIFO_TH_FULL, 181 }; 182 183 enum i2s_std { 184 I2S_STD_I2S, 185 I2S_STD_LEFT_J, 186 I2S_STD_RIGHT_J, 187 I2S_STD_DSP, 188 }; 189 190 enum i2s_datlen { 191 I2S_I2SMOD_DATLEN_16, 192 I2S_I2SMOD_DATLEN_24, 193 I2S_I2SMOD_DATLEN_32, 194 }; 195 196 #define STM32_I2S_FIFO_SIZE 16 197 198 #define STM32_I2S_IS_MASTER(x) ((x)->ms_flg == I2S_MS_MASTER) 199 #define STM32_I2S_IS_SLAVE(x) ((x)->ms_flg == I2S_MS_SLAVE) 200 201 #define STM32_I2S_NAME_LEN 32 202 #define STM32_I2S_RATE_11K 11025 203 204 /** 205 * struct stm32_i2s_data - private data of I2S 206 * @regmap_conf: I2S register map configuration pointer 207 * @regmap: I2S register map pointer 208 * @pdev: device data pointer 209 * @dai_drv: DAI driver pointer 210 * @dma_data_tx: dma configuration data for tx channel 211 * @dma_data_rx: dma configuration data for tx channel 212 * @substream: PCM substream data pointer 213 * @i2sclk: kernel clock feeding the I2S clock generator 214 * @i2smclk: master clock from I2S mclk provider 215 * @pclk: peripheral clock driving bus interface 216 * @x8kclk: I2S parent clock for sampling frequencies multiple of 8kHz 217 * @x11kclk: I2S parent clock for sampling frequencies multiple of 11kHz 218 * @base: mmio register base virtual address 219 * @phys_addr: I2S registers physical base address 220 * @lock_fd: lock to manage race conditions in full duplex mode 221 * @irq_lock: prevent race condition with IRQ 222 * @mclk_rate: master clock frequency (Hz) 223 * @fmt: DAI protocol 224 * @divider: prescaler division ratio 225 * @div: prescaler div field 226 * @odd: prescaler odd field 227 * @refcount: keep count of opened streams on I2S 228 * @ms_flg: master mode flag. 229 */ 230 struct stm32_i2s_data { 231 const struct regmap_config *regmap_conf; 232 struct regmap *regmap; 233 struct platform_device *pdev; 234 struct snd_soc_dai_driver *dai_drv; 235 struct snd_dmaengine_dai_dma_data dma_data_tx; 236 struct snd_dmaengine_dai_dma_data dma_data_rx; 237 struct snd_pcm_substream *substream; 238 struct clk *i2sclk; 239 struct clk *i2smclk; 240 struct clk *pclk; 241 struct clk *x8kclk; 242 struct clk *x11kclk; 243 void __iomem *base; 244 dma_addr_t phys_addr; 245 spinlock_t lock_fd; /* Manage race conditions for full duplex */ 246 spinlock_t irq_lock; /* used to prevent race condition with IRQ */ 247 unsigned int mclk_rate; 248 unsigned int fmt; 249 unsigned int divider; 250 unsigned int div; 251 bool odd; 252 int refcount; 253 int ms_flg; 254 }; 255 256 struct stm32_i2smclk_data { 257 struct clk_hw hw; 258 unsigned long freq; 259 struct stm32_i2s_data *i2s_data; 260 }; 261 262 #define to_mclk_data(_hw) container_of(_hw, struct stm32_i2smclk_data, hw) 263 264 static int stm32_i2s_calc_clk_div(struct stm32_i2s_data *i2s, 265 unsigned long input_rate, 266 unsigned long output_rate) 267 { 268 unsigned int ratio, div, divider = 1; 269 bool odd; 270 271 ratio = DIV_ROUND_CLOSEST(input_rate, output_rate); 272 273 /* Check the parity of the divider */ 274 odd = ratio & 0x1; 275 276 /* Compute the div prescaler */ 277 div = ratio >> 1; 278 279 /* If div is 0 actual divider is 1 */ 280 if (div) { 281 divider = ((2 * div) + odd); 282 dev_dbg(&i2s->pdev->dev, "Divider: 2*%d(div)+%d(odd) = %d\n", 283 div, odd, divider); 284 } 285 286 /* Division by three is not allowed by I2S prescaler */ 287 if ((div == 1 && odd) || div > I2S_CGFR_I2SDIV_MAX) { 288 dev_err(&i2s->pdev->dev, "Wrong divider setting\n"); 289 return -EINVAL; 290 } 291 292 if (input_rate % divider) 293 dev_dbg(&i2s->pdev->dev, 294 "Rate not accurate. requested (%ld), actual (%ld)\n", 295 output_rate, input_rate / divider); 296 297 i2s->div = div; 298 i2s->odd = odd; 299 i2s->divider = divider; 300 301 return 0; 302 } 303 304 static int stm32_i2s_set_clk_div(struct stm32_i2s_data *i2s) 305 { 306 u32 cgfr, cgfr_mask; 307 308 cgfr = I2S_CGFR_I2SDIV_SET(i2s->div) | (i2s->odd << I2S_CGFR_ODD_SHIFT); 309 cgfr_mask = I2S_CGFR_I2SDIV_MASK | I2S_CGFR_ODD; 310 311 return regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG, 312 cgfr_mask, cgfr); 313 } 314 315 static int stm32_i2s_set_parent_clock(struct stm32_i2s_data *i2s, 316 unsigned int rate) 317 { 318 struct platform_device *pdev = i2s->pdev; 319 struct clk *parent_clk; 320 int ret; 321 322 if (!(rate % STM32_I2S_RATE_11K)) 323 parent_clk = i2s->x11kclk; 324 else 325 parent_clk = i2s->x8kclk; 326 327 ret = clk_set_parent(i2s->i2sclk, parent_clk); 328 if (ret) 329 dev_err(&pdev->dev, 330 "Error %d setting i2sclk parent clock\n", ret); 331 332 return ret; 333 } 334 335 static long stm32_i2smclk_round_rate(struct clk_hw *hw, unsigned long rate, 336 unsigned long *prate) 337 { 338 struct stm32_i2smclk_data *mclk = to_mclk_data(hw); 339 struct stm32_i2s_data *i2s = mclk->i2s_data; 340 int ret; 341 342 ret = stm32_i2s_calc_clk_div(i2s, *prate, rate); 343 if (ret) 344 return ret; 345 346 mclk->freq = *prate / i2s->divider; 347 348 return mclk->freq; 349 } 350 351 static unsigned long stm32_i2smclk_recalc_rate(struct clk_hw *hw, 352 unsigned long parent_rate) 353 { 354 struct stm32_i2smclk_data *mclk = to_mclk_data(hw); 355 356 return mclk->freq; 357 } 358 359 static int stm32_i2smclk_set_rate(struct clk_hw *hw, unsigned long rate, 360 unsigned long parent_rate) 361 { 362 struct stm32_i2smclk_data *mclk = to_mclk_data(hw); 363 struct stm32_i2s_data *i2s = mclk->i2s_data; 364 int ret; 365 366 ret = stm32_i2s_calc_clk_div(i2s, parent_rate, rate); 367 if (ret) 368 return ret; 369 370 ret = stm32_i2s_set_clk_div(i2s); 371 if (ret) 372 return ret; 373 374 mclk->freq = rate; 375 376 return 0; 377 } 378 379 static int stm32_i2smclk_enable(struct clk_hw *hw) 380 { 381 struct stm32_i2smclk_data *mclk = to_mclk_data(hw); 382 struct stm32_i2s_data *i2s = mclk->i2s_data; 383 384 dev_dbg(&i2s->pdev->dev, "Enable master clock\n"); 385 386 return regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG, 387 I2S_CGFR_MCKOE, I2S_CGFR_MCKOE); 388 } 389 390 static void stm32_i2smclk_disable(struct clk_hw *hw) 391 { 392 struct stm32_i2smclk_data *mclk = to_mclk_data(hw); 393 struct stm32_i2s_data *i2s = mclk->i2s_data; 394 395 dev_dbg(&i2s->pdev->dev, "Disable master clock\n"); 396 397 regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG, I2S_CGFR_MCKOE, 0); 398 } 399 400 static const struct clk_ops mclk_ops = { 401 .enable = stm32_i2smclk_enable, 402 .disable = stm32_i2smclk_disable, 403 .recalc_rate = stm32_i2smclk_recalc_rate, 404 .round_rate = stm32_i2smclk_round_rate, 405 .set_rate = stm32_i2smclk_set_rate, 406 }; 407 408 static int stm32_i2s_add_mclk_provider(struct stm32_i2s_data *i2s) 409 { 410 struct clk_hw *hw; 411 struct stm32_i2smclk_data *mclk; 412 struct device *dev = &i2s->pdev->dev; 413 const char *pname = __clk_get_name(i2s->i2sclk); 414 char *mclk_name, *p, *s = (char *)pname; 415 int ret, i = 0; 416 417 mclk = devm_kzalloc(dev, sizeof(*mclk), GFP_KERNEL); 418 if (!mclk) 419 return -ENOMEM; 420 421 mclk_name = devm_kcalloc(dev, sizeof(char), 422 STM32_I2S_NAME_LEN, GFP_KERNEL); 423 if (!mclk_name) 424 return -ENOMEM; 425 426 /* 427 * Forge mclk clock name from parent clock name and suffix. 428 * String after "_" char is stripped in parent name. 429 */ 430 p = mclk_name; 431 while (*s && *s != '_' && (i < (STM32_I2S_NAME_LEN - 7))) { 432 *p++ = *s++; 433 i++; 434 } 435 strcat(p, "_mclk"); 436 437 mclk->hw.init = CLK_HW_INIT(mclk_name, pname, &mclk_ops, 0); 438 mclk->i2s_data = i2s; 439 hw = &mclk->hw; 440 441 dev_dbg(dev, "Register master clock %s\n", mclk_name); 442 ret = devm_clk_hw_register(&i2s->pdev->dev, hw); 443 if (ret) { 444 dev_err(dev, "mclk register fails with error %d\n", ret); 445 return ret; 446 } 447 i2s->i2smclk = hw->clk; 448 449 /* register mclk provider */ 450 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw); 451 } 452 453 static irqreturn_t stm32_i2s_isr(int irq, void *devid) 454 { 455 struct stm32_i2s_data *i2s = (struct stm32_i2s_data *)devid; 456 struct platform_device *pdev = i2s->pdev; 457 u32 sr, ier; 458 unsigned long flags; 459 int err = 0; 460 461 regmap_read(i2s->regmap, STM32_I2S_SR_REG, &sr); 462 regmap_read(i2s->regmap, STM32_I2S_IER_REG, &ier); 463 464 flags = sr & ier; 465 if (!flags) { 466 dev_dbg(&pdev->dev, "Spurious IRQ sr=0x%08x, ier=0x%08x\n", 467 sr, ier); 468 return IRQ_NONE; 469 } 470 471 regmap_write_bits(i2s->regmap, STM32_I2S_IFCR_REG, 472 I2S_IFCR_MASK, flags); 473 474 if (flags & I2S_SR_OVR) { 475 dev_dbg(&pdev->dev, "Overrun\n"); 476 err = 1; 477 } 478 479 if (flags & I2S_SR_UDR) { 480 dev_dbg(&pdev->dev, "Underrun\n"); 481 err = 1; 482 } 483 484 if (flags & I2S_SR_TIFRE) 485 dev_dbg(&pdev->dev, "Frame error\n"); 486 487 spin_lock(&i2s->irq_lock); 488 if (err && i2s->substream) 489 snd_pcm_stop_xrun(i2s->substream); 490 spin_unlock(&i2s->irq_lock); 491 492 return IRQ_HANDLED; 493 } 494 495 static bool stm32_i2s_readable_reg(struct device *dev, unsigned int reg) 496 { 497 switch (reg) { 498 case STM32_I2S_CR1_REG: 499 case STM32_I2S_CFG1_REG: 500 case STM32_I2S_CFG2_REG: 501 case STM32_I2S_IER_REG: 502 case STM32_I2S_SR_REG: 503 case STM32_I2S_RXDR_REG: 504 case STM32_I2S_CGFR_REG: 505 case STM32_I2S_HWCFGR_REG: 506 case STM32_I2S_VERR_REG: 507 case STM32_I2S_IPIDR_REG: 508 case STM32_I2S_SIDR_REG: 509 return true; 510 default: 511 return false; 512 } 513 } 514 515 static bool stm32_i2s_volatile_reg(struct device *dev, unsigned int reg) 516 { 517 switch (reg) { 518 case STM32_I2S_SR_REG: 519 case STM32_I2S_RXDR_REG: 520 return true; 521 default: 522 return false; 523 } 524 } 525 526 static bool stm32_i2s_writeable_reg(struct device *dev, unsigned int reg) 527 { 528 switch (reg) { 529 case STM32_I2S_CR1_REG: 530 case STM32_I2S_CFG1_REG: 531 case STM32_I2S_CFG2_REG: 532 case STM32_I2S_IER_REG: 533 case STM32_I2S_IFCR_REG: 534 case STM32_I2S_TXDR_REG: 535 case STM32_I2S_CGFR_REG: 536 return true; 537 default: 538 return false; 539 } 540 } 541 542 static int stm32_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) 543 { 544 struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai); 545 u32 cgfr; 546 u32 cgfr_mask = I2S_CGFR_I2SSTD_MASK | I2S_CGFR_CKPOL | 547 I2S_CGFR_WSINV | I2S_CGFR_I2SCFG_MASK; 548 549 dev_dbg(cpu_dai->dev, "fmt %x\n", fmt); 550 551 /* 552 * winv = 0 : default behavior (high/low) for all standards 553 * ckpol = 0 for all standards. 554 */ 555 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 556 case SND_SOC_DAIFMT_I2S: 557 cgfr = I2S_CGFR_I2SSTD_SET(I2S_STD_I2S); 558 break; 559 case SND_SOC_DAIFMT_MSB: 560 cgfr = I2S_CGFR_I2SSTD_SET(I2S_STD_LEFT_J); 561 break; 562 case SND_SOC_DAIFMT_LSB: 563 cgfr = I2S_CGFR_I2SSTD_SET(I2S_STD_RIGHT_J); 564 break; 565 case SND_SOC_DAIFMT_DSP_A: 566 cgfr = I2S_CGFR_I2SSTD_SET(I2S_STD_DSP); 567 break; 568 /* DSP_B not mapped on I2S PCM long format. 1 bit offset does not fit */ 569 default: 570 dev_err(cpu_dai->dev, "Unsupported protocol %#x\n", 571 fmt & SND_SOC_DAIFMT_FORMAT_MASK); 572 return -EINVAL; 573 } 574 575 /* DAI clock strobing */ 576 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 577 case SND_SOC_DAIFMT_NB_NF: 578 break; 579 case SND_SOC_DAIFMT_IB_NF: 580 cgfr |= I2S_CGFR_CKPOL; 581 break; 582 case SND_SOC_DAIFMT_NB_IF: 583 cgfr |= I2S_CGFR_WSINV; 584 break; 585 case SND_SOC_DAIFMT_IB_IF: 586 cgfr |= I2S_CGFR_CKPOL; 587 cgfr |= I2S_CGFR_WSINV; 588 break; 589 default: 590 dev_err(cpu_dai->dev, "Unsupported strobing %#x\n", 591 fmt & SND_SOC_DAIFMT_INV_MASK); 592 return -EINVAL; 593 } 594 595 /* DAI clock master masks */ 596 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 597 case SND_SOC_DAIFMT_BC_FC: 598 i2s->ms_flg = I2S_MS_SLAVE; 599 break; 600 case SND_SOC_DAIFMT_BP_FP: 601 i2s->ms_flg = I2S_MS_MASTER; 602 break; 603 default: 604 dev_err(cpu_dai->dev, "Unsupported mode %#x\n", 605 fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK); 606 return -EINVAL; 607 } 608 609 i2s->fmt = fmt; 610 return regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG, 611 cgfr_mask, cgfr); 612 } 613 614 static int stm32_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, 615 int clk_id, unsigned int freq, int dir) 616 { 617 struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai); 618 int ret = 0; 619 620 dev_dbg(cpu_dai->dev, "I2S MCLK frequency is %uHz. mode: %s, dir: %s\n", 621 freq, STM32_I2S_IS_MASTER(i2s) ? "master" : "slave", 622 dir ? "output" : "input"); 623 624 /* MCLK generation is available only in master mode */ 625 if (dir == SND_SOC_CLOCK_OUT && STM32_I2S_IS_MASTER(i2s)) { 626 if (!i2s->i2smclk) { 627 dev_dbg(cpu_dai->dev, "No MCLK registered\n"); 628 return 0; 629 } 630 631 /* Assume shutdown if requested frequency is 0Hz */ 632 if (!freq) { 633 /* Release mclk rate only if rate was actually set */ 634 if (i2s->mclk_rate) { 635 clk_rate_exclusive_put(i2s->i2smclk); 636 i2s->mclk_rate = 0; 637 } 638 return regmap_update_bits(i2s->regmap, 639 STM32_I2S_CGFR_REG, 640 I2S_CGFR_MCKOE, 0); 641 } 642 /* If master clock is used, set parent clock now */ 643 ret = stm32_i2s_set_parent_clock(i2s, freq); 644 if (ret) 645 return ret; 646 ret = clk_set_rate_exclusive(i2s->i2smclk, freq); 647 if (ret) { 648 dev_err(cpu_dai->dev, "Could not set mclk rate\n"); 649 return ret; 650 } 651 ret = regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG, 652 I2S_CGFR_MCKOE, I2S_CGFR_MCKOE); 653 if (!ret) 654 i2s->mclk_rate = freq; 655 } 656 657 return ret; 658 } 659 660 static int stm32_i2s_configure_clock(struct snd_soc_dai *cpu_dai, 661 struct snd_pcm_hw_params *params) 662 { 663 struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai); 664 unsigned long i2s_clock_rate; 665 unsigned int nb_bits, frame_len; 666 unsigned int rate = params_rate(params); 667 u32 cgfr; 668 int ret; 669 670 if (!(rate % 11025)) 671 clk_set_parent(i2s->i2sclk, i2s->x11kclk); 672 else 673 clk_set_parent(i2s->i2sclk, i2s->x8kclk); 674 i2s_clock_rate = clk_get_rate(i2s->i2sclk); 675 676 /* 677 * mckl = mclk_ratio x ws 678 * i2s mode : mclk_ratio = 256 679 * dsp mode : mclk_ratio = 128 680 * 681 * mclk on 682 * i2s mode : div = i2s_clk / (mclk_ratio * ws) 683 * dsp mode : div = i2s_clk / (mclk_ratio * ws) 684 * mclk off 685 * i2s mode : div = i2s_clk / (nb_bits x ws) 686 * dsp mode : div = i2s_clk / (nb_bits x ws) 687 */ 688 if (i2s->mclk_rate) { 689 ret = stm32_i2s_calc_clk_div(i2s, i2s_clock_rate, 690 i2s->mclk_rate); 691 if (ret) 692 return ret; 693 } else { 694 frame_len = 32; 695 if ((i2s->fmt & SND_SOC_DAIFMT_FORMAT_MASK) == 696 SND_SOC_DAIFMT_DSP_A) 697 frame_len = 16; 698 699 /* master clock not enabled */ 700 ret = regmap_read(i2s->regmap, STM32_I2S_CGFR_REG, &cgfr); 701 if (ret < 0) 702 return ret; 703 704 nb_bits = frame_len * (FIELD_GET(I2S_CGFR_CHLEN, cgfr) + 1); 705 ret = stm32_i2s_calc_clk_div(i2s, i2s_clock_rate, 706 (nb_bits * rate)); 707 if (ret) 708 return ret; 709 } 710 711 ret = stm32_i2s_set_clk_div(i2s); 712 if (ret < 0) 713 return ret; 714 715 /* Set bitclock and frameclock to their inactive state */ 716 return regmap_update_bits(i2s->regmap, STM32_I2S_CFG2_REG, 717 I2S_CFG2_AFCNTR, I2S_CFG2_AFCNTR); 718 } 719 720 static int stm32_i2s_configure(struct snd_soc_dai *cpu_dai, 721 struct snd_pcm_hw_params *params, 722 struct snd_pcm_substream *substream) 723 { 724 struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai); 725 int format = params_width(params); 726 u32 cfgr, cfgr_mask, cfg1; 727 unsigned int fthlv; 728 int ret; 729 730 switch (format) { 731 case 16: 732 cfgr = I2S_CGFR_DATLEN_SET(I2S_I2SMOD_DATLEN_16); 733 cfgr_mask = I2S_CGFR_DATLEN_MASK | I2S_CGFR_CHLEN; 734 break; 735 case 32: 736 cfgr = I2S_CGFR_DATLEN_SET(I2S_I2SMOD_DATLEN_32) | 737 I2S_CGFR_CHLEN; 738 cfgr_mask = I2S_CGFR_DATLEN_MASK | I2S_CGFR_CHLEN; 739 break; 740 default: 741 dev_err(cpu_dai->dev, "Unexpected format %d", format); 742 return -EINVAL; 743 } 744 745 if (STM32_I2S_IS_SLAVE(i2s)) { 746 cfgr |= I2S_CGFR_I2SCFG_SET(I2S_I2SMOD_FD_SLAVE); 747 748 /* As data length is either 16 or 32 bits, fixch always set */ 749 cfgr |= I2S_CGFR_FIXCH; 750 cfgr_mask |= I2S_CGFR_FIXCH; 751 } else { 752 cfgr |= I2S_CGFR_I2SCFG_SET(I2S_I2SMOD_FD_MASTER); 753 } 754 cfgr_mask |= I2S_CGFR_I2SCFG_MASK; 755 756 ret = regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG, 757 cfgr_mask, cfgr); 758 if (ret < 0) 759 return ret; 760 761 fthlv = STM32_I2S_FIFO_SIZE * I2S_FIFO_TH_ONE_QUARTER / 4; 762 cfg1 = I2S_CFG1_FTHVL_SET(fthlv - 1); 763 764 return regmap_update_bits(i2s->regmap, STM32_I2S_CFG1_REG, 765 I2S_CFG1_FTHVL_MASK, cfg1); 766 } 767 768 static int stm32_i2s_startup(struct snd_pcm_substream *substream, 769 struct snd_soc_dai *cpu_dai) 770 { 771 struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai); 772 unsigned long flags; 773 int ret; 774 775 spin_lock_irqsave(&i2s->irq_lock, flags); 776 i2s->substream = substream; 777 spin_unlock_irqrestore(&i2s->irq_lock, flags); 778 779 if ((i2s->fmt & SND_SOC_DAIFMT_FORMAT_MASK) != SND_SOC_DAIFMT_DSP_A) 780 snd_pcm_hw_constraint_single(substream->runtime, 781 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 782 783 ret = clk_prepare_enable(i2s->i2sclk); 784 if (ret < 0) { 785 dev_err(cpu_dai->dev, "Failed to enable clock: %d\n", ret); 786 return ret; 787 } 788 789 return regmap_write_bits(i2s->regmap, STM32_I2S_IFCR_REG, 790 I2S_IFCR_MASK, I2S_IFCR_MASK); 791 } 792 793 static int stm32_i2s_hw_params(struct snd_pcm_substream *substream, 794 struct snd_pcm_hw_params *params, 795 struct snd_soc_dai *cpu_dai) 796 { 797 struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai); 798 int ret; 799 800 ret = stm32_i2s_configure(cpu_dai, params, substream); 801 if (ret < 0) { 802 dev_err(cpu_dai->dev, "Configuration returned error %d\n", ret); 803 return ret; 804 } 805 806 if (STM32_I2S_IS_MASTER(i2s)) 807 ret = stm32_i2s_configure_clock(cpu_dai, params); 808 809 return ret; 810 } 811 812 static int stm32_i2s_trigger(struct snd_pcm_substream *substream, int cmd, 813 struct snd_soc_dai *cpu_dai) 814 { 815 struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai); 816 bool playback_flg = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); 817 u32 cfg1_mask, ier; 818 int ret; 819 820 switch (cmd) { 821 case SNDRV_PCM_TRIGGER_START: 822 case SNDRV_PCM_TRIGGER_RESUME: 823 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 824 /* Enable i2s */ 825 dev_dbg(cpu_dai->dev, "start I2S %s\n", 826 playback_flg ? "playback" : "capture"); 827 828 cfg1_mask = I2S_CFG1_RXDMAEN | I2S_CFG1_TXDMAEN; 829 regmap_update_bits(i2s->regmap, STM32_I2S_CFG1_REG, 830 cfg1_mask, cfg1_mask); 831 832 ret = regmap_update_bits(i2s->regmap, STM32_I2S_CR1_REG, 833 I2S_CR1_SPE, I2S_CR1_SPE); 834 if (ret < 0) { 835 dev_err(cpu_dai->dev, "Error %d enabling I2S\n", ret); 836 return ret; 837 } 838 839 ret = regmap_write_bits(i2s->regmap, STM32_I2S_CR1_REG, 840 I2S_CR1_CSTART, I2S_CR1_CSTART); 841 if (ret < 0) { 842 dev_err(cpu_dai->dev, "Error %d starting I2S\n", ret); 843 return ret; 844 } 845 846 regmap_write_bits(i2s->regmap, STM32_I2S_IFCR_REG, 847 I2S_IFCR_MASK, I2S_IFCR_MASK); 848 849 spin_lock(&i2s->lock_fd); 850 i2s->refcount++; 851 if (playback_flg) { 852 ier = I2S_IER_UDRIE; 853 } else { 854 ier = I2S_IER_OVRIE; 855 856 if (STM32_I2S_IS_MASTER(i2s) && i2s->refcount == 1) 857 /* dummy write to gate bus clocks */ 858 regmap_write(i2s->regmap, 859 STM32_I2S_TXDR_REG, 0); 860 } 861 spin_unlock(&i2s->lock_fd); 862 863 if (STM32_I2S_IS_SLAVE(i2s)) 864 ier |= I2S_IER_TIFREIE; 865 866 regmap_update_bits(i2s->regmap, STM32_I2S_IER_REG, ier, ier); 867 break; 868 case SNDRV_PCM_TRIGGER_STOP: 869 case SNDRV_PCM_TRIGGER_SUSPEND: 870 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 871 dev_dbg(cpu_dai->dev, "stop I2S %s\n", 872 playback_flg ? "playback" : "capture"); 873 874 if (playback_flg) 875 regmap_update_bits(i2s->regmap, STM32_I2S_IER_REG, 876 I2S_IER_UDRIE, 877 (unsigned int)~I2S_IER_UDRIE); 878 else 879 regmap_update_bits(i2s->regmap, STM32_I2S_IER_REG, 880 I2S_IER_OVRIE, 881 (unsigned int)~I2S_IER_OVRIE); 882 883 spin_lock(&i2s->lock_fd); 884 i2s->refcount--; 885 if (i2s->refcount) { 886 spin_unlock(&i2s->lock_fd); 887 break; 888 } 889 890 ret = regmap_update_bits(i2s->regmap, STM32_I2S_CR1_REG, 891 I2S_CR1_SPE, 0); 892 if (ret < 0) { 893 dev_err(cpu_dai->dev, "Error %d disabling I2S\n", ret); 894 spin_unlock(&i2s->lock_fd); 895 return ret; 896 } 897 spin_unlock(&i2s->lock_fd); 898 899 cfg1_mask = I2S_CFG1_RXDMAEN | I2S_CFG1_TXDMAEN; 900 regmap_update_bits(i2s->regmap, STM32_I2S_CFG1_REG, 901 cfg1_mask, 0); 902 break; 903 default: 904 return -EINVAL; 905 } 906 907 return 0; 908 } 909 910 static void stm32_i2s_shutdown(struct snd_pcm_substream *substream, 911 struct snd_soc_dai *cpu_dai) 912 { 913 struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai); 914 unsigned long flags; 915 916 clk_disable_unprepare(i2s->i2sclk); 917 918 spin_lock_irqsave(&i2s->irq_lock, flags); 919 i2s->substream = NULL; 920 spin_unlock_irqrestore(&i2s->irq_lock, flags); 921 } 922 923 static int stm32_i2s_dai_probe(struct snd_soc_dai *cpu_dai) 924 { 925 struct stm32_i2s_data *i2s = dev_get_drvdata(cpu_dai->dev); 926 struct snd_dmaengine_dai_dma_data *dma_data_tx = &i2s->dma_data_tx; 927 struct snd_dmaengine_dai_dma_data *dma_data_rx = &i2s->dma_data_rx; 928 929 /* Buswidth will be set by framework */ 930 dma_data_tx->addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED; 931 dma_data_tx->addr = (dma_addr_t)(i2s->phys_addr) + STM32_I2S_TXDR_REG; 932 dma_data_tx->maxburst = 1; 933 dma_data_rx->addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED; 934 dma_data_rx->addr = (dma_addr_t)(i2s->phys_addr) + STM32_I2S_RXDR_REG; 935 dma_data_rx->maxburst = 1; 936 937 snd_soc_dai_init_dma_data(cpu_dai, dma_data_tx, dma_data_rx); 938 939 return 0; 940 } 941 942 static const struct regmap_config stm32_h7_i2s_regmap_conf = { 943 .reg_bits = 32, 944 .reg_stride = 4, 945 .val_bits = 32, 946 .max_register = STM32_I2S_SIDR_REG, 947 .readable_reg = stm32_i2s_readable_reg, 948 .volatile_reg = stm32_i2s_volatile_reg, 949 .writeable_reg = stm32_i2s_writeable_reg, 950 .num_reg_defaults_raw = STM32_I2S_SIDR_REG / sizeof(u32) + 1, 951 .fast_io = true, 952 .cache_type = REGCACHE_FLAT, 953 }; 954 955 static const struct snd_soc_dai_ops stm32_i2s_pcm_dai_ops = { 956 .set_sysclk = stm32_i2s_set_sysclk, 957 .set_fmt = stm32_i2s_set_dai_fmt, 958 .startup = stm32_i2s_startup, 959 .hw_params = stm32_i2s_hw_params, 960 .trigger = stm32_i2s_trigger, 961 .shutdown = stm32_i2s_shutdown, 962 }; 963 964 static const struct snd_pcm_hardware stm32_i2s_pcm_hw = { 965 .info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP, 966 .buffer_bytes_max = 8 * PAGE_SIZE, 967 .period_bytes_min = 1024, 968 .period_bytes_max = 4 * PAGE_SIZE, 969 .periods_min = 2, 970 .periods_max = 8, 971 }; 972 973 static const struct snd_dmaengine_pcm_config stm32_i2s_pcm_config = { 974 .pcm_hardware = &stm32_i2s_pcm_hw, 975 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, 976 .prealloc_buffer_size = PAGE_SIZE * 8, 977 }; 978 979 static const struct snd_soc_component_driver stm32_i2s_component = { 980 .name = "stm32-i2s", 981 .legacy_dai_naming = 1, 982 }; 983 984 static void stm32_i2s_dai_init(struct snd_soc_pcm_stream *stream, 985 char *stream_name) 986 { 987 stream->stream_name = stream_name; 988 stream->channels_min = 1; 989 stream->channels_max = 2; 990 stream->rates = SNDRV_PCM_RATE_8000_192000; 991 stream->formats = SNDRV_PCM_FMTBIT_S16_LE | 992 SNDRV_PCM_FMTBIT_S32_LE; 993 } 994 995 static int stm32_i2s_dais_init(struct platform_device *pdev, 996 struct stm32_i2s_data *i2s) 997 { 998 struct snd_soc_dai_driver *dai_ptr; 999 1000 dai_ptr = devm_kzalloc(&pdev->dev, sizeof(struct snd_soc_dai_driver), 1001 GFP_KERNEL); 1002 if (!dai_ptr) 1003 return -ENOMEM; 1004 1005 dai_ptr->probe = stm32_i2s_dai_probe; 1006 dai_ptr->ops = &stm32_i2s_pcm_dai_ops; 1007 dai_ptr->id = 1; 1008 stm32_i2s_dai_init(&dai_ptr->playback, "playback"); 1009 stm32_i2s_dai_init(&dai_ptr->capture, "capture"); 1010 i2s->dai_drv = dai_ptr; 1011 1012 return 0; 1013 } 1014 1015 static const struct of_device_id stm32_i2s_ids[] = { 1016 { 1017 .compatible = "st,stm32h7-i2s", 1018 .data = &stm32_h7_i2s_regmap_conf 1019 }, 1020 {}, 1021 }; 1022 1023 static int stm32_i2s_parse_dt(struct platform_device *pdev, 1024 struct stm32_i2s_data *i2s) 1025 { 1026 struct device_node *np = pdev->dev.of_node; 1027 const struct of_device_id *of_id; 1028 struct reset_control *rst; 1029 struct resource *res; 1030 int irq, ret; 1031 1032 if (!np) 1033 return -ENODEV; 1034 1035 of_id = of_match_device(stm32_i2s_ids, &pdev->dev); 1036 if (of_id) 1037 i2s->regmap_conf = (const struct regmap_config *)of_id->data; 1038 else 1039 return -EINVAL; 1040 1041 i2s->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1042 if (IS_ERR(i2s->base)) 1043 return PTR_ERR(i2s->base); 1044 1045 i2s->phys_addr = res->start; 1046 1047 /* Get clocks */ 1048 i2s->pclk = devm_clk_get(&pdev->dev, "pclk"); 1049 if (IS_ERR(i2s->pclk)) 1050 return dev_err_probe(&pdev->dev, PTR_ERR(i2s->pclk), 1051 "Could not get pclk\n"); 1052 1053 i2s->i2sclk = devm_clk_get(&pdev->dev, "i2sclk"); 1054 if (IS_ERR(i2s->i2sclk)) 1055 return dev_err_probe(&pdev->dev, PTR_ERR(i2s->i2sclk), 1056 "Could not get i2sclk\n"); 1057 1058 i2s->x8kclk = devm_clk_get(&pdev->dev, "x8k"); 1059 if (IS_ERR(i2s->x8kclk)) 1060 return dev_err_probe(&pdev->dev, PTR_ERR(i2s->x8kclk), 1061 "Could not get x8k parent clock\n"); 1062 1063 i2s->x11kclk = devm_clk_get(&pdev->dev, "x11k"); 1064 if (IS_ERR(i2s->x11kclk)) 1065 return dev_err_probe(&pdev->dev, PTR_ERR(i2s->x11kclk), 1066 "Could not get x11k parent clock\n"); 1067 1068 /* Register mclk provider if requested */ 1069 if (of_property_present(np, "#clock-cells")) { 1070 ret = stm32_i2s_add_mclk_provider(i2s); 1071 if (ret < 0) 1072 return ret; 1073 } 1074 1075 /* Get irqs */ 1076 irq = platform_get_irq(pdev, 0); 1077 if (irq < 0) 1078 return irq; 1079 1080 ret = devm_request_irq(&pdev->dev, irq, stm32_i2s_isr, 0, 1081 dev_name(&pdev->dev), i2s); 1082 if (ret) { 1083 dev_err(&pdev->dev, "irq request returned %d\n", ret); 1084 return ret; 1085 } 1086 1087 /* Reset */ 1088 rst = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL); 1089 if (IS_ERR(rst)) 1090 return dev_err_probe(&pdev->dev, PTR_ERR(rst), 1091 "Reset controller error\n"); 1092 1093 reset_control_assert(rst); 1094 udelay(2); 1095 reset_control_deassert(rst); 1096 1097 return 0; 1098 } 1099 1100 static void stm32_i2s_remove(struct platform_device *pdev) 1101 { 1102 snd_dmaengine_pcm_unregister(&pdev->dev); 1103 snd_soc_unregister_component(&pdev->dev); 1104 pm_runtime_disable(&pdev->dev); 1105 } 1106 1107 static int stm32_i2s_probe(struct platform_device *pdev) 1108 { 1109 struct stm32_i2s_data *i2s; 1110 u32 val; 1111 int ret; 1112 1113 i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL); 1114 if (!i2s) 1115 return -ENOMEM; 1116 1117 i2s->pdev = pdev; 1118 i2s->ms_flg = I2S_MS_NOT_SET; 1119 spin_lock_init(&i2s->lock_fd); 1120 spin_lock_init(&i2s->irq_lock); 1121 platform_set_drvdata(pdev, i2s); 1122 1123 ret = stm32_i2s_parse_dt(pdev, i2s); 1124 if (ret) 1125 return ret; 1126 1127 ret = stm32_i2s_dais_init(pdev, i2s); 1128 if (ret) 1129 return ret; 1130 1131 i2s->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "pclk", 1132 i2s->base, i2s->regmap_conf); 1133 if (IS_ERR(i2s->regmap)) 1134 return dev_err_probe(&pdev->dev, PTR_ERR(i2s->regmap), 1135 "Regmap init error\n"); 1136 1137 ret = snd_dmaengine_pcm_register(&pdev->dev, &stm32_i2s_pcm_config, 0); 1138 if (ret) 1139 return dev_err_probe(&pdev->dev, ret, "PCM DMA register error\n"); 1140 1141 ret = snd_soc_register_component(&pdev->dev, &stm32_i2s_component, 1142 i2s->dai_drv, 1); 1143 if (ret) { 1144 snd_dmaengine_pcm_unregister(&pdev->dev); 1145 return ret; 1146 } 1147 1148 /* Set SPI/I2S in i2s mode */ 1149 ret = regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG, 1150 I2S_CGFR_I2SMOD, I2S_CGFR_I2SMOD); 1151 if (ret) 1152 goto error; 1153 1154 ret = regmap_read(i2s->regmap, STM32_I2S_IPIDR_REG, &val); 1155 if (ret) 1156 goto error; 1157 1158 if (val == I2S_IPIDR_NUMBER) { 1159 ret = regmap_read(i2s->regmap, STM32_I2S_HWCFGR_REG, &val); 1160 if (ret) 1161 goto error; 1162 1163 if (!FIELD_GET(I2S_HWCFGR_I2S_SUPPORT_MASK, val)) { 1164 dev_err(&pdev->dev, 1165 "Device does not support i2s mode\n"); 1166 ret = -EPERM; 1167 goto error; 1168 } 1169 1170 ret = regmap_read(i2s->regmap, STM32_I2S_VERR_REG, &val); 1171 if (ret) 1172 goto error; 1173 1174 dev_dbg(&pdev->dev, "I2S version: %lu.%lu registered\n", 1175 FIELD_GET(I2S_VERR_MAJ_MASK, val), 1176 FIELD_GET(I2S_VERR_MIN_MASK, val)); 1177 } 1178 1179 pm_runtime_enable(&pdev->dev); 1180 1181 return ret; 1182 1183 error: 1184 stm32_i2s_remove(pdev); 1185 1186 return ret; 1187 } 1188 1189 MODULE_DEVICE_TABLE(of, stm32_i2s_ids); 1190 1191 #ifdef CONFIG_PM_SLEEP 1192 static int stm32_i2s_suspend(struct device *dev) 1193 { 1194 struct stm32_i2s_data *i2s = dev_get_drvdata(dev); 1195 1196 regcache_cache_only(i2s->regmap, true); 1197 regcache_mark_dirty(i2s->regmap); 1198 1199 return 0; 1200 } 1201 1202 static int stm32_i2s_resume(struct device *dev) 1203 { 1204 struct stm32_i2s_data *i2s = dev_get_drvdata(dev); 1205 1206 regcache_cache_only(i2s->regmap, false); 1207 return regcache_sync(i2s->regmap); 1208 } 1209 #endif /* CONFIG_PM_SLEEP */ 1210 1211 static const struct dev_pm_ops stm32_i2s_pm_ops = { 1212 SET_SYSTEM_SLEEP_PM_OPS(stm32_i2s_suspend, stm32_i2s_resume) 1213 }; 1214 1215 static struct platform_driver stm32_i2s_driver = { 1216 .driver = { 1217 .name = "st,stm32-i2s", 1218 .of_match_table = stm32_i2s_ids, 1219 .pm = &stm32_i2s_pm_ops, 1220 }, 1221 .probe = stm32_i2s_probe, 1222 .remove_new = stm32_i2s_remove, 1223 }; 1224 1225 module_platform_driver(stm32_i2s_driver); 1226 1227 MODULE_DESCRIPTION("STM32 Soc i2s Interface"); 1228 MODULE_AUTHOR("Olivier Moysan, <olivier.moysan@st.com>"); 1229 MODULE_ALIAS("platform:stm32-i2s"); 1230 MODULE_LICENSE("GPL v2"); 1231