1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2 //
3 // Copyright(c) 2021 Mediatek Inc. All rights reserved.
4 //
5 // Author: YC Hung <yc.hung@mediatek.com>
6 //
7 
8 /*
9  * Hardware interface for audio DSP on mt8195
10  */
11 
12 #include <linux/delay.h>
13 #include <linux/firmware.h>
14 #include <linux/io.h>
15 #include <linux/of_address.h>
16 #include <linux/of_irq.h>
17 #include <linux/of_platform.h>
18 #include <linux/of_reserved_mem.h>
19 #include <linux/module.h>
20 
21 #include <sound/sof.h>
22 #include <sound/sof/xtensa.h>
23 #include "../../ops.h"
24 #include "../../sof-of-dev.h"
25 #include "../../sof-audio.h"
26 #include "../adsp_helper.h"
27 #include "../mtk-adsp-common.h"
28 #include "mt8195.h"
29 #include "mt8195-clk.h"
30 
31 static int mt8195_get_mailbox_offset(struct snd_sof_dev *sdev)
32 {
33 	return MBOX_OFFSET;
34 }
35 
36 static int mt8195_get_window_offset(struct snd_sof_dev *sdev, u32 id)
37 {
38 	return MBOX_OFFSET;
39 }
40 
41 static int mt8195_send_msg(struct snd_sof_dev *sdev,
42 			   struct snd_sof_ipc_msg *msg)
43 {
44 	struct adsp_priv *priv = sdev->pdata->hw_pdata;
45 
46 	sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data,
47 			  msg->msg_size);
48 
49 	return mtk_adsp_ipc_send(priv->dsp_ipc, MTK_ADSP_IPC_REQ, MTK_ADSP_IPC_OP_REQ);
50 }
51 
52 static void mt8195_get_reply(struct snd_sof_dev *sdev)
53 {
54 	struct snd_sof_ipc_msg *msg = sdev->msg;
55 	struct sof_ipc_reply reply;
56 	int ret = 0;
57 
58 	if (!msg) {
59 		dev_warn(sdev->dev, "unexpected ipc interrupt\n");
60 		return;
61 	}
62 
63 	/* get reply */
64 	sof_mailbox_read(sdev, sdev->host_box.offset, &reply, sizeof(reply));
65 	if (reply.error < 0) {
66 		memcpy(msg->reply_data, &reply, sizeof(reply));
67 		ret = reply.error;
68 	} else {
69 		/* reply has correct size? */
70 		if (reply.hdr.size != msg->reply_size) {
71 			dev_err(sdev->dev, "error: reply expected %zu got %u bytes\n",
72 				msg->reply_size, reply.hdr.size);
73 			ret = -EINVAL;
74 		}
75 
76 		/* read the message */
77 		if (msg->reply_size > 0)
78 			sof_mailbox_read(sdev, sdev->host_box.offset,
79 					 msg->reply_data, msg->reply_size);
80 	}
81 
82 	msg->reply_error = ret;
83 }
84 
85 static void mt8195_dsp_handle_reply(struct mtk_adsp_ipc *ipc)
86 {
87 	struct adsp_priv *priv = mtk_adsp_ipc_get_data(ipc);
88 	unsigned long flags;
89 
90 	spin_lock_irqsave(&priv->sdev->ipc_lock, flags);
91 	mt8195_get_reply(priv->sdev);
92 	snd_sof_ipc_reply(priv->sdev, 0);
93 	spin_unlock_irqrestore(&priv->sdev->ipc_lock, flags);
94 }
95 
96 static void mt8195_dsp_handle_request(struct mtk_adsp_ipc *ipc)
97 {
98 	struct adsp_priv *priv = mtk_adsp_ipc_get_data(ipc);
99 	u32 p; /* panic code */
100 	int ret;
101 
102 	/* Read the message from the debug box. */
103 	sof_mailbox_read(priv->sdev, priv->sdev->debug_box.offset + 4,
104 			 &p, sizeof(p));
105 
106 	/* Check to see if the message is a panic code 0x0dead*** */
107 	if ((p & SOF_IPC_PANIC_MAGIC_MASK) == SOF_IPC_PANIC_MAGIC) {
108 		snd_sof_dsp_panic(priv->sdev, p, true);
109 	} else {
110 		snd_sof_ipc_msgs_rx(priv->sdev);
111 
112 		/* tell DSP cmd is done */
113 		ret = mtk_adsp_ipc_send(priv->dsp_ipc, MTK_ADSP_IPC_RSP, MTK_ADSP_IPC_OP_RSP);
114 		if (ret)
115 			dev_err(priv->dev, "request send ipc failed");
116 	}
117 }
118 
119 static struct mtk_adsp_ipc_ops dsp_ops = {
120 	.handle_reply		= mt8195_dsp_handle_reply,
121 	.handle_request		= mt8195_dsp_handle_request,
122 };
123 
124 static int platform_parse_resource(struct platform_device *pdev, void *data)
125 {
126 	struct resource *mmio;
127 	struct resource res;
128 	struct device_node *mem_region;
129 	struct device *dev = &pdev->dev;
130 	struct mtk_adsp_chip_info *adsp = data;
131 	int ret;
132 
133 	mem_region = of_parse_phandle(dev->of_node, "memory-region", 0);
134 	if (!mem_region) {
135 		dev_err(dev, "no dma memory-region phandle\n");
136 		return -ENODEV;
137 	}
138 
139 	ret = of_address_to_resource(mem_region, 0, &res);
140 	of_node_put(mem_region);
141 	if (ret) {
142 		dev_err(dev, "of_address_to_resource dma failed\n");
143 		return ret;
144 	}
145 
146 	dev_dbg(dev, "DMA %pR\n", &res);
147 
148 	adsp->pa_shared_dram = (phys_addr_t)res.start;
149 	adsp->shared_size = resource_size(&res);
150 	if (adsp->pa_shared_dram & DRAM_REMAP_MASK) {
151 		dev_err(dev, "adsp shared dma memory(%#x) is not 4K-aligned\n",
152 			(u32)adsp->pa_shared_dram);
153 		return -EINVAL;
154 	}
155 
156 	ret = of_reserved_mem_device_init(dev);
157 	if (ret) {
158 		dev_err(dev, "of_reserved_mem_device_init failed\n");
159 		return ret;
160 	}
161 
162 	mem_region = of_parse_phandle(dev->of_node, "memory-region", 1);
163 	if (!mem_region) {
164 		dev_err(dev, "no memory-region sysmem phandle\n");
165 		return -ENODEV;
166 	}
167 
168 	ret = of_address_to_resource(mem_region, 0, &res);
169 	of_node_put(mem_region);
170 	if (ret) {
171 		dev_err(dev, "of_address_to_resource sysmem failed\n");
172 		return ret;
173 	}
174 
175 	adsp->pa_dram = (phys_addr_t)res.start;
176 	adsp->dramsize = resource_size(&res);
177 	if (adsp->pa_dram & DRAM_REMAP_MASK) {
178 		dev_err(dev, "adsp memory(%#x) is not 4K-aligned\n",
179 			(u32)adsp->pa_dram);
180 		return -EINVAL;
181 	}
182 
183 	if (adsp->dramsize < TOTAL_SIZE_SHARED_DRAM_FROM_TAIL) {
184 		dev_err(dev, "adsp memory(%#x) is not enough for share\n",
185 			adsp->dramsize);
186 		return -EINVAL;
187 	}
188 
189 	dev_dbg(dev, "dram pbase=%pa, dramsize=%#x\n",
190 		&adsp->pa_dram, adsp->dramsize);
191 
192 	/* Parse CFG base */
193 	mmio = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
194 	if (!mmio) {
195 		dev_err(dev, "no ADSP-CFG register resource\n");
196 		return -ENXIO;
197 	}
198 	/* remap for DSP register accessing */
199 	adsp->va_cfgreg = devm_ioremap_resource(dev, mmio);
200 	if (IS_ERR(adsp->va_cfgreg))
201 		return PTR_ERR(adsp->va_cfgreg);
202 
203 	adsp->pa_cfgreg = (phys_addr_t)mmio->start;
204 	adsp->cfgregsize = resource_size(mmio);
205 
206 	dev_dbg(dev, "cfgreg-vbase=%p, cfgregsize=%#x\n",
207 		adsp->va_cfgreg, adsp->cfgregsize);
208 
209 	/* Parse SRAM */
210 	mmio = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sram");
211 	if (!mmio) {
212 		dev_err(dev, "no SRAM resource\n");
213 		return -ENXIO;
214 	}
215 
216 	adsp->pa_sram = (phys_addr_t)mmio->start;
217 	adsp->sramsize = resource_size(mmio);
218 	if (adsp->sramsize < TOTAL_SIZE_SHARED_SRAM_FROM_TAIL) {
219 		dev_err(dev, "adsp SRAM(%#x) is not enough for share\n",
220 			adsp->sramsize);
221 		return -EINVAL;
222 	}
223 
224 	dev_dbg(dev, "sram pbase=%pa,%#x\n", &adsp->pa_sram, adsp->sramsize);
225 
226 	return ret;
227 }
228 
229 static int adsp_sram_power_on(struct device *dev, bool on)
230 {
231 	void __iomem *va_dspsysreg;
232 	u32 srampool_con;
233 
234 	va_dspsysreg = ioremap(ADSP_SRAM_POOL_CON, 0x4);
235 	if (!va_dspsysreg) {
236 		dev_err(dev, "failed to ioremap sram pool base %#x\n",
237 			ADSP_SRAM_POOL_CON);
238 		return -ENOMEM;
239 	}
240 
241 	srampool_con = readl(va_dspsysreg);
242 	if (on)
243 		writel(srampool_con & ~DSP_SRAM_POOL_PD_MASK, va_dspsysreg);
244 	else
245 		writel(srampool_con | DSP_SRAM_POOL_PD_MASK, va_dspsysreg);
246 
247 	iounmap(va_dspsysreg);
248 	return 0;
249 }
250 
251 /*  Init the basic DSP DRAM address */
252 static int adsp_memory_remap_init(struct device *dev, struct mtk_adsp_chip_info *adsp)
253 {
254 	void __iomem *vaddr_emi_map;
255 	int offset;
256 
257 	if (!adsp)
258 		return -ENXIO;
259 
260 	vaddr_emi_map = devm_ioremap(dev, DSP_EMI_MAP_ADDR, 0x4);
261 	if (!vaddr_emi_map) {
262 		dev_err(dev, "failed to ioremap emi map base %#x\n",
263 			DSP_EMI_MAP_ADDR);
264 		return -ENOMEM;
265 	}
266 
267 	offset = adsp->pa_dram - DRAM_PHYS_BASE_FROM_DSP_VIEW;
268 	adsp->dram_offset = offset;
269 	offset >>= DRAM_REMAP_SHIFT;
270 	dev_dbg(dev, "adsp->pa_dram %pa, offset %#x\n", &adsp->pa_dram, offset);
271 	writel(offset, vaddr_emi_map);
272 	if (offset != readl(vaddr_emi_map)) {
273 		dev_err(dev, "write emi map fail : %#x\n", readl(vaddr_emi_map));
274 		return -EIO;
275 	}
276 
277 	return 0;
278 }
279 
280 static int adsp_shared_base_ioremap(struct platform_device *pdev, void *data)
281 {
282 	struct device *dev = &pdev->dev;
283 	struct mtk_adsp_chip_info *adsp = data;
284 
285 	/* remap shared-dram base to be non-cachable */
286 	adsp->shared_dram = devm_ioremap(dev, adsp->pa_shared_dram,
287 					 adsp->shared_size);
288 	if (!adsp->shared_dram) {
289 		dev_err(dev, "failed to ioremap base %pa size %#x\n",
290 			adsp->shared_dram, adsp->shared_size);
291 		return -ENOMEM;
292 	}
293 
294 	dev_dbg(dev, "shared-dram vbase=%p, phy addr :%pa,  size=%#x\n",
295 		adsp->shared_dram, &adsp->pa_shared_dram, adsp->shared_size);
296 
297 	return 0;
298 }
299 
300 static int mt8195_run(struct snd_sof_dev *sdev)
301 {
302 	u32 adsp_bootup_addr;
303 
304 	adsp_bootup_addr = SRAM_PHYS_BASE_FROM_DSP_VIEW;
305 	dev_dbg(sdev->dev, "HIFIxDSP boot from base : 0x%08X\n", adsp_bootup_addr);
306 	sof_hifixdsp_boot_sequence(sdev, adsp_bootup_addr);
307 
308 	return 0;
309 }
310 
311 static int mt8195_dsp_probe(struct snd_sof_dev *sdev)
312 {
313 	struct platform_device *pdev = container_of(sdev->dev, struct platform_device, dev);
314 	struct adsp_priv *priv;
315 	int ret;
316 
317 	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
318 	if (!priv)
319 		return -ENOMEM;
320 
321 	sdev->pdata->hw_pdata = priv;
322 	priv->dev = sdev->dev;
323 	priv->sdev = sdev;
324 
325 	priv->adsp = devm_kzalloc(&pdev->dev, sizeof(struct mtk_adsp_chip_info), GFP_KERNEL);
326 	if (!priv->adsp)
327 		return -ENOMEM;
328 
329 	ret = platform_parse_resource(pdev, priv->adsp);
330 	if (ret)
331 		return ret;
332 
333 	ret = mt8195_adsp_init_clock(sdev);
334 	if (ret) {
335 		dev_err(sdev->dev, "mt8195_adsp_init_clock failed\n");
336 		return -EINVAL;
337 	}
338 
339 	ret = adsp_clock_on(sdev);
340 	if (ret) {
341 		dev_err(sdev->dev, "adsp_clock_on fail!\n");
342 		return -EINVAL;
343 	}
344 
345 	ret = adsp_sram_power_on(sdev->dev, true);
346 	if (ret) {
347 		dev_err(sdev->dev, "adsp_sram_power_on fail!\n");
348 		goto exit_clk_disable;
349 	}
350 
351 	ret = adsp_memory_remap_init(&pdev->dev, priv->adsp);
352 	if (ret) {
353 		dev_err(sdev->dev, "adsp_memory_remap_init fail!\n");
354 		goto err_adsp_sram_power_off;
355 	}
356 
357 	sdev->bar[SOF_FW_BLK_TYPE_IRAM] = devm_ioremap(sdev->dev,
358 						       priv->adsp->pa_sram,
359 						       priv->adsp->sramsize);
360 	if (!sdev->bar[SOF_FW_BLK_TYPE_IRAM]) {
361 		dev_err(sdev->dev, "failed to ioremap base %pa size %#x\n",
362 			&priv->adsp->pa_sram, priv->adsp->sramsize);
363 		ret = -EINVAL;
364 		goto err_adsp_sram_power_off;
365 	}
366 
367 	priv->adsp->va_sram = sdev->bar[SOF_FW_BLK_TYPE_IRAM];
368 
369 	sdev->bar[SOF_FW_BLK_TYPE_SRAM] = devm_ioremap(sdev->dev,
370 						       priv->adsp->pa_dram,
371 						       priv->adsp->dramsize);
372 	if (!sdev->bar[SOF_FW_BLK_TYPE_SRAM]) {
373 		dev_err(sdev->dev, "failed to ioremap base %pa size %#x\n",
374 			&priv->adsp->pa_dram, priv->adsp->dramsize);
375 		ret = -EINVAL;
376 		goto err_adsp_sram_power_off;
377 	}
378 	priv->adsp->va_dram = sdev->bar[SOF_FW_BLK_TYPE_SRAM];
379 
380 	ret = adsp_shared_base_ioremap(pdev, priv->adsp);
381 	if (ret) {
382 		dev_err(sdev->dev, "adsp_shared_base_ioremap fail!\n");
383 		goto err_adsp_sram_power_off;
384 	}
385 
386 	sdev->bar[DSP_REG_BAR] = priv->adsp->va_cfgreg;
387 
388 	sdev->mmio_bar = SOF_FW_BLK_TYPE_SRAM;
389 	sdev->mailbox_bar = SOF_FW_BLK_TYPE_SRAM;
390 
391 	/* set default mailbox offset for FW ready message */
392 	sdev->dsp_box.offset = mt8195_get_mailbox_offset(sdev);
393 
394 	priv->ipc_dev = platform_device_register_data(&pdev->dev, "mtk-adsp-ipc",
395 						      PLATFORM_DEVID_NONE,
396 						      pdev, sizeof(*pdev));
397 	if (IS_ERR(priv->ipc_dev)) {
398 		ret = PTR_ERR(priv->ipc_dev);
399 		dev_err(sdev->dev, "failed to register mtk-adsp-ipc device\n");
400 		goto err_adsp_sram_power_off;
401 	}
402 
403 	priv->dsp_ipc = dev_get_drvdata(&priv->ipc_dev->dev);
404 	if (!priv->dsp_ipc) {
405 		ret = -EPROBE_DEFER;
406 		dev_err(sdev->dev, "failed to get drvdata\n");
407 		goto exit_pdev_unregister;
408 	}
409 
410 	mtk_adsp_ipc_set_data(priv->dsp_ipc, priv);
411 	priv->dsp_ipc->ops = &dsp_ops;
412 
413 	return 0;
414 
415 exit_pdev_unregister:
416 	platform_device_unregister(priv->ipc_dev);
417 err_adsp_sram_power_off:
418 	adsp_sram_power_on(&pdev->dev, false);
419 exit_clk_disable:
420 	adsp_clock_off(sdev);
421 
422 	return ret;
423 }
424 
425 static int mt8195_dsp_shutdown(struct snd_sof_dev *sdev)
426 {
427 	return snd_sof_suspend(sdev->dev);
428 }
429 
430 static int mt8195_dsp_remove(struct snd_sof_dev *sdev)
431 {
432 	struct platform_device *pdev = container_of(sdev->dev, struct platform_device, dev);
433 	struct adsp_priv *priv = sdev->pdata->hw_pdata;
434 
435 	platform_device_unregister(priv->ipc_dev);
436 	adsp_sram_power_on(&pdev->dev, false);
437 	adsp_clock_off(sdev);
438 
439 	return 0;
440 }
441 
442 static int mt8195_dsp_suspend(struct snd_sof_dev *sdev, u32 target_state)
443 {
444 	struct platform_device *pdev = container_of(sdev->dev, struct platform_device, dev);
445 	int ret;
446 	u32 reset_sw, dbg_pc;
447 
448 	/* wait dsp enter idle, timeout is 1 second */
449 	ret = snd_sof_dsp_read_poll_timeout(sdev, DSP_REG_BAR,
450 					    DSP_RESET_SW, reset_sw,
451 					    ((reset_sw & ADSP_PWAIT) == ADSP_PWAIT),
452 					    SUSPEND_DSP_IDLE_POLL_INTERVAL_US,
453 					    SUSPEND_DSP_IDLE_TIMEOUT_US);
454 	if (ret < 0) {
455 		dbg_pc = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGPC);
456 		dev_warn(sdev->dev, "dsp not idle, powering off anyway : swrest %#x, pc %#x, ret %d\n",
457 			 reset_sw, dbg_pc, ret);
458 	}
459 
460 	/* stall and reset dsp */
461 	sof_hifixdsp_shutdown(sdev);
462 
463 	/* power down adsp sram */
464 	ret = adsp_sram_power_on(&pdev->dev, false);
465 	if (ret) {
466 		dev_err(sdev->dev, "adsp_sram_power_off fail!\n");
467 		return ret;
468 	}
469 
470 	/* turn off adsp clock */
471 	return adsp_clock_off(sdev);
472 }
473 
474 static int mt8195_dsp_resume(struct snd_sof_dev *sdev)
475 {
476 	int ret;
477 
478 	/* turn on adsp clock */
479 	ret = adsp_clock_on(sdev);
480 	if (ret) {
481 		dev_err(sdev->dev, "adsp_clock_on fail!\n");
482 		return ret;
483 	}
484 
485 	/* power on adsp sram */
486 	ret = adsp_sram_power_on(sdev->dev, true);
487 	if (ret)
488 		dev_err(sdev->dev, "adsp_sram_power_on fail!\n");
489 
490 	return ret;
491 }
492 
493 /* on mt8195 there is 1 to 1 match between type and BAR idx */
494 static int mt8195_get_bar_index(struct snd_sof_dev *sdev, u32 type)
495 {
496 	return type;
497 }
498 
499 static int mt8195_ipc_msg_data(struct snd_sof_dev *sdev,
500 			       struct snd_pcm_substream *substream,
501 			       void *p, size_t sz)
502 {
503 	sof_mailbox_read(sdev, sdev->dsp_box.offset, p, sz);
504 	return 0;
505 }
506 
507 static void mt8195_adsp_dump(struct snd_sof_dev *sdev, u32 flags)
508 {
509 	u32 dbg_pc, dbg_data, dbg_bus0, dbg_bus1, dbg_inst;
510 	u32 dbg_ls0stat, dbg_ls1stat, faultbus, faultinfo, swrest;
511 
512 	/* dump debug registers */
513 	dbg_pc = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGPC);
514 	dbg_data = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGDATA);
515 	dbg_bus0 = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGBUS0);
516 	dbg_bus1 = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGBUS1);
517 	dbg_inst = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGINST);
518 	dbg_ls0stat = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGLS0STAT);
519 	dbg_ls1stat = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGLS1STAT);
520 	faultbus = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PFAULTBUS);
521 	faultinfo = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PFAULTINFO);
522 	swrest = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_RESET_SW);
523 
524 	dev_info(sdev->dev, "adsp dump : pc %#x, data %#x, bus0 %#x, bus1 %#x, swrest %#x",
525 		 dbg_pc, dbg_data, dbg_bus0, dbg_bus1, swrest);
526 	dev_info(sdev->dev, "dbg_inst %#x, ls0stat %#x, ls1stat %#x, faultbus %#x, faultinfo %#x",
527 		 dbg_inst, dbg_ls0stat, dbg_ls1stat, faultbus, faultinfo);
528 
529 	mtk_adsp_dump(sdev, flags);
530 }
531 
532 static struct snd_soc_dai_driver mt8195_dai[] = {
533 {
534 	.name = "SOF_DL2",
535 	.playback = {
536 		.channels_min = 1,
537 		.channels_max = 2,
538 	},
539 },
540 {
541 	.name = "SOF_DL3",
542 	.playback = {
543 		.channels_min = 1,
544 		.channels_max = 2,
545 	},
546 },
547 {
548 	.name = "SOF_UL4",
549 	.capture = {
550 		.channels_min = 1,
551 		.channels_max = 2,
552 	},
553 },
554 {
555 	.name = "SOF_UL5",
556 	.capture = {
557 		.channels_min = 1,
558 		.channels_max = 2,
559 	},
560 },
561 };
562 
563 /* mt8195 ops */
564 static struct snd_sof_dsp_ops sof_mt8195_ops = {
565 	/* probe and remove */
566 	.probe		= mt8195_dsp_probe,
567 	.remove		= mt8195_dsp_remove,
568 	.shutdown	= mt8195_dsp_shutdown,
569 
570 	/* DSP core boot */
571 	.run		= mt8195_run,
572 
573 	/* Block IO */
574 	.block_read	= sof_block_read,
575 	.block_write	= sof_block_write,
576 
577 	/* Register IO */
578 	.write		= sof_io_write,
579 	.read		= sof_io_read,
580 	.write64	= sof_io_write64,
581 	.read64		= sof_io_read64,
582 
583 	/* ipc */
584 	.send_msg		= mt8195_send_msg,
585 	.get_mailbox_offset	= mt8195_get_mailbox_offset,
586 	.get_window_offset	= mt8195_get_window_offset,
587 	.ipc_msg_data		= mt8195_ipc_msg_data,
588 	.set_stream_data_offset = sof_set_stream_data_offset,
589 
590 	/* misc */
591 	.get_bar_index	= mt8195_get_bar_index,
592 
593 	/* firmware loading */
594 	.load_firmware	= snd_sof_load_firmware_memcpy,
595 
596 	/* Firmware ops */
597 	.dsp_arch_ops = &sof_xtensa_arch_ops,
598 
599 	/* Debug information */
600 	.dbg_dump = mt8195_adsp_dump,
601 
602 	/* DAI drivers */
603 	.drv = mt8195_dai,
604 	.num_drv = ARRAY_SIZE(mt8195_dai),
605 
606 	/* PM */
607 	.suspend	= mt8195_dsp_suspend,
608 	.resume		= mt8195_dsp_resume,
609 
610 	/* ALSA HW info flags */
611 	.hw_info =	SNDRV_PCM_INFO_MMAP |
612 			SNDRV_PCM_INFO_MMAP_VALID |
613 			SNDRV_PCM_INFO_INTERLEAVED |
614 			SNDRV_PCM_INFO_PAUSE |
615 			SNDRV_PCM_INFO_NO_PERIOD_WAKEUP,
616 };
617 
618 static const struct sof_dev_desc sof_of_mt8195_desc = {
619 	.ipc_supported_mask	= BIT(SOF_IPC),
620 	.ipc_default		= SOF_IPC,
621 	.default_fw_path = {
622 		[SOF_IPC] = "mediatek/sof",
623 	},
624 	.default_tplg_path = {
625 		[SOF_IPC] = "mediatek/sof-tplg",
626 	},
627 	.default_fw_filename = {
628 		[SOF_IPC] = "sof-mt8195.ri",
629 	},
630 	.nocodec_tplg_filename = "sof-mt8195-nocodec.tplg",
631 	.ops = &sof_mt8195_ops,
632 	.ipc_timeout = 1000,
633 };
634 
635 static const struct of_device_id sof_of_mt8195_ids[] = {
636 	{ .compatible = "mediatek,mt8195-dsp", .data = &sof_of_mt8195_desc},
637 	{ }
638 };
639 MODULE_DEVICE_TABLE(of, sof_of_mt8195_ids);
640 
641 /* DT driver definition */
642 static struct platform_driver snd_sof_of_mt8195_driver = {
643 	.probe = sof_of_probe,
644 	.remove = sof_of_remove,
645 	.shutdown = sof_of_shutdown,
646 	.driver = {
647 	.name = "sof-audio-of-mt8195",
648 		.pm = &sof_of_pm,
649 		.of_match_table = sof_of_mt8195_ids,
650 	},
651 };
652 module_platform_driver(snd_sof_of_mt8195_driver);
653 
654 MODULE_IMPORT_NS(SND_SOC_SOF_XTENSA);
655 MODULE_LICENSE("Dual BSD/GPL");
656