1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 // 3 // Copyright(c) 2021 Mediatek Inc. All rights reserved. 4 // 5 // Author: YC Hung <yc.hung@mediatek.com> 6 // 7 8 /* 9 * Hardware interface for audio DSP on mt8195 10 */ 11 12 #include <linux/delay.h> 13 #include <linux/firmware.h> 14 #include <linux/io.h> 15 #include <linux/of_address.h> 16 #include <linux/of_irq.h> 17 #include <linux/of_platform.h> 18 #include <linux/of_reserved_mem.h> 19 #include <linux/module.h> 20 21 #include <sound/sof.h> 22 #include <sound/sof/xtensa.h> 23 #include "../../ops.h" 24 #include "../../sof-of-dev.h" 25 #include "../../sof-audio.h" 26 #include "../adsp_helper.h" 27 #include "mt8195.h" 28 #include "mt8195-clk.h" 29 30 static int platform_parse_resource(struct platform_device *pdev, void *data) 31 { 32 struct resource *mmio; 33 struct resource res; 34 struct device_node *mem_region; 35 struct device *dev = &pdev->dev; 36 struct mtk_adsp_chip_info *adsp = data; 37 int ret; 38 39 mem_region = of_parse_phandle(dev->of_node, "memory-region", 0); 40 if (!mem_region) { 41 dev_err(dev, "no dma memory-region phandle\n"); 42 return -ENODEV; 43 } 44 45 ret = of_address_to_resource(mem_region, 0, &res); 46 of_node_put(mem_region); 47 if (ret) { 48 dev_err(dev, "of_address_to_resource dma failed\n"); 49 return ret; 50 } 51 52 dev_dbg(dev, "DMA %pR\n", &res); 53 54 ret = of_reserved_mem_device_init(dev); 55 if (ret) { 56 dev_err(dev, "of_reserved_mem_device_init failed\n"); 57 return ret; 58 } 59 60 mem_region = of_parse_phandle(dev->of_node, "memory-region", 1); 61 if (!mem_region) { 62 dev_err(dev, "no memory-region sysmem phandle\n"); 63 return -ENODEV; 64 } 65 66 ret = of_address_to_resource(mem_region, 0, &res); 67 of_node_put(mem_region); 68 if (ret) { 69 dev_err(dev, "of_address_to_resource sysmem failed\n"); 70 return ret; 71 } 72 73 adsp->pa_dram = (phys_addr_t)res.start; 74 adsp->dramsize = resource_size(&res); 75 if (adsp->pa_dram & DRAM_REMAP_MASK) { 76 dev_err(dev, "adsp memory(%#x) is not 4K-aligned\n", 77 (u32)adsp->pa_dram); 78 return -EINVAL; 79 } 80 81 if (adsp->dramsize < TOTAL_SIZE_SHARED_DRAM_FROM_TAIL) { 82 dev_err(dev, "adsp memory(%#x) is not enough for share\n", 83 adsp->dramsize); 84 return -EINVAL; 85 } 86 87 dev_dbg(dev, "dram pbase=%pa, dramsize=%#x\n", 88 &adsp->pa_dram, adsp->dramsize); 89 90 /* Parse CFG base */ 91 mmio = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg"); 92 if (!mmio) { 93 dev_err(dev, "no ADSP-CFG register resource\n"); 94 return -ENXIO; 95 } 96 /* remap for DSP register accessing */ 97 adsp->va_cfgreg = devm_ioremap_resource(dev, mmio); 98 if (IS_ERR(adsp->va_cfgreg)) 99 return PTR_ERR(adsp->va_cfgreg); 100 101 adsp->pa_cfgreg = (phys_addr_t)mmio->start; 102 adsp->cfgregsize = resource_size(mmio); 103 104 dev_dbg(dev, "cfgreg-vbase=%p, cfgregsize=%#x\n", 105 adsp->va_cfgreg, adsp->cfgregsize); 106 107 /* Parse SRAM */ 108 mmio = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sram"); 109 if (!mmio) { 110 dev_err(dev, "no SRAM resource\n"); 111 return -ENXIO; 112 } 113 114 adsp->pa_sram = (phys_addr_t)mmio->start; 115 adsp->sramsize = resource_size(mmio); 116 if (adsp->sramsize < TOTAL_SIZE_SHARED_SRAM_FROM_TAIL) { 117 dev_err(dev, "adsp SRAM(%#x) is not enough for share\n", 118 adsp->sramsize); 119 return -EINVAL; 120 } 121 122 dev_dbg(dev, "sram pbase=%pa,%#x\n", &adsp->pa_sram, adsp->sramsize); 123 124 return ret; 125 } 126 127 static int adsp_sram_power_on(struct device *dev, bool on) 128 { 129 void __iomem *va_dspsysreg; 130 u32 srampool_con; 131 132 va_dspsysreg = ioremap(ADSP_SRAM_POOL_CON, 0x4); 133 if (!va_dspsysreg) { 134 dev_err(dev, "failed to ioremap sram pool base %#x\n", 135 ADSP_SRAM_POOL_CON); 136 return -ENOMEM; 137 } 138 139 srampool_con = readl(va_dspsysreg); 140 if (on) 141 writel(srampool_con & ~DSP_SRAM_POOL_PD_MASK, va_dspsysreg); 142 else 143 writel(srampool_con | DSP_SRAM_POOL_PD_MASK, va_dspsysreg); 144 145 iounmap(va_dspsysreg); 146 return 0; 147 } 148 149 /* Init the basic DSP DRAM address */ 150 static int adsp_memory_remap_init(struct device *dev, struct mtk_adsp_chip_info *adsp) 151 { 152 void __iomem *vaddr_emi_map; 153 int offset; 154 155 if (!adsp) 156 return -ENXIO; 157 158 vaddr_emi_map = devm_ioremap(dev, DSP_EMI_MAP_ADDR, 0x4); 159 if (!vaddr_emi_map) { 160 dev_err(dev, "failed to ioremap emi map base %#x\n", 161 DSP_EMI_MAP_ADDR); 162 return -ENOMEM; 163 } 164 165 offset = adsp->pa_dram - DRAM_PHYS_BASE_FROM_DSP_VIEW; 166 adsp->dram_offset = offset; 167 offset >>= DRAM_REMAP_SHIFT; 168 dev_dbg(dev, "adsp->pa_dram %pa, offset %#x\n", &adsp->pa_dram, offset); 169 writel(offset, vaddr_emi_map); 170 if (offset != readl(vaddr_emi_map)) { 171 dev_err(dev, "write emi map fail : %#x\n", readl(vaddr_emi_map)); 172 return -EIO; 173 } 174 175 return 0; 176 } 177 178 static int adsp_shared_base_ioremap(struct platform_device *pdev, void *data) 179 { 180 struct device *dev = &pdev->dev; 181 struct mtk_adsp_chip_info *adsp = data; 182 u32 shared_size; 183 184 /* remap shared-dram base to be non-cachable */ 185 shared_size = TOTAL_SIZE_SHARED_DRAM_FROM_TAIL; 186 adsp->pa_shared_dram = adsp->pa_dram + adsp->dramsize - shared_size; 187 if (adsp->va_dram) { 188 adsp->shared_dram = adsp->va_dram + DSP_DRAM_SIZE - shared_size; 189 } else { 190 adsp->shared_dram = devm_ioremap(dev, adsp->pa_shared_dram, 191 shared_size); 192 if (!adsp->shared_dram) { 193 dev_err(dev, "ioremap failed for shared DRAM\n"); 194 return -ENOMEM; 195 } 196 } 197 dev_dbg(dev, "shared-dram vbase=%p, phy addr :%pa, size=%#x\n", 198 adsp->shared_dram, &adsp->pa_shared_dram, shared_size); 199 200 return 0; 201 } 202 203 static int mt8195_run(struct snd_sof_dev *sdev) 204 { 205 u32 adsp_bootup_addr; 206 207 adsp_bootup_addr = SRAM_PHYS_BASE_FROM_DSP_VIEW; 208 dev_dbg(sdev->dev, "HIFIxDSP boot from base : 0x%08X\n", adsp_bootup_addr); 209 sof_hifixdsp_boot_sequence(sdev, adsp_bootup_addr); 210 211 return 0; 212 } 213 214 static int mt8195_dsp_probe(struct snd_sof_dev *sdev) 215 { 216 struct platform_device *pdev = container_of(sdev->dev, struct platform_device, dev); 217 struct adsp_priv *priv; 218 int ret; 219 220 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 221 if (!priv) 222 return -ENOMEM; 223 224 sdev->pdata->hw_pdata = priv; 225 priv->dev = sdev->dev; 226 priv->sdev = sdev; 227 228 priv->adsp = devm_kzalloc(&pdev->dev, sizeof(struct mtk_adsp_chip_info), GFP_KERNEL); 229 if (!priv->adsp) 230 return -ENOMEM; 231 232 ret = platform_parse_resource(pdev, priv->adsp); 233 if (ret) 234 return ret; 235 236 ret = mt8195_adsp_init_clock(sdev); 237 if (ret) { 238 dev_err(sdev->dev, "mt8195_adsp_init_clock failed\n"); 239 return -EINVAL; 240 } 241 242 ret = adsp_clock_on(sdev); 243 if (ret) { 244 dev_err(sdev->dev, "adsp_clock_on fail!\n"); 245 return -EINVAL; 246 } 247 248 ret = adsp_sram_power_on(sdev->dev, true); 249 if (ret) { 250 dev_err(sdev->dev, "adsp_sram_power_on fail!\n"); 251 goto exit_clk_disable; 252 } 253 254 ret = adsp_memory_remap_init(&pdev->dev, priv->adsp); 255 if (ret) { 256 dev_err(sdev->dev, "adsp_memory_remap_init fail!\n"); 257 goto err_adsp_sram_power_off; 258 } 259 260 sdev->bar[SOF_FW_BLK_TYPE_IRAM] = devm_ioremap(sdev->dev, 261 priv->adsp->pa_sram, 262 priv->adsp->sramsize); 263 if (!sdev->bar[SOF_FW_BLK_TYPE_IRAM]) { 264 dev_err(sdev->dev, "failed to ioremap base %pa size %#x\n", 265 &priv->adsp->pa_sram, priv->adsp->sramsize); 266 ret = -EINVAL; 267 goto err_adsp_sram_power_off; 268 } 269 270 sdev->bar[SOF_FW_BLK_TYPE_SRAM] = devm_ioremap_wc(sdev->dev, 271 priv->adsp->pa_dram, 272 priv->adsp->dramsize); 273 if (!sdev->bar[SOF_FW_BLK_TYPE_SRAM]) { 274 dev_err(sdev->dev, "failed to ioremap base %pa size %#x\n", 275 &priv->adsp->pa_dram, priv->adsp->dramsize); 276 ret = -EINVAL; 277 goto err_adsp_sram_power_off; 278 } 279 priv->adsp->va_dram = sdev->bar[SOF_FW_BLK_TYPE_SRAM]; 280 281 ret = adsp_shared_base_ioremap(pdev, priv->adsp); 282 if (ret) { 283 dev_err(sdev->dev, "adsp_shared_base_ioremap fail!\n"); 284 goto err_adsp_sram_power_off; 285 } 286 287 sdev->bar[DSP_REG_BAR] = priv->adsp->va_cfgreg; 288 sdev->bar[DSP_MBOX0_BAR] = priv->adsp->va_mboxreg[0]; 289 sdev->bar[DSP_MBOX1_BAR] = priv->adsp->va_mboxreg[1]; 290 sdev->bar[DSP_MBOX2_BAR] = priv->adsp->va_mboxreg[2]; 291 292 sdev->mmio_bar = SOF_FW_BLK_TYPE_SRAM; 293 sdev->mailbox_bar = SOF_FW_BLK_TYPE_SRAM; 294 295 return 0; 296 297 err_adsp_sram_power_off: 298 adsp_sram_power_on(&pdev->dev, false); 299 exit_clk_disable: 300 adsp_clock_off(sdev); 301 302 return ret; 303 } 304 305 static int mt8195_dsp_remove(struct snd_sof_dev *sdev) 306 { 307 struct platform_device *pdev = container_of(sdev->dev, struct platform_device, dev); 308 309 adsp_sram_power_on(&pdev->dev, false); 310 adsp_clock_off(sdev); 311 312 return 0; 313 } 314 315 static int mt8195_dsp_suspend(struct snd_sof_dev *sdev, u32 target_state) 316 { 317 struct platform_device *pdev = container_of(sdev->dev, struct platform_device, dev); 318 int ret; 319 320 /* stall and reset dsp */ 321 sof_hifixdsp_shutdown(sdev); 322 323 /* power down adsp sram */ 324 ret = adsp_sram_power_on(&pdev->dev, false); 325 if (ret) { 326 dev_err(sdev->dev, "adsp_sram_power_off fail!\n"); 327 return ret; 328 } 329 330 /* turn off adsp clock */ 331 return adsp_clock_off(sdev); 332 } 333 334 static int mt8195_dsp_resume(struct snd_sof_dev *sdev) 335 { 336 int ret; 337 338 /* turn on adsp clock */ 339 ret = adsp_clock_on(sdev); 340 if (ret) { 341 dev_err(sdev->dev, "adsp_clock_on fail!\n"); 342 return ret; 343 } 344 345 /* power on adsp sram */ 346 ret = adsp_sram_power_on(sdev->dev, true); 347 if (ret) 348 dev_err(sdev->dev, "adsp_sram_power_on fail!\n"); 349 350 return ret; 351 } 352 353 /* on mt8195 there is 1 to 1 match between type and BAR idx */ 354 static int mt8195_get_bar_index(struct snd_sof_dev *sdev, u32 type) 355 { 356 return type; 357 } 358 359 static struct snd_soc_dai_driver mt8195_dai[] = { 360 { 361 .name = "SOF_DL2", 362 .playback = { 363 .channels_min = 1, 364 .channels_max = 2, 365 }, 366 }, 367 { 368 .name = "SOF_DL3", 369 .playback = { 370 .channels_min = 1, 371 .channels_max = 2, 372 }, 373 }, 374 { 375 .name = "SOF_UL4", 376 .capture = { 377 .channels_min = 1, 378 .channels_max = 2, 379 }, 380 }, 381 { 382 .name = "SOF_UL5", 383 .capture = { 384 .channels_min = 1, 385 .channels_max = 2, 386 }, 387 }, 388 }; 389 390 /* mt8195 ops */ 391 static const struct snd_sof_dsp_ops sof_mt8195_ops = { 392 /* probe and remove */ 393 .probe = mt8195_dsp_probe, 394 .remove = mt8195_dsp_remove, 395 396 /* DSP core boot */ 397 .run = mt8195_run, 398 399 /* Block IO */ 400 .block_read = sof_block_read, 401 .block_write = sof_block_write, 402 403 /* Register IO */ 404 .write = sof_io_write, 405 .read = sof_io_read, 406 .write64 = sof_io_write64, 407 .read64 = sof_io_read64, 408 409 /* misc */ 410 .get_bar_index = mt8195_get_bar_index, 411 412 /* module loading */ 413 .load_module = snd_sof_parse_module_memcpy, 414 /* firmware loading */ 415 .load_firmware = snd_sof_load_firmware_memcpy, 416 417 /* Firmware ops */ 418 .dsp_arch_ops = &sof_xtensa_arch_ops, 419 420 /* DAI drivers */ 421 .drv = mt8195_dai, 422 .num_drv = ARRAY_SIZE(mt8195_dai), 423 424 /* PM */ 425 .suspend = mt8195_dsp_suspend, 426 .resume = mt8195_dsp_resume, 427 428 /* ALSA HW info flags */ 429 .hw_info = SNDRV_PCM_INFO_MMAP | 430 SNDRV_PCM_INFO_MMAP_VALID | 431 SNDRV_PCM_INFO_INTERLEAVED | 432 SNDRV_PCM_INFO_PAUSE | 433 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP, 434 }; 435 436 static const struct sof_dev_desc sof_of_mt8195_desc = { 437 .default_fw_path = "mediatek/sof", 438 .default_tplg_path = "mediatek/sof-tplg", 439 .default_fw_filename = "sof-mt8195.ri", 440 .nocodec_tplg_filename = "sof-mt8195-nocodec.tplg", 441 .ops = &sof_mt8195_ops, 442 }; 443 444 static const struct of_device_id sof_of_mt8195_ids[] = { 445 { .compatible = "mediatek,mt8195-dsp", .data = &sof_of_mt8195_desc}, 446 { } 447 }; 448 MODULE_DEVICE_TABLE(of, sof_of_mt8195_ids); 449 450 /* DT driver definition */ 451 static struct platform_driver snd_sof_of_mt8195_driver = { 452 .probe = sof_of_probe, 453 .remove = sof_of_remove, 454 .driver = { 455 .name = "sof-audio-of-mt8195", 456 .pm = &sof_of_pm, 457 .of_match_table = sof_of_mt8195_ids, 458 }, 459 }; 460 module_platform_driver(snd_sof_of_mt8195_driver); 461 462 MODULE_IMPORT_NS(SND_SOC_SOF_XTENSA); 463 MODULE_LICENSE("Dual BSD/GPL"); 464