1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 // 3 // Copyright(c) 2021 Mediatek Inc. All rights reserved. 4 // 5 // Author: YC Hung <yc.hung@mediatek.com> 6 // 7 8 /* 9 * Hardware interface for audio DSP on mt8195 10 */ 11 12 #include <linux/delay.h> 13 #include <linux/firmware.h> 14 #include <linux/io.h> 15 #include <linux/of_address.h> 16 #include <linux/of_irq.h> 17 #include <linux/of_platform.h> 18 #include <linux/of_reserved_mem.h> 19 #include <linux/module.h> 20 21 #include <sound/sof.h> 22 #include <sound/sof/xtensa.h> 23 #include "../../ops.h" 24 #include "../../sof-of-dev.h" 25 #include "../../sof-audio.h" 26 #include "../adsp_helper.h" 27 #include "../mtk-adsp-common.h" 28 #include "mt8195.h" 29 #include "mt8195-clk.h" 30 31 static int mt8195_get_mailbox_offset(struct snd_sof_dev *sdev) 32 { 33 return MBOX_OFFSET; 34 } 35 36 static int mt8195_get_window_offset(struct snd_sof_dev *sdev, u32 id) 37 { 38 return MBOX_OFFSET; 39 } 40 41 static int mt8195_send_msg(struct snd_sof_dev *sdev, 42 struct snd_sof_ipc_msg *msg) 43 { 44 struct adsp_priv *priv = sdev->pdata->hw_pdata; 45 46 sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data, 47 msg->msg_size); 48 49 return mtk_adsp_ipc_send(priv->dsp_ipc, MTK_ADSP_IPC_REQ, MTK_ADSP_IPC_OP_REQ); 50 } 51 52 static void mt8195_get_reply(struct snd_sof_dev *sdev) 53 { 54 struct snd_sof_ipc_msg *msg = sdev->msg; 55 struct sof_ipc_reply reply; 56 int ret = 0; 57 58 if (!msg) { 59 dev_warn(sdev->dev, "unexpected ipc interrupt\n"); 60 return; 61 } 62 63 /* get reply */ 64 sof_mailbox_read(sdev, sdev->host_box.offset, &reply, sizeof(reply)); 65 if (reply.error < 0) { 66 memcpy(msg->reply_data, &reply, sizeof(reply)); 67 ret = reply.error; 68 } else { 69 /* reply has correct size? */ 70 if (reply.hdr.size != msg->reply_size) { 71 dev_err(sdev->dev, "error: reply expected %zu got %u bytes\n", 72 msg->reply_size, reply.hdr.size); 73 ret = -EINVAL; 74 } 75 76 /* read the message */ 77 if (msg->reply_size > 0) 78 sof_mailbox_read(sdev, sdev->host_box.offset, 79 msg->reply_data, msg->reply_size); 80 } 81 82 msg->reply_error = ret; 83 } 84 85 static void mt8195_dsp_handle_reply(struct mtk_adsp_ipc *ipc) 86 { 87 struct adsp_priv *priv = mtk_adsp_ipc_get_data(ipc); 88 unsigned long flags; 89 90 spin_lock_irqsave(&priv->sdev->ipc_lock, flags); 91 mt8195_get_reply(priv->sdev); 92 snd_sof_ipc_reply(priv->sdev, 0); 93 spin_unlock_irqrestore(&priv->sdev->ipc_lock, flags); 94 } 95 96 static void mt8195_dsp_handle_request(struct mtk_adsp_ipc *ipc) 97 { 98 struct adsp_priv *priv = mtk_adsp_ipc_get_data(ipc); 99 u32 p; /* panic code */ 100 int ret; 101 102 /* Read the message from the debug box. */ 103 sof_mailbox_read(priv->sdev, priv->sdev->debug_box.offset + 4, 104 &p, sizeof(p)); 105 106 /* Check to see if the message is a panic code 0x0dead*** */ 107 if ((p & SOF_IPC_PANIC_MAGIC_MASK) == SOF_IPC_PANIC_MAGIC) { 108 snd_sof_dsp_panic(priv->sdev, p, true); 109 } else { 110 snd_sof_ipc_msgs_rx(priv->sdev); 111 112 /* tell DSP cmd is done */ 113 ret = mtk_adsp_ipc_send(priv->dsp_ipc, MTK_ADSP_IPC_RSP, MTK_ADSP_IPC_OP_RSP); 114 if (ret) 115 dev_err(priv->dev, "request send ipc failed"); 116 } 117 } 118 119 static struct mtk_adsp_ipc_ops dsp_ops = { 120 .handle_reply = mt8195_dsp_handle_reply, 121 .handle_request = mt8195_dsp_handle_request, 122 }; 123 124 static int platform_parse_resource(struct platform_device *pdev, void *data) 125 { 126 struct resource *mmio; 127 struct resource res; 128 struct device_node *mem_region; 129 struct device *dev = &pdev->dev; 130 struct mtk_adsp_chip_info *adsp = data; 131 int ret; 132 133 mem_region = of_parse_phandle(dev->of_node, "memory-region", 0); 134 if (!mem_region) { 135 dev_err(dev, "no dma memory-region phandle\n"); 136 return -ENODEV; 137 } 138 139 ret = of_address_to_resource(mem_region, 0, &res); 140 of_node_put(mem_region); 141 if (ret) { 142 dev_err(dev, "of_address_to_resource dma failed\n"); 143 return ret; 144 } 145 146 dev_dbg(dev, "DMA %pR\n", &res); 147 148 adsp->pa_shared_dram = (phys_addr_t)res.start; 149 adsp->shared_size = resource_size(&res); 150 if (adsp->pa_shared_dram & DRAM_REMAP_MASK) { 151 dev_err(dev, "adsp shared dma memory(%#x) is not 4K-aligned\n", 152 (u32)adsp->pa_shared_dram); 153 return -EINVAL; 154 } 155 156 ret = of_reserved_mem_device_init(dev); 157 if (ret) { 158 dev_err(dev, "of_reserved_mem_device_init failed\n"); 159 return ret; 160 } 161 162 mem_region = of_parse_phandle(dev->of_node, "memory-region", 1); 163 if (!mem_region) { 164 dev_err(dev, "no memory-region sysmem phandle\n"); 165 return -ENODEV; 166 } 167 168 ret = of_address_to_resource(mem_region, 0, &res); 169 of_node_put(mem_region); 170 if (ret) { 171 dev_err(dev, "of_address_to_resource sysmem failed\n"); 172 return ret; 173 } 174 175 adsp->pa_dram = (phys_addr_t)res.start; 176 adsp->dramsize = resource_size(&res); 177 if (adsp->pa_dram & DRAM_REMAP_MASK) { 178 dev_err(dev, "adsp memory(%#x) is not 4K-aligned\n", 179 (u32)adsp->pa_dram); 180 return -EINVAL; 181 } 182 183 if (adsp->dramsize < TOTAL_SIZE_SHARED_DRAM_FROM_TAIL) { 184 dev_err(dev, "adsp memory(%#x) is not enough for share\n", 185 adsp->dramsize); 186 return -EINVAL; 187 } 188 189 dev_dbg(dev, "dram pbase=%pa, dramsize=%#x\n", 190 &adsp->pa_dram, adsp->dramsize); 191 192 /* Parse CFG base */ 193 mmio = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg"); 194 if (!mmio) { 195 dev_err(dev, "no ADSP-CFG register resource\n"); 196 return -ENXIO; 197 } 198 /* remap for DSP register accessing */ 199 adsp->va_cfgreg = devm_ioremap_resource(dev, mmio); 200 if (IS_ERR(adsp->va_cfgreg)) 201 return PTR_ERR(adsp->va_cfgreg); 202 203 adsp->pa_cfgreg = (phys_addr_t)mmio->start; 204 adsp->cfgregsize = resource_size(mmio); 205 206 dev_dbg(dev, "cfgreg-vbase=%p, cfgregsize=%#x\n", 207 adsp->va_cfgreg, adsp->cfgregsize); 208 209 /* Parse SRAM */ 210 mmio = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sram"); 211 if (!mmio) { 212 dev_err(dev, "no SRAM resource\n"); 213 return -ENXIO; 214 } 215 216 adsp->pa_sram = (phys_addr_t)mmio->start; 217 adsp->sramsize = resource_size(mmio); 218 219 dev_dbg(dev, "sram pbase=%pa,%#x\n", &adsp->pa_sram, adsp->sramsize); 220 221 return ret; 222 } 223 224 static int adsp_sram_power_on(struct device *dev, bool on) 225 { 226 void __iomem *va_dspsysreg; 227 u32 srampool_con; 228 229 va_dspsysreg = ioremap(ADSP_SRAM_POOL_CON, 0x4); 230 if (!va_dspsysreg) { 231 dev_err(dev, "failed to ioremap sram pool base %#x\n", 232 ADSP_SRAM_POOL_CON); 233 return -ENOMEM; 234 } 235 236 srampool_con = readl(va_dspsysreg); 237 if (on) 238 writel(srampool_con & ~DSP_SRAM_POOL_PD_MASK, va_dspsysreg); 239 else 240 writel(srampool_con | DSP_SRAM_POOL_PD_MASK, va_dspsysreg); 241 242 iounmap(va_dspsysreg); 243 return 0; 244 } 245 246 /* Init the basic DSP DRAM address */ 247 static int adsp_memory_remap_init(struct device *dev, struct mtk_adsp_chip_info *adsp) 248 { 249 void __iomem *vaddr_emi_map; 250 int offset; 251 252 if (!adsp) 253 return -ENXIO; 254 255 vaddr_emi_map = devm_ioremap(dev, DSP_EMI_MAP_ADDR, 0x4); 256 if (!vaddr_emi_map) { 257 dev_err(dev, "failed to ioremap emi map base %#x\n", 258 DSP_EMI_MAP_ADDR); 259 return -ENOMEM; 260 } 261 262 offset = adsp->pa_dram - DRAM_PHYS_BASE_FROM_DSP_VIEW; 263 adsp->dram_offset = offset; 264 offset >>= DRAM_REMAP_SHIFT; 265 dev_dbg(dev, "adsp->pa_dram %pa, offset %#x\n", &adsp->pa_dram, offset); 266 writel(offset, vaddr_emi_map); 267 if (offset != readl(vaddr_emi_map)) { 268 dev_err(dev, "write emi map fail : %#x\n", readl(vaddr_emi_map)); 269 return -EIO; 270 } 271 272 return 0; 273 } 274 275 static int adsp_shared_base_ioremap(struct platform_device *pdev, void *data) 276 { 277 struct device *dev = &pdev->dev; 278 struct mtk_adsp_chip_info *adsp = data; 279 280 /* remap shared-dram base to be non-cachable */ 281 adsp->shared_dram = devm_ioremap(dev, adsp->pa_shared_dram, 282 adsp->shared_size); 283 if (!adsp->shared_dram) { 284 dev_err(dev, "failed to ioremap base %pa size %#x\n", 285 adsp->shared_dram, adsp->shared_size); 286 return -ENOMEM; 287 } 288 289 dev_dbg(dev, "shared-dram vbase=%p, phy addr :%pa, size=%#x\n", 290 adsp->shared_dram, &adsp->pa_shared_dram, adsp->shared_size); 291 292 return 0; 293 } 294 295 static int mt8195_run(struct snd_sof_dev *sdev) 296 { 297 u32 adsp_bootup_addr; 298 299 adsp_bootup_addr = SRAM_PHYS_BASE_FROM_DSP_VIEW; 300 dev_dbg(sdev->dev, "HIFIxDSP boot from base : 0x%08X\n", adsp_bootup_addr); 301 sof_hifixdsp_boot_sequence(sdev, adsp_bootup_addr); 302 303 return 0; 304 } 305 306 static int mt8195_dsp_probe(struct snd_sof_dev *sdev) 307 { 308 struct platform_device *pdev = container_of(sdev->dev, struct platform_device, dev); 309 struct adsp_priv *priv; 310 int ret; 311 312 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 313 if (!priv) 314 return -ENOMEM; 315 316 sdev->pdata->hw_pdata = priv; 317 priv->dev = sdev->dev; 318 priv->sdev = sdev; 319 320 priv->adsp = devm_kzalloc(&pdev->dev, sizeof(struct mtk_adsp_chip_info), GFP_KERNEL); 321 if (!priv->adsp) 322 return -ENOMEM; 323 324 ret = platform_parse_resource(pdev, priv->adsp); 325 if (ret) 326 return ret; 327 328 ret = mt8195_adsp_init_clock(sdev); 329 if (ret) { 330 dev_err(sdev->dev, "mt8195_adsp_init_clock failed\n"); 331 return -EINVAL; 332 } 333 334 ret = adsp_clock_on(sdev); 335 if (ret) { 336 dev_err(sdev->dev, "adsp_clock_on fail!\n"); 337 return -EINVAL; 338 } 339 340 ret = adsp_sram_power_on(sdev->dev, true); 341 if (ret) { 342 dev_err(sdev->dev, "adsp_sram_power_on fail!\n"); 343 goto exit_clk_disable; 344 } 345 346 ret = adsp_memory_remap_init(&pdev->dev, priv->adsp); 347 if (ret) { 348 dev_err(sdev->dev, "adsp_memory_remap_init fail!\n"); 349 goto err_adsp_sram_power_off; 350 } 351 352 sdev->bar[SOF_FW_BLK_TYPE_IRAM] = devm_ioremap(sdev->dev, 353 priv->adsp->pa_sram, 354 priv->adsp->sramsize); 355 if (!sdev->bar[SOF_FW_BLK_TYPE_IRAM]) { 356 dev_err(sdev->dev, "failed to ioremap base %pa size %#x\n", 357 &priv->adsp->pa_sram, priv->adsp->sramsize); 358 ret = -EINVAL; 359 goto err_adsp_sram_power_off; 360 } 361 362 priv->adsp->va_sram = sdev->bar[SOF_FW_BLK_TYPE_IRAM]; 363 364 sdev->bar[SOF_FW_BLK_TYPE_SRAM] = devm_ioremap(sdev->dev, 365 priv->adsp->pa_dram, 366 priv->adsp->dramsize); 367 if (!sdev->bar[SOF_FW_BLK_TYPE_SRAM]) { 368 dev_err(sdev->dev, "failed to ioremap base %pa size %#x\n", 369 &priv->adsp->pa_dram, priv->adsp->dramsize); 370 ret = -EINVAL; 371 goto err_adsp_sram_power_off; 372 } 373 priv->adsp->va_dram = sdev->bar[SOF_FW_BLK_TYPE_SRAM]; 374 375 ret = adsp_shared_base_ioremap(pdev, priv->adsp); 376 if (ret) { 377 dev_err(sdev->dev, "adsp_shared_base_ioremap fail!\n"); 378 goto err_adsp_sram_power_off; 379 } 380 381 sdev->bar[DSP_REG_BAR] = priv->adsp->va_cfgreg; 382 383 sdev->mmio_bar = SOF_FW_BLK_TYPE_SRAM; 384 sdev->mailbox_bar = SOF_FW_BLK_TYPE_SRAM; 385 386 /* set default mailbox offset for FW ready message */ 387 sdev->dsp_box.offset = mt8195_get_mailbox_offset(sdev); 388 389 priv->ipc_dev = platform_device_register_data(&pdev->dev, "mtk-adsp-ipc", 390 PLATFORM_DEVID_NONE, 391 pdev, sizeof(*pdev)); 392 if (IS_ERR(priv->ipc_dev)) { 393 ret = PTR_ERR(priv->ipc_dev); 394 dev_err(sdev->dev, "failed to register mtk-adsp-ipc device\n"); 395 goto err_adsp_sram_power_off; 396 } 397 398 priv->dsp_ipc = dev_get_drvdata(&priv->ipc_dev->dev); 399 if (!priv->dsp_ipc) { 400 ret = -EPROBE_DEFER; 401 dev_err(sdev->dev, "failed to get drvdata\n"); 402 goto exit_pdev_unregister; 403 } 404 405 mtk_adsp_ipc_set_data(priv->dsp_ipc, priv); 406 priv->dsp_ipc->ops = &dsp_ops; 407 408 return 0; 409 410 exit_pdev_unregister: 411 platform_device_unregister(priv->ipc_dev); 412 err_adsp_sram_power_off: 413 adsp_sram_power_on(&pdev->dev, false); 414 exit_clk_disable: 415 adsp_clock_off(sdev); 416 417 return ret; 418 } 419 420 static int mt8195_dsp_shutdown(struct snd_sof_dev *sdev) 421 { 422 return snd_sof_suspend(sdev->dev); 423 } 424 425 static int mt8195_dsp_remove(struct snd_sof_dev *sdev) 426 { 427 struct platform_device *pdev = container_of(sdev->dev, struct platform_device, dev); 428 struct adsp_priv *priv = sdev->pdata->hw_pdata; 429 430 platform_device_unregister(priv->ipc_dev); 431 adsp_sram_power_on(&pdev->dev, false); 432 adsp_clock_off(sdev); 433 434 return 0; 435 } 436 437 static int mt8195_dsp_suspend(struct snd_sof_dev *sdev, u32 target_state) 438 { 439 struct platform_device *pdev = container_of(sdev->dev, struct platform_device, dev); 440 int ret; 441 u32 reset_sw, dbg_pc; 442 443 /* wait dsp enter idle, timeout is 1 second */ 444 ret = snd_sof_dsp_read_poll_timeout(sdev, DSP_REG_BAR, 445 DSP_RESET_SW, reset_sw, 446 ((reset_sw & ADSP_PWAIT) == ADSP_PWAIT), 447 SUSPEND_DSP_IDLE_POLL_INTERVAL_US, 448 SUSPEND_DSP_IDLE_TIMEOUT_US); 449 if (ret < 0) { 450 dbg_pc = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGPC); 451 dev_warn(sdev->dev, "dsp not idle, powering off anyway : swrest %#x, pc %#x, ret %d\n", 452 reset_sw, dbg_pc, ret); 453 } 454 455 /* stall and reset dsp */ 456 sof_hifixdsp_shutdown(sdev); 457 458 /* power down adsp sram */ 459 ret = adsp_sram_power_on(&pdev->dev, false); 460 if (ret) { 461 dev_err(sdev->dev, "adsp_sram_power_off fail!\n"); 462 return ret; 463 } 464 465 /* turn off adsp clock */ 466 return adsp_clock_off(sdev); 467 } 468 469 static int mt8195_dsp_resume(struct snd_sof_dev *sdev) 470 { 471 int ret; 472 473 /* turn on adsp clock */ 474 ret = adsp_clock_on(sdev); 475 if (ret) { 476 dev_err(sdev->dev, "adsp_clock_on fail!\n"); 477 return ret; 478 } 479 480 /* power on adsp sram */ 481 ret = adsp_sram_power_on(sdev->dev, true); 482 if (ret) 483 dev_err(sdev->dev, "adsp_sram_power_on fail!\n"); 484 485 return ret; 486 } 487 488 /* on mt8195 there is 1 to 1 match between type and BAR idx */ 489 static int mt8195_get_bar_index(struct snd_sof_dev *sdev, u32 type) 490 { 491 return type; 492 } 493 494 static int mt8195_pcm_hw_params(struct snd_sof_dev *sdev, 495 struct snd_pcm_substream *substream, 496 struct snd_pcm_hw_params *params, 497 struct snd_sof_platform_stream_params *platform_params) 498 { 499 platform_params->cont_update_posn = 1; 500 501 return 0; 502 } 503 504 static snd_pcm_uframes_t mt8195_pcm_pointer(struct snd_sof_dev *sdev, 505 struct snd_pcm_substream *substream) 506 { 507 int ret; 508 snd_pcm_uframes_t pos; 509 struct snd_sof_pcm *spcm; 510 struct sof_ipc_stream_posn posn; 511 struct snd_sof_pcm_stream *stream; 512 struct snd_soc_component *scomp = sdev->component; 513 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); 514 515 spcm = snd_sof_find_spcm_dai(scomp, rtd); 516 if (!spcm) { 517 dev_warn_ratelimited(sdev->dev, "warn: can't find PCM with DAI ID %d\n", 518 rtd->dai_link->id); 519 return 0; 520 } 521 522 stream = &spcm->stream[substream->stream]; 523 ret = snd_sof_ipc_msg_data(sdev, stream, &posn, sizeof(posn)); 524 if (ret < 0) { 525 dev_warn(sdev->dev, "failed to read stream position: %d\n", ret); 526 return 0; 527 } 528 529 memcpy(&stream->posn, &posn, sizeof(posn)); 530 pos = spcm->stream[substream->stream].posn.host_posn; 531 pos = bytes_to_frames(substream->runtime, pos); 532 533 return pos; 534 } 535 536 static void mt8195_adsp_dump(struct snd_sof_dev *sdev, u32 flags) 537 { 538 u32 dbg_pc, dbg_data, dbg_bus0, dbg_bus1, dbg_inst; 539 u32 dbg_ls0stat, dbg_ls1stat, faultbus, faultinfo, swrest; 540 541 /* dump debug registers */ 542 dbg_pc = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGPC); 543 dbg_data = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGDATA); 544 dbg_bus0 = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGBUS0); 545 dbg_bus1 = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGBUS1); 546 dbg_inst = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGINST); 547 dbg_ls0stat = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGLS0STAT); 548 dbg_ls1stat = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGLS1STAT); 549 faultbus = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PFAULTBUS); 550 faultinfo = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PFAULTINFO); 551 swrest = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_RESET_SW); 552 553 dev_info(sdev->dev, "adsp dump : pc %#x, data %#x, bus0 %#x, bus1 %#x, swrest %#x", 554 dbg_pc, dbg_data, dbg_bus0, dbg_bus1, swrest); 555 dev_info(sdev->dev, "dbg_inst %#x, ls0stat %#x, ls1stat %#x, faultbus %#x, faultinfo %#x", 556 dbg_inst, dbg_ls0stat, dbg_ls1stat, faultbus, faultinfo); 557 558 mtk_adsp_dump(sdev, flags); 559 } 560 561 static struct snd_soc_dai_driver mt8195_dai[] = { 562 { 563 .name = "SOF_DL2", 564 .playback = { 565 .channels_min = 1, 566 .channels_max = 2, 567 }, 568 }, 569 { 570 .name = "SOF_DL3", 571 .playback = { 572 .channels_min = 1, 573 .channels_max = 2, 574 }, 575 }, 576 { 577 .name = "SOF_UL4", 578 .capture = { 579 .channels_min = 1, 580 .channels_max = 2, 581 }, 582 }, 583 { 584 .name = "SOF_UL5", 585 .capture = { 586 .channels_min = 1, 587 .channels_max = 2, 588 }, 589 }, 590 }; 591 592 /* mt8195 ops */ 593 static struct snd_sof_dsp_ops sof_mt8195_ops = { 594 /* probe and remove */ 595 .probe = mt8195_dsp_probe, 596 .remove = mt8195_dsp_remove, 597 .shutdown = mt8195_dsp_shutdown, 598 599 /* DSP core boot */ 600 .run = mt8195_run, 601 602 /* Block IO */ 603 .block_read = sof_block_read, 604 .block_write = sof_block_write, 605 606 /* Mailbox IO */ 607 .mailbox_read = sof_mailbox_read, 608 .mailbox_write = sof_mailbox_write, 609 610 /* Register IO */ 611 .write = sof_io_write, 612 .read = sof_io_read, 613 .write64 = sof_io_write64, 614 .read64 = sof_io_read64, 615 616 /* ipc */ 617 .send_msg = mt8195_send_msg, 618 .get_mailbox_offset = mt8195_get_mailbox_offset, 619 .get_window_offset = mt8195_get_window_offset, 620 .ipc_msg_data = sof_ipc_msg_data, 621 .set_stream_data_offset = sof_set_stream_data_offset, 622 623 /* misc */ 624 .get_bar_index = mt8195_get_bar_index, 625 626 /* stream callbacks */ 627 .pcm_open = sof_stream_pcm_open, 628 .pcm_hw_params = mt8195_pcm_hw_params, 629 .pcm_pointer = mt8195_pcm_pointer, 630 .pcm_close = sof_stream_pcm_close, 631 632 /* firmware loading */ 633 .load_firmware = snd_sof_load_firmware_memcpy, 634 635 /* Firmware ops */ 636 .dsp_arch_ops = &sof_xtensa_arch_ops, 637 638 /* Debug information */ 639 .dbg_dump = mt8195_adsp_dump, 640 .debugfs_add_region_item = snd_sof_debugfs_add_region_item_iomem, 641 642 /* DAI drivers */ 643 .drv = mt8195_dai, 644 .num_drv = ARRAY_SIZE(mt8195_dai), 645 646 /* PM */ 647 .suspend = mt8195_dsp_suspend, 648 .resume = mt8195_dsp_resume, 649 650 /* ALSA HW info flags */ 651 .hw_info = SNDRV_PCM_INFO_MMAP | 652 SNDRV_PCM_INFO_MMAP_VALID | 653 SNDRV_PCM_INFO_INTERLEAVED | 654 SNDRV_PCM_INFO_PAUSE | 655 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP, 656 }; 657 658 static struct snd_sof_of_mach sof_mt8195_machs[] = { 659 { 660 .compatible = "google,tomato", 661 .sof_tplg_filename = "sof-mt8195-mt6359-rt1019-rt5682-dts.tplg" 662 }, { 663 .compatible = "mediatek,mt8195", 664 .sof_tplg_filename = "sof-mt8195.tplg" 665 }, { 666 /* sentinel */ 667 } 668 }; 669 670 static const struct sof_dev_desc sof_of_mt8195_desc = { 671 .of_machines = sof_mt8195_machs, 672 .ipc_supported_mask = BIT(SOF_IPC), 673 .ipc_default = SOF_IPC, 674 .default_fw_path = { 675 [SOF_IPC] = "mediatek/sof", 676 }, 677 .default_tplg_path = { 678 [SOF_IPC] = "mediatek/sof-tplg", 679 }, 680 .default_fw_filename = { 681 [SOF_IPC] = "sof-mt8195.ri", 682 }, 683 .nocodec_tplg_filename = "sof-mt8195-nocodec.tplg", 684 .ops = &sof_mt8195_ops, 685 .ipc_timeout = 1000, 686 }; 687 688 static const struct of_device_id sof_of_mt8195_ids[] = { 689 { .compatible = "mediatek,mt8195-dsp", .data = &sof_of_mt8195_desc}, 690 { } 691 }; 692 MODULE_DEVICE_TABLE(of, sof_of_mt8195_ids); 693 694 /* DT driver definition */ 695 static struct platform_driver snd_sof_of_mt8195_driver = { 696 .probe = sof_of_probe, 697 .remove = sof_of_remove, 698 .shutdown = sof_of_shutdown, 699 .driver = { 700 .name = "sof-audio-of-mt8195", 701 .pm = &sof_of_pm, 702 .of_match_table = sof_of_mt8195_ids, 703 }, 704 }; 705 module_platform_driver(snd_sof_of_mt8195_driver); 706 707 MODULE_IMPORT_NS(SND_SOC_SOF_XTENSA); 708 MODULE_IMPORT_NS(SND_SOC_SOF_MTK_COMMON); 709 MODULE_LICENSE("Dual BSD/GPL"); 710