1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2 //
3 // Copyright(c) 2021 Mediatek Inc. All rights reserved.
4 //
5 // Author: YC Hung <yc.hung@mediatek.com>
6 //
7 
8 /*
9  * Hardware interface for audio DSP on mt8195
10  */
11 
12 #include <linux/delay.h>
13 #include <linux/firmware.h>
14 #include <linux/io.h>
15 #include <linux/of_address.h>
16 #include <linux/of_irq.h>
17 #include <linux/of_platform.h>
18 #include <linux/of_reserved_mem.h>
19 #include <linux/module.h>
20 
21 #include <sound/sof.h>
22 #include <sound/sof/xtensa.h>
23 #include "../../ops.h"
24 #include "../../sof-of-dev.h"
25 #include "../../sof-audio.h"
26 #include "../adsp_helper.h"
27 #include "../mtk-adsp-common.h"
28 #include "mt8195.h"
29 #include "mt8195-clk.h"
30 
31 static int mt8195_get_mailbox_offset(struct snd_sof_dev *sdev)
32 {
33 	return MBOX_OFFSET;
34 }
35 
36 static int mt8195_get_window_offset(struct snd_sof_dev *sdev, u32 id)
37 {
38 	return MBOX_OFFSET;
39 }
40 
41 static int mt8195_send_msg(struct snd_sof_dev *sdev,
42 			   struct snd_sof_ipc_msg *msg)
43 {
44 	struct adsp_priv *priv = sdev->pdata->hw_pdata;
45 
46 	sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data,
47 			  msg->msg_size);
48 
49 	return mtk_adsp_ipc_send(priv->dsp_ipc, MTK_ADSP_IPC_REQ, MTK_ADSP_IPC_OP_REQ);
50 }
51 
52 static void mt8195_dsp_handle_reply(struct mtk_adsp_ipc *ipc)
53 {
54 	struct adsp_priv *priv = mtk_adsp_ipc_get_data(ipc);
55 	unsigned long flags;
56 
57 	spin_lock_irqsave(&priv->sdev->ipc_lock, flags);
58 	snd_sof_ipc_process_reply(priv->sdev, 0);
59 	spin_unlock_irqrestore(&priv->sdev->ipc_lock, flags);
60 }
61 
62 static void mt8195_dsp_handle_request(struct mtk_adsp_ipc *ipc)
63 {
64 	struct adsp_priv *priv = mtk_adsp_ipc_get_data(ipc);
65 	u32 p; /* panic code */
66 	int ret;
67 
68 	/* Read the message from the debug box. */
69 	sof_mailbox_read(priv->sdev, priv->sdev->debug_box.offset + 4,
70 			 &p, sizeof(p));
71 
72 	/* Check to see if the message is a panic code 0x0dead*** */
73 	if ((p & SOF_IPC_PANIC_MAGIC_MASK) == SOF_IPC_PANIC_MAGIC) {
74 		snd_sof_dsp_panic(priv->sdev, p, true);
75 	} else {
76 		snd_sof_ipc_msgs_rx(priv->sdev);
77 
78 		/* tell DSP cmd is done */
79 		ret = mtk_adsp_ipc_send(priv->dsp_ipc, MTK_ADSP_IPC_RSP, MTK_ADSP_IPC_OP_RSP);
80 		if (ret)
81 			dev_err(priv->dev, "request send ipc failed");
82 	}
83 }
84 
85 static struct mtk_adsp_ipc_ops dsp_ops = {
86 	.handle_reply		= mt8195_dsp_handle_reply,
87 	.handle_request		= mt8195_dsp_handle_request,
88 };
89 
90 static int platform_parse_resource(struct platform_device *pdev, void *data)
91 {
92 	struct resource *mmio;
93 	struct resource res;
94 	struct device_node *mem_region;
95 	struct device *dev = &pdev->dev;
96 	struct mtk_adsp_chip_info *adsp = data;
97 	int ret;
98 
99 	mem_region = of_parse_phandle(dev->of_node, "memory-region", 0);
100 	if (!mem_region) {
101 		dev_err(dev, "no dma memory-region phandle\n");
102 		return -ENODEV;
103 	}
104 
105 	ret = of_address_to_resource(mem_region, 0, &res);
106 	of_node_put(mem_region);
107 	if (ret) {
108 		dev_err(dev, "of_address_to_resource dma failed\n");
109 		return ret;
110 	}
111 
112 	dev_dbg(dev, "DMA %pR\n", &res);
113 
114 	adsp->pa_shared_dram = (phys_addr_t)res.start;
115 	adsp->shared_size = resource_size(&res);
116 	if (adsp->pa_shared_dram & DRAM_REMAP_MASK) {
117 		dev_err(dev, "adsp shared dma memory(%#x) is not 4K-aligned\n",
118 			(u32)adsp->pa_shared_dram);
119 		return -EINVAL;
120 	}
121 
122 	ret = of_reserved_mem_device_init(dev);
123 	if (ret) {
124 		dev_err(dev, "of_reserved_mem_device_init failed\n");
125 		return ret;
126 	}
127 
128 	mem_region = of_parse_phandle(dev->of_node, "memory-region", 1);
129 	if (!mem_region) {
130 		dev_err(dev, "no memory-region sysmem phandle\n");
131 		return -ENODEV;
132 	}
133 
134 	ret = of_address_to_resource(mem_region, 0, &res);
135 	of_node_put(mem_region);
136 	if (ret) {
137 		dev_err(dev, "of_address_to_resource sysmem failed\n");
138 		return ret;
139 	}
140 
141 	adsp->pa_dram = (phys_addr_t)res.start;
142 	adsp->dramsize = resource_size(&res);
143 	if (adsp->pa_dram & DRAM_REMAP_MASK) {
144 		dev_err(dev, "adsp memory(%#x) is not 4K-aligned\n",
145 			(u32)adsp->pa_dram);
146 		return -EINVAL;
147 	}
148 
149 	if (adsp->dramsize < TOTAL_SIZE_SHARED_DRAM_FROM_TAIL) {
150 		dev_err(dev, "adsp memory(%#x) is not enough for share\n",
151 			adsp->dramsize);
152 		return -EINVAL;
153 	}
154 
155 	dev_dbg(dev, "dram pbase=%pa, dramsize=%#x\n",
156 		&adsp->pa_dram, adsp->dramsize);
157 
158 	/* Parse CFG base */
159 	mmio = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
160 	if (!mmio) {
161 		dev_err(dev, "no ADSP-CFG register resource\n");
162 		return -ENXIO;
163 	}
164 	/* remap for DSP register accessing */
165 	adsp->va_cfgreg = devm_ioremap_resource(dev, mmio);
166 	if (IS_ERR(adsp->va_cfgreg))
167 		return PTR_ERR(adsp->va_cfgreg);
168 
169 	adsp->pa_cfgreg = (phys_addr_t)mmio->start;
170 	adsp->cfgregsize = resource_size(mmio);
171 
172 	dev_dbg(dev, "cfgreg-vbase=%p, cfgregsize=%#x\n",
173 		adsp->va_cfgreg, adsp->cfgregsize);
174 
175 	/* Parse SRAM */
176 	mmio = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sram");
177 	if (!mmio) {
178 		dev_err(dev, "no SRAM resource\n");
179 		return -ENXIO;
180 	}
181 
182 	adsp->pa_sram = (phys_addr_t)mmio->start;
183 	adsp->sramsize = resource_size(mmio);
184 
185 	dev_dbg(dev, "sram pbase=%pa,%#x\n", &adsp->pa_sram, adsp->sramsize);
186 
187 	return ret;
188 }
189 
190 static int adsp_sram_power_on(struct device *dev, bool on)
191 {
192 	void __iomem *va_dspsysreg;
193 	u32 srampool_con;
194 
195 	va_dspsysreg = ioremap(ADSP_SRAM_POOL_CON, 0x4);
196 	if (!va_dspsysreg) {
197 		dev_err(dev, "failed to ioremap sram pool base %#x\n",
198 			ADSP_SRAM_POOL_CON);
199 		return -ENOMEM;
200 	}
201 
202 	srampool_con = readl(va_dspsysreg);
203 	if (on)
204 		writel(srampool_con & ~DSP_SRAM_POOL_PD_MASK, va_dspsysreg);
205 	else
206 		writel(srampool_con | DSP_SRAM_POOL_PD_MASK, va_dspsysreg);
207 
208 	iounmap(va_dspsysreg);
209 	return 0;
210 }
211 
212 /*  Init the basic DSP DRAM address */
213 static int adsp_memory_remap_init(struct device *dev, struct mtk_adsp_chip_info *adsp)
214 {
215 	void __iomem *vaddr_emi_map;
216 	int offset;
217 
218 	if (!adsp)
219 		return -ENXIO;
220 
221 	vaddr_emi_map = devm_ioremap(dev, DSP_EMI_MAP_ADDR, 0x4);
222 	if (!vaddr_emi_map) {
223 		dev_err(dev, "failed to ioremap emi map base %#x\n",
224 			DSP_EMI_MAP_ADDR);
225 		return -ENOMEM;
226 	}
227 
228 	offset = adsp->pa_dram - DRAM_PHYS_BASE_FROM_DSP_VIEW;
229 	adsp->dram_offset = offset;
230 	offset >>= DRAM_REMAP_SHIFT;
231 	dev_dbg(dev, "adsp->pa_dram %pa, offset %#x\n", &adsp->pa_dram, offset);
232 	writel(offset, vaddr_emi_map);
233 	if (offset != readl(vaddr_emi_map)) {
234 		dev_err(dev, "write emi map fail : %#x\n", readl(vaddr_emi_map));
235 		return -EIO;
236 	}
237 
238 	return 0;
239 }
240 
241 static int adsp_shared_base_ioremap(struct platform_device *pdev, void *data)
242 {
243 	struct device *dev = &pdev->dev;
244 	struct mtk_adsp_chip_info *adsp = data;
245 
246 	/* remap shared-dram base to be non-cachable */
247 	adsp->shared_dram = devm_ioremap(dev, adsp->pa_shared_dram,
248 					 adsp->shared_size);
249 	if (!adsp->shared_dram) {
250 		dev_err(dev, "failed to ioremap base %pa size %#x\n",
251 			adsp->shared_dram, adsp->shared_size);
252 		return -ENOMEM;
253 	}
254 
255 	dev_dbg(dev, "shared-dram vbase=%p, phy addr :%pa,  size=%#x\n",
256 		adsp->shared_dram, &adsp->pa_shared_dram, adsp->shared_size);
257 
258 	return 0;
259 }
260 
261 static int mt8195_run(struct snd_sof_dev *sdev)
262 {
263 	u32 adsp_bootup_addr;
264 
265 	adsp_bootup_addr = SRAM_PHYS_BASE_FROM_DSP_VIEW;
266 	dev_dbg(sdev->dev, "HIFIxDSP boot from base : 0x%08X\n", adsp_bootup_addr);
267 	sof_hifixdsp_boot_sequence(sdev, adsp_bootup_addr);
268 
269 	return 0;
270 }
271 
272 static int mt8195_dsp_probe(struct snd_sof_dev *sdev)
273 {
274 	struct platform_device *pdev = container_of(sdev->dev, struct platform_device, dev);
275 	struct adsp_priv *priv;
276 	int ret;
277 
278 	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
279 	if (!priv)
280 		return -ENOMEM;
281 
282 	sdev->pdata->hw_pdata = priv;
283 	priv->dev = sdev->dev;
284 	priv->sdev = sdev;
285 
286 	priv->adsp = devm_kzalloc(&pdev->dev, sizeof(struct mtk_adsp_chip_info), GFP_KERNEL);
287 	if (!priv->adsp)
288 		return -ENOMEM;
289 
290 	ret = platform_parse_resource(pdev, priv->adsp);
291 	if (ret)
292 		return ret;
293 
294 	ret = mt8195_adsp_init_clock(sdev);
295 	if (ret) {
296 		dev_err(sdev->dev, "mt8195_adsp_init_clock failed\n");
297 		return -EINVAL;
298 	}
299 
300 	ret = adsp_clock_on(sdev);
301 	if (ret) {
302 		dev_err(sdev->dev, "adsp_clock_on fail!\n");
303 		return -EINVAL;
304 	}
305 
306 	ret = adsp_sram_power_on(sdev->dev, true);
307 	if (ret) {
308 		dev_err(sdev->dev, "adsp_sram_power_on fail!\n");
309 		goto exit_clk_disable;
310 	}
311 
312 	ret = adsp_memory_remap_init(&pdev->dev, priv->adsp);
313 	if (ret) {
314 		dev_err(sdev->dev, "adsp_memory_remap_init fail!\n");
315 		goto err_adsp_sram_power_off;
316 	}
317 
318 	sdev->bar[SOF_FW_BLK_TYPE_IRAM] = devm_ioremap(sdev->dev,
319 						       priv->adsp->pa_sram,
320 						       priv->adsp->sramsize);
321 	if (!sdev->bar[SOF_FW_BLK_TYPE_IRAM]) {
322 		dev_err(sdev->dev, "failed to ioremap base %pa size %#x\n",
323 			&priv->adsp->pa_sram, priv->adsp->sramsize);
324 		ret = -EINVAL;
325 		goto err_adsp_sram_power_off;
326 	}
327 
328 	priv->adsp->va_sram = sdev->bar[SOF_FW_BLK_TYPE_IRAM];
329 
330 	sdev->bar[SOF_FW_BLK_TYPE_SRAM] = devm_ioremap(sdev->dev,
331 						       priv->adsp->pa_dram,
332 						       priv->adsp->dramsize);
333 	if (!sdev->bar[SOF_FW_BLK_TYPE_SRAM]) {
334 		dev_err(sdev->dev, "failed to ioremap base %pa size %#x\n",
335 			&priv->adsp->pa_dram, priv->adsp->dramsize);
336 		ret = -EINVAL;
337 		goto err_adsp_sram_power_off;
338 	}
339 	priv->adsp->va_dram = sdev->bar[SOF_FW_BLK_TYPE_SRAM];
340 
341 	ret = adsp_shared_base_ioremap(pdev, priv->adsp);
342 	if (ret) {
343 		dev_err(sdev->dev, "adsp_shared_base_ioremap fail!\n");
344 		goto err_adsp_sram_power_off;
345 	}
346 
347 	sdev->bar[DSP_REG_BAR] = priv->adsp->va_cfgreg;
348 
349 	sdev->mmio_bar = SOF_FW_BLK_TYPE_SRAM;
350 	sdev->mailbox_bar = SOF_FW_BLK_TYPE_SRAM;
351 
352 	/* set default mailbox offset for FW ready message */
353 	sdev->dsp_box.offset = mt8195_get_mailbox_offset(sdev);
354 
355 	priv->ipc_dev = platform_device_register_data(&pdev->dev, "mtk-adsp-ipc",
356 						      PLATFORM_DEVID_NONE,
357 						      pdev, sizeof(*pdev));
358 	if (IS_ERR(priv->ipc_dev)) {
359 		ret = PTR_ERR(priv->ipc_dev);
360 		dev_err(sdev->dev, "failed to register mtk-adsp-ipc device\n");
361 		goto err_adsp_sram_power_off;
362 	}
363 
364 	priv->dsp_ipc = dev_get_drvdata(&priv->ipc_dev->dev);
365 	if (!priv->dsp_ipc) {
366 		ret = -EPROBE_DEFER;
367 		dev_err(sdev->dev, "failed to get drvdata\n");
368 		goto exit_pdev_unregister;
369 	}
370 
371 	mtk_adsp_ipc_set_data(priv->dsp_ipc, priv);
372 	priv->dsp_ipc->ops = &dsp_ops;
373 
374 	return 0;
375 
376 exit_pdev_unregister:
377 	platform_device_unregister(priv->ipc_dev);
378 err_adsp_sram_power_off:
379 	adsp_sram_power_on(&pdev->dev, false);
380 exit_clk_disable:
381 	adsp_clock_off(sdev);
382 
383 	return ret;
384 }
385 
386 static int mt8195_dsp_shutdown(struct snd_sof_dev *sdev)
387 {
388 	return snd_sof_suspend(sdev->dev);
389 }
390 
391 static int mt8195_dsp_remove(struct snd_sof_dev *sdev)
392 {
393 	struct platform_device *pdev = container_of(sdev->dev, struct platform_device, dev);
394 	struct adsp_priv *priv = sdev->pdata->hw_pdata;
395 
396 	platform_device_unregister(priv->ipc_dev);
397 	adsp_sram_power_on(&pdev->dev, false);
398 	adsp_clock_off(sdev);
399 
400 	return 0;
401 }
402 
403 static int mt8195_dsp_suspend(struct snd_sof_dev *sdev, u32 target_state)
404 {
405 	struct platform_device *pdev = container_of(sdev->dev, struct platform_device, dev);
406 	int ret;
407 	u32 reset_sw, dbg_pc;
408 
409 	/* wait dsp enter idle, timeout is 1 second */
410 	ret = snd_sof_dsp_read_poll_timeout(sdev, DSP_REG_BAR,
411 					    DSP_RESET_SW, reset_sw,
412 					    ((reset_sw & ADSP_PWAIT) == ADSP_PWAIT),
413 					    SUSPEND_DSP_IDLE_POLL_INTERVAL_US,
414 					    SUSPEND_DSP_IDLE_TIMEOUT_US);
415 	if (ret < 0) {
416 		dbg_pc = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGPC);
417 		dev_warn(sdev->dev, "dsp not idle, powering off anyway : swrest %#x, pc %#x, ret %d\n",
418 			 reset_sw, dbg_pc, ret);
419 	}
420 
421 	/* stall and reset dsp */
422 	sof_hifixdsp_shutdown(sdev);
423 
424 	/* power down adsp sram */
425 	ret = adsp_sram_power_on(&pdev->dev, false);
426 	if (ret) {
427 		dev_err(sdev->dev, "adsp_sram_power_off fail!\n");
428 		return ret;
429 	}
430 
431 	/* turn off adsp clock */
432 	return adsp_clock_off(sdev);
433 }
434 
435 static int mt8195_dsp_resume(struct snd_sof_dev *sdev)
436 {
437 	int ret;
438 
439 	/* turn on adsp clock */
440 	ret = adsp_clock_on(sdev);
441 	if (ret) {
442 		dev_err(sdev->dev, "adsp_clock_on fail!\n");
443 		return ret;
444 	}
445 
446 	/* power on adsp sram */
447 	ret = adsp_sram_power_on(sdev->dev, true);
448 	if (ret)
449 		dev_err(sdev->dev, "adsp_sram_power_on fail!\n");
450 
451 	return ret;
452 }
453 
454 /* on mt8195 there is 1 to 1 match between type and BAR idx */
455 static int mt8195_get_bar_index(struct snd_sof_dev *sdev, u32 type)
456 {
457 	return type;
458 }
459 
460 static int mt8195_pcm_hw_params(struct snd_sof_dev *sdev,
461 				struct snd_pcm_substream *substream,
462 				struct snd_pcm_hw_params *params,
463 				struct snd_sof_platform_stream_params *platform_params)
464 {
465 	platform_params->cont_update_posn = 1;
466 
467 	return 0;
468 }
469 
470 static snd_pcm_uframes_t mt8195_pcm_pointer(struct snd_sof_dev *sdev,
471 					    struct snd_pcm_substream *substream)
472 {
473 	int ret;
474 	snd_pcm_uframes_t pos;
475 	struct snd_sof_pcm *spcm;
476 	struct sof_ipc_stream_posn posn;
477 	struct snd_sof_pcm_stream *stream;
478 	struct snd_soc_component *scomp = sdev->component;
479 	struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
480 
481 	spcm = snd_sof_find_spcm_dai(scomp, rtd);
482 	if (!spcm) {
483 		dev_warn_ratelimited(sdev->dev, "warn: can't find PCM with DAI ID %d\n",
484 				     rtd->dai_link->id);
485 		return 0;
486 	}
487 
488 	stream = &spcm->stream[substream->stream];
489 	ret = snd_sof_ipc_msg_data(sdev, stream, &posn, sizeof(posn));
490 	if (ret < 0) {
491 		dev_warn(sdev->dev, "failed to read stream position: %d\n", ret);
492 		return 0;
493 	}
494 
495 	memcpy(&stream->posn, &posn, sizeof(posn));
496 	pos = spcm->stream[substream->stream].posn.host_posn;
497 	pos = bytes_to_frames(substream->runtime, pos);
498 
499 	return pos;
500 }
501 
502 static void mt8195_adsp_dump(struct snd_sof_dev *sdev, u32 flags)
503 {
504 	u32 dbg_pc, dbg_data, dbg_bus0, dbg_bus1, dbg_inst;
505 	u32 dbg_ls0stat, dbg_ls1stat, faultbus, faultinfo, swrest;
506 
507 	/* dump debug registers */
508 	dbg_pc = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGPC);
509 	dbg_data = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGDATA);
510 	dbg_bus0 = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGBUS0);
511 	dbg_bus1 = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGBUS1);
512 	dbg_inst = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGINST);
513 	dbg_ls0stat = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGLS0STAT);
514 	dbg_ls1stat = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGLS1STAT);
515 	faultbus = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PFAULTBUS);
516 	faultinfo = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PFAULTINFO);
517 	swrest = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_RESET_SW);
518 
519 	dev_info(sdev->dev, "adsp dump : pc %#x, data %#x, bus0 %#x, bus1 %#x, swrest %#x",
520 		 dbg_pc, dbg_data, dbg_bus0, dbg_bus1, swrest);
521 	dev_info(sdev->dev, "dbg_inst %#x, ls0stat %#x, ls1stat %#x, faultbus %#x, faultinfo %#x",
522 		 dbg_inst, dbg_ls0stat, dbg_ls1stat, faultbus, faultinfo);
523 
524 	mtk_adsp_dump(sdev, flags);
525 }
526 
527 static struct snd_soc_dai_driver mt8195_dai[] = {
528 {
529 	.name = "SOF_DL2",
530 	.playback = {
531 		.channels_min = 1,
532 		.channels_max = 2,
533 	},
534 },
535 {
536 	.name = "SOF_DL3",
537 	.playback = {
538 		.channels_min = 1,
539 		.channels_max = 2,
540 	},
541 },
542 {
543 	.name = "SOF_UL4",
544 	.capture = {
545 		.channels_min = 1,
546 		.channels_max = 2,
547 	},
548 },
549 {
550 	.name = "SOF_UL5",
551 	.capture = {
552 		.channels_min = 1,
553 		.channels_max = 2,
554 	},
555 },
556 };
557 
558 /* mt8195 ops */
559 static struct snd_sof_dsp_ops sof_mt8195_ops = {
560 	/* probe and remove */
561 	.probe		= mt8195_dsp_probe,
562 	.remove		= mt8195_dsp_remove,
563 	.shutdown	= mt8195_dsp_shutdown,
564 
565 	/* DSP core boot */
566 	.run		= mt8195_run,
567 
568 	/* Block IO */
569 	.block_read	= sof_block_read,
570 	.block_write	= sof_block_write,
571 
572 	/* Mailbox IO */
573 	.mailbox_read	= sof_mailbox_read,
574 	.mailbox_write	= sof_mailbox_write,
575 
576 	/* Register IO */
577 	.write		= sof_io_write,
578 	.read		= sof_io_read,
579 	.write64	= sof_io_write64,
580 	.read64		= sof_io_read64,
581 
582 	/* ipc */
583 	.send_msg		= mt8195_send_msg,
584 	.get_mailbox_offset	= mt8195_get_mailbox_offset,
585 	.get_window_offset	= mt8195_get_window_offset,
586 	.ipc_msg_data		= sof_ipc_msg_data,
587 	.set_stream_data_offset = sof_set_stream_data_offset,
588 
589 	/* misc */
590 	.get_bar_index	= mt8195_get_bar_index,
591 
592 	/* stream callbacks */
593 	.pcm_open	= sof_stream_pcm_open,
594 	.pcm_hw_params	= mt8195_pcm_hw_params,
595 	.pcm_pointer	= mt8195_pcm_pointer,
596 	.pcm_close	= sof_stream_pcm_close,
597 
598 	/* firmware loading */
599 	.load_firmware	= snd_sof_load_firmware_memcpy,
600 
601 	/* Firmware ops */
602 	.dsp_arch_ops = &sof_xtensa_arch_ops,
603 
604 	/* Debug information */
605 	.dbg_dump = mt8195_adsp_dump,
606 	.debugfs_add_region_item = snd_sof_debugfs_add_region_item_iomem,
607 
608 	/* DAI drivers */
609 	.drv = mt8195_dai,
610 	.num_drv = ARRAY_SIZE(mt8195_dai),
611 
612 	/* PM */
613 	.suspend	= mt8195_dsp_suspend,
614 	.resume		= mt8195_dsp_resume,
615 
616 	/* ALSA HW info flags */
617 	.hw_info =	SNDRV_PCM_INFO_MMAP |
618 			SNDRV_PCM_INFO_MMAP_VALID |
619 			SNDRV_PCM_INFO_INTERLEAVED |
620 			SNDRV_PCM_INFO_PAUSE |
621 			SNDRV_PCM_INFO_NO_PERIOD_WAKEUP,
622 };
623 
624 static struct snd_sof_of_mach sof_mt8195_machs[] = {
625 	{
626 		.compatible = "google,tomato",
627 		.sof_tplg_filename = "sof-mt8195-mt6359-rt1019-rt5682-dts.tplg"
628 	}, {
629 		.compatible = "mediatek,mt8195",
630 		.sof_tplg_filename = "sof-mt8195.tplg"
631 	}, {
632 		/* sentinel */
633 	}
634 };
635 
636 static const struct sof_dev_desc sof_of_mt8195_desc = {
637 	.of_machines = sof_mt8195_machs,
638 	.ipc_supported_mask	= BIT(SOF_IPC),
639 	.ipc_default		= SOF_IPC,
640 	.default_fw_path = {
641 		[SOF_IPC] = "mediatek/sof",
642 	},
643 	.default_tplg_path = {
644 		[SOF_IPC] = "mediatek/sof-tplg",
645 	},
646 	.default_fw_filename = {
647 		[SOF_IPC] = "sof-mt8195.ri",
648 	},
649 	.nocodec_tplg_filename = "sof-mt8195-nocodec.tplg",
650 	.ops = &sof_mt8195_ops,
651 	.ipc_timeout = 1000,
652 };
653 
654 static const struct of_device_id sof_of_mt8195_ids[] = {
655 	{ .compatible = "mediatek,mt8195-dsp", .data = &sof_of_mt8195_desc},
656 	{ }
657 };
658 MODULE_DEVICE_TABLE(of, sof_of_mt8195_ids);
659 
660 /* DT driver definition */
661 static struct platform_driver snd_sof_of_mt8195_driver = {
662 	.probe = sof_of_probe,
663 	.remove = sof_of_remove,
664 	.shutdown = sof_of_shutdown,
665 	.driver = {
666 	.name = "sof-audio-of-mt8195",
667 		.pm = &sof_of_pm,
668 		.of_match_table = sof_of_mt8195_ids,
669 	},
670 };
671 module_platform_driver(snd_sof_of_mt8195_driver);
672 
673 MODULE_IMPORT_NS(SND_SOC_SOF_XTENSA);
674 MODULE_IMPORT_NS(SND_SOC_SOF_MTK_COMMON);
675 MODULE_LICENSE("Dual BSD/GPL");
676