1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2 //
3 // Copyright (c) 2021 Mediatek Corporation. All rights reserved.
4 //
5 // Author: YC Hung <yc.hung@mediatek.com>
6 //
7 // Hardware interface for mt8195 DSP code loader
8 
9 #include <sound/sof.h>
10 #include "mt8195.h"
11 #include "../../ops.h"
12 
13 void sof_hifixdsp_boot_sequence(struct snd_sof_dev *sdev, u32 boot_addr)
14 {
15 	/* ADSP bootup base */
16 	snd_sof_dsp_write(sdev, DSP_REG_BAR, DSP_ALTRESETVEC, boot_addr);
17 
18 	/* pull high RunStall (set bit3 to 1) */
19 	snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, DSP_RESET_SW,
20 				ADSP_RUNSTALL, ADSP_RUNSTALL);
21 
22 	/* pull high StatVectorSel to use AltResetVec (set bit4 to 1) */
23 	snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, DSP_RESET_SW,
24 				STATVECTOR_SEL, STATVECTOR_SEL);
25 
26 	/* toggle  DReset & BReset */
27 	/* pull high DReset & BReset */
28 	snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, DSP_RESET_SW,
29 				ADSP_BRESET_SW | ADSP_DRESET_SW,
30 				ADSP_BRESET_SW | ADSP_DRESET_SW);
31 
32 	/* delay 10 DSP cycles at 26M about 1us by IP vendor's suggestion */
33 	udelay(1);
34 
35 	/* pull low DReset & BReset */
36 	snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, DSP_RESET_SW,
37 				ADSP_BRESET_SW | ADSP_DRESET_SW,
38 				0);
39 
40 	/* Enable PDebug */
41 	snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, DSP_PDEBUGBUS0,
42 				PDEBUG_ENABLE,
43 				PDEBUG_ENABLE);
44 
45 	/* release RunStall (set bit3 to 0) */
46 	snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, DSP_RESET_SW,
47 				ADSP_RUNSTALL, 0);
48 }
49 
50 void sof_hifixdsp_shutdown(struct snd_sof_dev *sdev)
51 {
52 	/* RUN_STALL pull high again to reset */
53 	snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, DSP_RESET_SW,
54 				ADSP_RUNSTALL, ADSP_RUNSTALL);
55 
56 	/* pull high DReset & BReset */
57 	snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, DSP_RESET_SW,
58 				ADSP_BRESET_SW | ADSP_DRESET_SW,
59 				ADSP_BRESET_SW | ADSP_DRESET_SW);
60 }
61 
62