1*424d6d1aSYC Hung /* SPDX-License-Identifier: GPL-2.0 */ 2*424d6d1aSYC Hung 3*424d6d1aSYC Hung /* 4*424d6d1aSYC Hung * Copyright (c) 2021 MediaTek Corporation. All rights reserved. 5*424d6d1aSYC Hung * 6*424d6d1aSYC Hung * Header file for the mt8195 DSP clock definition 7*424d6d1aSYC Hung */ 8*424d6d1aSYC Hung 9*424d6d1aSYC Hung #ifndef __MT8195_CLK_H 10*424d6d1aSYC Hung #define __MT8195_CLK_H 11*424d6d1aSYC Hung 12*424d6d1aSYC Hung struct snd_sof_dev; 13*424d6d1aSYC Hung 14*424d6d1aSYC Hung /*DSP clock*/ 15*424d6d1aSYC Hung enum adsp_clk_id { 16*424d6d1aSYC Hung CLK_TOP_ADSP, 17*424d6d1aSYC Hung CLK_TOP_CLK26M, 18*424d6d1aSYC Hung CLK_TOP_AUDIO_LOCAL_BUS, 19*424d6d1aSYC Hung CLK_TOP_MAINPLL_D7_D2, 20*424d6d1aSYC Hung CLK_SCP_ADSP_AUDIODSP, 21*424d6d1aSYC Hung CLK_TOP_AUDIO_H, 22*424d6d1aSYC Hung ADSP_CLK_MAX 23*424d6d1aSYC Hung }; 24*424d6d1aSYC Hung 25*424d6d1aSYC Hung int mt8195_adsp_init_clock(struct snd_sof_dev *sdev); 26*424d6d1aSYC Hung int adsp_clock_on(struct snd_sof_dev *sdev); 27*424d6d1aSYC Hung int adsp_clock_off(struct snd_sof_dev *sdev); 28*424d6d1aSYC Hung #endif 29