11f0214a8STinghan Shen /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ 21f0214a8STinghan Shen 31f0214a8STinghan Shen /* 41f0214a8STinghan Shen * Copyright (c) 2022 MediaTek Corporation. All rights reserved. 51f0214a8STinghan Shen * 61f0214a8STinghan Shen * Header file for the mt8186 DSP register definition 71f0214a8STinghan Shen */ 81f0214a8STinghan Shen 91f0214a8STinghan Shen #ifndef __MT8186_H 101f0214a8STinghan Shen #define __MT8186_H 111f0214a8STinghan Shen 121f0214a8STinghan Shen struct mtk_adsp_chip_info; 13570c14dcSTinghan Shen struct snd_sof_dev; 141f0214a8STinghan Shen 151f0214a8STinghan Shen #define DSP_REG_BAR 4 161f0214a8STinghan Shen #define DSP_SECREG_BAR 5 171f0214a8STinghan Shen #define DSP_BUSREG_BAR 6 181f0214a8STinghan Shen 191f0214a8STinghan Shen /***************************************************************************** 201f0214a8STinghan Shen * R E G I S T E R TABLE 211f0214a8STinghan Shen *****************************************************************************/ 221f0214a8STinghan Shen /* dsp cfg */ 231f0214a8STinghan Shen #define ADSP_CFGREG_SW_RSTN 0x0000 241f0214a8STinghan Shen #define SW_DBG_RSTN_C0 BIT(0) 251f0214a8STinghan Shen #define SW_RSTN_C0 BIT(4) 261f0214a8STinghan Shen #define ADSP_HIFI_IO_CONFIG 0x000C 271f0214a8STinghan Shen #define TRACEMEMREADY BIT(15) 281f0214a8STinghan Shen #define RUNSTALL BIT(31) 291f0214a8STinghan Shen #define ADSP_IRQ_MASK 0x0030 301f0214a8STinghan Shen #define ADSP_DVFSRC_REQ 0x0040 311f0214a8STinghan Shen #define ADSP_DDREN_REQ_0 0x0044 321f0214a8STinghan Shen #define ADSP_SEMAPHORE 0x0064 331f0214a8STinghan Shen #define ADSP_WDT_CON_C0 0x007C 341f0214a8STinghan Shen #define ADSP_MBOX_IRQ_EN 0x009C 351f0214a8STinghan Shen #define DSP_MBOX0_IRQ_EN BIT(0) 361f0214a8STinghan Shen #define DSP_MBOX1_IRQ_EN BIT(1) 371f0214a8STinghan Shen #define DSP_MBOX2_IRQ_EN BIT(2) 381f0214a8STinghan Shen #define DSP_MBOX3_IRQ_EN BIT(3) 391f0214a8STinghan Shen #define DSP_MBOX4_IRQ_EN BIT(4) 401f0214a8STinghan Shen #define DSP_PDEBUGPC 0x013C 411f0214a8STinghan Shen #define ADSP_CK_EN 0x1000 421f0214a8STinghan Shen #define CORE_CLK_EN BIT(0) 431f0214a8STinghan Shen #define COREDBG_EN BIT(1) 441f0214a8STinghan Shen #define TIMER_EN BIT(3) 451f0214a8STinghan Shen #define DMA_EN BIT(4) 461f0214a8STinghan Shen #define UART_EN BIT(5) 471f0214a8STinghan Shen #define ADSP_UART_CTRL 0x1010 481f0214a8STinghan Shen #define UART_BCLK_CG BIT(0) 491f0214a8STinghan Shen #define UART_RSTN BIT(3) 501f0214a8STinghan Shen 511f0214a8STinghan Shen /* dsp sec */ 521f0214a8STinghan Shen #define ADSP_PRID 0x0 531f0214a8STinghan Shen #define ADSP_ALTVEC_C0 0x04 541f0214a8STinghan Shen #define ADSP_ALTVECSEL 0x0C 551f0214a8STinghan Shen #define ADSP_ALTVECSEL_C0 BIT(1) 561f0214a8STinghan Shen 571f0214a8STinghan Shen /* dsp bus */ 581f0214a8STinghan Shen #define ADSP_SRAM_POOL_CON 0x190 591f0214a8STinghan Shen #define DSP_SRAM_POOL_PD_MASK 0xF00F /* [0:3] and [12:15] */ 601f0214a8STinghan Shen #define DSP_C0_EMI_MAP_ADDR 0xA00 /* ADSP Core0 To EMI Address Remap */ 611f0214a8STinghan Shen #define DSP_C0_DMAEMI_MAP_ADDR 0xA08 /* DMA0 To EMI Address Remap */ 621f0214a8STinghan Shen 631f0214a8STinghan Shen /* DSP memories */ 641f0214a8STinghan Shen #define MBOX_OFFSET 0x500000 /* DRAM */ 651f0214a8STinghan Shen #define MBOX_SIZE 0x1000 /* consistent with which in memory.h of sof fw */ 661f0214a8STinghan Shen #define DSP_DRAM_SIZE 0xA00000 /* 16M */ 671f0214a8STinghan Shen 681f0214a8STinghan Shen /*remap dram between AP and DSP view, 4KB aligned*/ 691f0214a8STinghan Shen #define SRAM_PHYS_BASE_FROM_DSP_VIEW 0x4E100000 /* MT8186 DSP view */ 701f0214a8STinghan Shen #define DRAM_PHYS_BASE_FROM_DSP_VIEW 0x60000000 /* MT8186 DSP view */ 711f0214a8STinghan Shen #define DRAM_REMAP_SHIFT 12 721f0214a8STinghan Shen #define DRAM_REMAP_MASK 0xFFF 731f0214a8STinghan Shen 741f0214a8STinghan Shen #define SIZE_SHARED_DRAM_DL 0x40000 /*Shared buffer for Downlink*/ 751f0214a8STinghan Shen #define SIZE_SHARED_DRAM_UL 0x40000 /*Shared buffer for Uplink*/ 761f0214a8STinghan Shen #define TOTAL_SIZE_SHARED_DRAM_FROM_TAIL (SIZE_SHARED_DRAM_DL + SIZE_SHARED_DRAM_UL) 771f0214a8STinghan Shen 78*9ce170dcSTinghan Shen void mt8186_sof_hifixdsp_boot_sequence(struct snd_sof_dev *sdev, u32 boot_addr); 79*9ce170dcSTinghan Shen void mt8186_sof_hifixdsp_shutdown(struct snd_sof_dev *sdev); 801f0214a8STinghan Shen #endif 81