1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2 //
3 // Copyright(c) 2022 Mediatek Inc. All rights reserved.
4 //
5 // Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
6 //         Tinghan Shen <tinghan.shen@mediatek.com>
7 
8 /*
9  * Hardware interface for audio DSP on mt8186
10  */
11 
12 #include <linux/delay.h>
13 #include <linux/firmware.h>
14 #include <linux/io.h>
15 #include <linux/of_address.h>
16 #include <linux/of_irq.h>
17 #include <linux/of_platform.h>
18 #include <linux/of_reserved_mem.h>
19 #include <linux/module.h>
20 
21 #include <sound/sof.h>
22 #include <sound/sof/xtensa.h>
23 #include "../../ops.h"
24 #include "../../sof-of-dev.h"
25 #include "../../sof-audio.h"
26 #include "../adsp_helper.h"
27 #include "mt8186.h"
28 #include "mt8186-clk.h"
29 
30 static int mt8186_get_mailbox_offset(struct snd_sof_dev *sdev)
31 {
32 	return MBOX_OFFSET;
33 }
34 
35 static int mt8186_get_window_offset(struct snd_sof_dev *sdev, u32 id)
36 {
37 	return MBOX_OFFSET;
38 }
39 
40 static int mt8186_send_msg(struct snd_sof_dev *sdev,
41 			   struct snd_sof_ipc_msg *msg)
42 {
43 	struct adsp_priv *priv = sdev->pdata->hw_pdata;
44 
45 	sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data,
46 			  msg->msg_size);
47 
48 	return mtk_adsp_ipc_send(priv->dsp_ipc, MTK_ADSP_IPC_REQ, MTK_ADSP_IPC_OP_REQ);
49 }
50 
51 static void mt8186_get_reply(struct snd_sof_dev *sdev)
52 {
53 	struct snd_sof_ipc_msg *msg = sdev->msg;
54 	struct sof_ipc_reply reply;
55 	int ret = 0;
56 
57 	if (!msg) {
58 		dev_warn(sdev->dev, "unexpected ipc interrupt\n");
59 		return;
60 	}
61 
62 	/* get reply */
63 	sof_mailbox_read(sdev, sdev->host_box.offset, &reply, sizeof(reply));
64 	if (reply.error < 0) {
65 		memcpy(msg->reply_data, &reply, sizeof(reply));
66 		ret = reply.error;
67 	} else {
68 		/* reply has correct size? */
69 		if (reply.hdr.size != msg->reply_size) {
70 			dev_err(sdev->dev, "error: reply expected %zu got %u bytes\n",
71 				msg->reply_size, reply.hdr.size);
72 			ret = -EINVAL;
73 		}
74 
75 		/* read the message */
76 		if (msg->reply_size > 0)
77 			sof_mailbox_read(sdev, sdev->host_box.offset,
78 					 msg->reply_data, msg->reply_size);
79 	}
80 
81 	msg->reply_error = ret;
82 }
83 
84 static void mt8186_dsp_handle_reply(struct mtk_adsp_ipc *ipc)
85 {
86 	struct adsp_priv *priv = mtk_adsp_ipc_get_data(ipc);
87 	unsigned long flags;
88 
89 	spin_lock_irqsave(&priv->sdev->ipc_lock, flags);
90 	mt8186_get_reply(priv->sdev);
91 	snd_sof_ipc_reply(priv->sdev, 0);
92 	spin_unlock_irqrestore(&priv->sdev->ipc_lock, flags);
93 }
94 
95 static void mt8186_dsp_handle_request(struct mtk_adsp_ipc *ipc)
96 {
97 	struct adsp_priv *priv = mtk_adsp_ipc_get_data(ipc);
98 	u32 p; /* panic code */
99 	int ret;
100 
101 	/* Read the message from the debug box. */
102 	sof_mailbox_read(priv->sdev, priv->sdev->debug_box.offset + 4,
103 			 &p, sizeof(p));
104 
105 	/* Check to see if the message is a panic code 0x0dead*** */
106 	if ((p & SOF_IPC_PANIC_MAGIC_MASK) == SOF_IPC_PANIC_MAGIC) {
107 		snd_sof_dsp_panic(priv->sdev, p, true);
108 	} else {
109 		snd_sof_ipc_msgs_rx(priv->sdev);
110 
111 		/* tell DSP cmd is done */
112 		ret = mtk_adsp_ipc_send(priv->dsp_ipc, MTK_ADSP_IPC_RSP, MTK_ADSP_IPC_OP_RSP);
113 		if (ret)
114 			dev_err(priv->dev, "request send ipc failed");
115 	}
116 }
117 
118 static struct mtk_adsp_ipc_ops dsp_ops = {
119 	.handle_reply		= mt8186_dsp_handle_reply,
120 	.handle_request		= mt8186_dsp_handle_request,
121 };
122 
123 static int platform_parse_resource(struct platform_device *pdev, void *data)
124 {
125 	struct resource *mmio;
126 	struct resource res;
127 	struct device_node *mem_region;
128 	struct device *dev = &pdev->dev;
129 	struct mtk_adsp_chip_info *adsp = data;
130 	int ret;
131 
132 	mem_region = of_parse_phandle(dev->of_node, "memory-region", 0);
133 	if (!mem_region) {
134 		dev_err(dev, "no dma memory-region phandle\n");
135 		return -ENODEV;
136 	}
137 
138 	ret = of_address_to_resource(mem_region, 0, &res);
139 	of_node_put(mem_region);
140 	if (ret) {
141 		dev_err(dev, "of_address_to_resource dma failed\n");
142 		return ret;
143 	}
144 
145 	dev_dbg(dev, "DMA %pR\n", &res);
146 
147 	ret = of_reserved_mem_device_init(dev);
148 	if (ret) {
149 		dev_err(dev, "of_reserved_mem_device_init failed\n");
150 		return ret;
151 	}
152 
153 	mem_region = of_parse_phandle(dev->of_node, "memory-region", 1);
154 	if (!mem_region) {
155 		dev_err(dev, "no memory-region sysmem phandle\n");
156 		return -ENODEV;
157 	}
158 
159 	ret = of_address_to_resource(mem_region, 0, &res);
160 	of_node_put(mem_region);
161 	if (ret) {
162 		dev_err(dev, "of_address_to_resource sysmem failed\n");
163 		return ret;
164 	}
165 
166 	adsp->pa_dram = (phys_addr_t)res.start;
167 	if (adsp->pa_dram & DRAM_REMAP_MASK) {
168 		dev_err(dev, "adsp memory(%#x) is not 4K-aligned\n",
169 			(u32)adsp->pa_dram);
170 		return -EINVAL;
171 	}
172 
173 	adsp->dramsize = resource_size(&res);
174 	if (adsp->dramsize < TOTAL_SIZE_SHARED_DRAM_FROM_TAIL) {
175 		dev_err(dev, "adsp memory(%#x) is not enough for share\n",
176 			adsp->dramsize);
177 		return -EINVAL;
178 	}
179 
180 	dev_dbg(dev, "dram pbase=%pa size=%#x\n", &adsp->pa_dram, adsp->dramsize);
181 
182 	mmio = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
183 	if (!mmio) {
184 		dev_err(dev, "no ADSP-CFG register resource\n");
185 		return -ENXIO;
186 	}
187 
188 	adsp->va_cfgreg = devm_ioremap_resource(dev, mmio);
189 	if (IS_ERR(adsp->va_cfgreg))
190 		return PTR_ERR(adsp->va_cfgreg);
191 
192 	adsp->pa_cfgreg = (phys_addr_t)mmio->start;
193 	adsp->cfgregsize = resource_size(mmio);
194 
195 	dev_dbg(dev, "cfgreg pbase=%pa size=%#x\n", &adsp->pa_cfgreg, adsp->cfgregsize);
196 
197 	mmio = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sram");
198 	if (!mmio) {
199 		dev_err(dev, "no SRAM resource\n");
200 		return -ENXIO;
201 	}
202 
203 	adsp->pa_sram = (phys_addr_t)mmio->start;
204 	adsp->sramsize = resource_size(mmio);
205 
206 	dev_dbg(dev, "sram pbase=%pa size=%#x\n", &adsp->pa_sram, adsp->sramsize);
207 
208 	mmio = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sec");
209 	if (!mmio) {
210 		dev_err(dev, "no SEC register resource\n");
211 		return -ENXIO;
212 	}
213 
214 	adsp->va_secreg = devm_ioremap_resource(dev, mmio);
215 	if (IS_ERR(adsp->va_secreg))
216 		return PTR_ERR(adsp->va_secreg);
217 
218 	adsp->pa_secreg = (phys_addr_t)mmio->start;
219 	adsp->secregsize = resource_size(mmio);
220 
221 	dev_dbg(dev, "secreg pbase=%pa size=%#x\n", &adsp->pa_secreg, adsp->secregsize);
222 
223 	mmio = platform_get_resource_byname(pdev, IORESOURCE_MEM, "bus");
224 	if (!mmio) {
225 		dev_err(dev, "no BUS register resource\n");
226 		return -ENXIO;
227 	}
228 
229 	adsp->va_busreg = devm_ioremap_resource(dev, mmio);
230 	if (IS_ERR(adsp->va_busreg))
231 		return PTR_ERR(adsp->va_busreg);
232 
233 	adsp->pa_busreg = (phys_addr_t)mmio->start;
234 	adsp->busregsize = resource_size(mmio);
235 
236 	dev_dbg(dev, "busreg pbase=%pa size=%#x\n", &adsp->pa_busreg, adsp->busregsize);
237 
238 	return 0;
239 }
240 
241 static void adsp_sram_power_on(struct snd_sof_dev *sdev)
242 {
243 	snd_sof_dsp_update_bits(sdev, DSP_BUSREG_BAR, ADSP_SRAM_POOL_CON,
244 				DSP_SRAM_POOL_PD_MASK, 0);
245 }
246 
247 static void adsp_sram_power_off(struct snd_sof_dev *sdev)
248 {
249 	snd_sof_dsp_update_bits(sdev, DSP_BUSREG_BAR, ADSP_SRAM_POOL_CON,
250 				DSP_SRAM_POOL_PD_MASK, DSP_SRAM_POOL_PD_MASK);
251 }
252 
253 /*  Init the basic DSP DRAM address */
254 static int adsp_memory_remap_init(struct snd_sof_dev *sdev, struct mtk_adsp_chip_info *adsp)
255 {
256 	u32 offset;
257 
258 	offset = adsp->pa_dram - DRAM_PHYS_BASE_FROM_DSP_VIEW;
259 	adsp->dram_offset = offset;
260 	offset >>= DRAM_REMAP_SHIFT;
261 
262 	dev_dbg(sdev->dev, "adsp->pa_dram %pa, offset %#x\n", &adsp->pa_dram, offset);
263 
264 	snd_sof_dsp_write(sdev, DSP_BUSREG_BAR, DSP_C0_EMI_MAP_ADDR, offset);
265 	snd_sof_dsp_write(sdev, DSP_BUSREG_BAR, DSP_C0_DMAEMI_MAP_ADDR, offset);
266 
267 	if (offset != snd_sof_dsp_read(sdev, DSP_BUSREG_BAR, DSP_C0_EMI_MAP_ADDR) ||
268 	    offset != snd_sof_dsp_read(sdev, DSP_BUSREG_BAR, DSP_C0_DMAEMI_MAP_ADDR)) {
269 		dev_err(sdev->dev, "emi remap fail\n");
270 		return -EIO;
271 	}
272 
273 	return 0;
274 }
275 
276 static int adsp_shared_base_ioremap(struct platform_device *pdev, void *data)
277 {
278 	struct device *dev = &pdev->dev;
279 	struct mtk_adsp_chip_info *adsp = data;
280 	u32 shared_size;
281 
282 	/* remap shared-dram base to be non-cachable */
283 	shared_size = TOTAL_SIZE_SHARED_DRAM_FROM_TAIL;
284 	adsp->pa_shared_dram = adsp->pa_dram + adsp->dramsize - shared_size;
285 	if (adsp->va_dram) {
286 		adsp->shared_dram = adsp->va_dram + DSP_DRAM_SIZE - shared_size;
287 	} else {
288 		adsp->shared_dram = devm_ioremap(dev, adsp->pa_shared_dram,
289 						 shared_size);
290 		if (!adsp->shared_dram) {
291 			dev_err(dev, "ioremap failed for shared DRAM\n");
292 			return -ENOMEM;
293 		}
294 	}
295 	dev_dbg(dev, "shared-dram vbase=%p, phy addr :%pa, size=%#x\n",
296 		adsp->shared_dram, &adsp->pa_shared_dram, shared_size);
297 
298 	return 0;
299 }
300 
301 static int mt8186_run(struct snd_sof_dev *sdev)
302 {
303 	u32 adsp_bootup_addr;
304 
305 	adsp_bootup_addr = SRAM_PHYS_BASE_FROM_DSP_VIEW;
306 	dev_dbg(sdev->dev, "HIFIxDSP boot from base : 0x%08X\n", adsp_bootup_addr);
307 	mt8186_sof_hifixdsp_boot_sequence(sdev, adsp_bootup_addr);
308 
309 	return 0;
310 }
311 
312 static int mt8186_dsp_probe(struct snd_sof_dev *sdev)
313 {
314 	struct platform_device *pdev = container_of(sdev->dev, struct platform_device, dev);
315 	struct adsp_priv *priv;
316 	int ret;
317 
318 	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
319 	if (!priv)
320 		return -ENOMEM;
321 
322 	sdev->pdata->hw_pdata = priv;
323 	priv->dev = sdev->dev;
324 	priv->sdev = sdev;
325 
326 	priv->adsp = devm_kzalloc(&pdev->dev, sizeof(struct mtk_adsp_chip_info), GFP_KERNEL);
327 	if (!priv->adsp)
328 		return -ENOMEM;
329 
330 	ret = platform_parse_resource(pdev, priv->adsp);
331 	if (ret)
332 		return ret;
333 
334 	sdev->bar[SOF_FW_BLK_TYPE_IRAM] = devm_ioremap(sdev->dev,
335 						       priv->adsp->pa_sram,
336 						       priv->adsp->sramsize);
337 	if (!sdev->bar[SOF_FW_BLK_TYPE_IRAM]) {
338 		dev_err(sdev->dev, "failed to ioremap base %pa size %#x\n",
339 			&priv->adsp->pa_sram, priv->adsp->sramsize);
340 		return -ENOMEM;
341 	}
342 
343 	sdev->bar[SOF_FW_BLK_TYPE_SRAM] = devm_ioremap_wc(sdev->dev,
344 							  priv->adsp->pa_dram,
345 							  priv->adsp->dramsize);
346 	if (!sdev->bar[SOF_FW_BLK_TYPE_SRAM]) {
347 		dev_err(sdev->dev, "failed to ioremap base %pa size %#x\n",
348 			&priv->adsp->pa_dram, priv->adsp->dramsize);
349 		return -ENOMEM;
350 	}
351 
352 	priv->adsp->va_dram = sdev->bar[SOF_FW_BLK_TYPE_SRAM];
353 
354 	ret = adsp_shared_base_ioremap(pdev, priv->adsp);
355 	if (ret) {
356 		dev_err(sdev->dev, "adsp_shared_base_ioremap fail!\n");
357 		return ret;
358 	}
359 
360 	sdev->bar[DSP_REG_BAR] = priv->adsp->va_cfgreg;
361 	sdev->bar[DSP_SECREG_BAR] = priv->adsp->va_secreg;
362 	sdev->bar[DSP_BUSREG_BAR] = priv->adsp->va_busreg;
363 
364 	sdev->mmio_bar = SOF_FW_BLK_TYPE_SRAM;
365 	sdev->mailbox_bar = SOF_FW_BLK_TYPE_SRAM;
366 
367 	/* set default mailbox offset for FW ready message */
368 	sdev->dsp_box.offset = mt8186_get_mailbox_offset(sdev);
369 
370 	ret = adsp_memory_remap_init(sdev, priv->adsp);
371 	if (ret) {
372 		dev_err(sdev->dev, "adsp_memory_remap_init fail!\n");
373 		return ret;
374 	}
375 
376 	/* enable adsp clock before touching registers */
377 	ret = mt8186_adsp_init_clock(sdev);
378 	if (ret) {
379 		dev_err(sdev->dev, "mt8186_adsp_init_clock failed\n");
380 		return ret;
381 	}
382 
383 	ret = mt8186_adsp_clock_on(sdev);
384 	if (ret) {
385 		dev_err(sdev->dev, "mt8186_adsp_clock_on fail!\n");
386 		return ret;
387 	}
388 
389 	adsp_sram_power_on(sdev);
390 
391 	priv->ipc_dev = platform_device_register_data(&pdev->dev, "mtk-adsp-ipc",
392 						      PLATFORM_DEVID_NONE,
393 						      pdev, sizeof(*pdev));
394 	if (IS_ERR(priv->ipc_dev)) {
395 		ret = IS_ERR(priv->ipc_dev);
396 		dev_err(sdev->dev, "failed to create mtk-adsp-ipc device\n");
397 		goto err_adsp_off;
398 	}
399 
400 	priv->dsp_ipc = dev_get_drvdata(&priv->ipc_dev->dev);
401 	if (!priv->dsp_ipc) {
402 		ret = -EPROBE_DEFER;
403 		dev_err(sdev->dev, "failed to get drvdata\n");
404 		goto exit_pdev_unregister;
405 	}
406 
407 	mtk_adsp_ipc_set_data(priv->dsp_ipc, priv);
408 	priv->dsp_ipc->ops = &dsp_ops;
409 
410 	return 0;
411 
412 exit_pdev_unregister:
413 	platform_device_unregister(priv->ipc_dev);
414 err_adsp_off:
415 	adsp_sram_power_off(sdev);
416 	mt8186_adsp_clock_off(sdev);
417 
418 	return ret;
419 }
420 
421 static int mt8186_dsp_remove(struct snd_sof_dev *sdev)
422 {
423 	struct adsp_priv *priv = sdev->pdata->hw_pdata;
424 
425 	platform_device_unregister(priv->ipc_dev);
426 	mt8186_sof_hifixdsp_shutdown(sdev);
427 	adsp_sram_power_off(sdev);
428 	mt8186_adsp_clock_off(sdev);
429 
430 	return 0;
431 }
432 
433 static int mt8186_dsp_suspend(struct snd_sof_dev *sdev, u32 target_state)
434 {
435 	mt8186_sof_hifixdsp_shutdown(sdev);
436 	adsp_sram_power_off(sdev);
437 	mt8186_adsp_clock_off(sdev);
438 
439 	return 0;
440 }
441 
442 static int mt8186_dsp_resume(struct snd_sof_dev *sdev)
443 {
444 	int ret;
445 
446 	ret = mt8186_adsp_clock_on(sdev);
447 	if (ret) {
448 		dev_err(sdev->dev, "mt8186_adsp_clock_on fail!\n");
449 		return ret;
450 	}
451 
452 	adsp_sram_power_on(sdev);
453 
454 	return ret;
455 }
456 
457 /* on mt8186 there is 1 to 1 match between type and BAR idx */
458 static int mt8186_get_bar_index(struct snd_sof_dev *sdev, u32 type)
459 {
460 	return type;
461 }
462 
463 static int mt8186_ipc_msg_data(struct snd_sof_dev *sdev,
464 			       struct snd_pcm_substream *substream,
465 			       void *p, size_t sz)
466 {
467 	sof_mailbox_read(sdev, sdev->dsp_box.offset, p, sz);
468 	return 0;
469 }
470 
471 /* mt8186 ops */
472 static struct snd_sof_dsp_ops sof_mt8186_ops = {
473 	/* probe and remove */
474 	.probe		= mt8186_dsp_probe,
475 	.remove		= mt8186_dsp_remove,
476 
477 	/* DSP core boot */
478 	.run		= mt8186_run,
479 
480 	/* Block IO */
481 	.block_read	= sof_block_read,
482 	.block_write	= sof_block_write,
483 
484 	/* Register IO */
485 	.write		= sof_io_write,
486 	.read		= sof_io_read,
487 	.write64	= sof_io_write64,
488 	.read64		= sof_io_read64,
489 
490 	/* ipc */
491 	.send_msg		= mt8186_send_msg,
492 	.get_mailbox_offset	= mt8186_get_mailbox_offset,
493 	.get_window_offset	= mt8186_get_window_offset,
494 	.ipc_msg_data		= mt8186_ipc_msg_data,
495 	.set_stream_data_offset = sof_set_stream_data_offset,
496 
497 	/* misc */
498 	.get_bar_index	= mt8186_get_bar_index,
499 
500 	/* firmware loading */
501 	.load_firmware	= snd_sof_load_firmware_memcpy,
502 
503 	/* Firmware ops */
504 	.dsp_arch_ops = &sof_xtensa_arch_ops,
505 
506 	/* PM */
507 	.suspend	= mt8186_dsp_suspend,
508 	.resume		= mt8186_dsp_resume,
509 
510 	/* ALSA HW info flags */
511 	.hw_info =	SNDRV_PCM_INFO_MMAP |
512 			SNDRV_PCM_INFO_MMAP_VALID |
513 			SNDRV_PCM_INFO_INTERLEAVED |
514 			SNDRV_PCM_INFO_PAUSE |
515 			SNDRV_PCM_INFO_NO_PERIOD_WAKEUP,
516 };
517 
518 static const struct sof_dev_desc sof_of_mt8186_desc = {
519 	.ipc_supported_mask	= BIT(SOF_IPC),
520 	.ipc_default		= SOF_IPC,
521 	.default_fw_path = {
522 		[SOF_IPC] = "mediatek/sof",
523 	},
524 	.default_tplg_path = {
525 		[SOF_IPC] = "mediatek/sof-tplg",
526 	},
527 	.default_fw_filename = {
528 		[SOF_IPC] = "sof-mt8186.ri",
529 	},
530 	.nocodec_tplg_filename = "sof-mt8186-nocodec.tplg",
531 	.ops = &sof_mt8186_ops,
532 };
533 
534 static const struct of_device_id sof_of_mt8186_ids[] = {
535 	{ .compatible = "mediatek,mt8186-dsp", .data = &sof_of_mt8186_desc},
536 	{ }
537 };
538 MODULE_DEVICE_TABLE(of, sof_of_mt8186_ids);
539 
540 /* DT driver definition */
541 static struct platform_driver snd_sof_of_mt8186_driver = {
542 	.probe = sof_of_probe,
543 	.remove = sof_of_remove,
544 	.driver = {
545 	.name = "sof-audio-of-mt8186",
546 		.pm = &sof_of_pm,
547 		.of_match_table = sof_of_mt8186_ids,
548 	},
549 };
550 module_platform_driver(snd_sof_of_mt8186_driver);
551 
552 MODULE_IMPORT_NS(SND_SOC_SOF_XTENSA);
553 MODULE_IMPORT_NS(SND_SOC_SOF_MTK_COMMON);
554 MODULE_LICENSE("Dual BSD/GPL");
555