1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 // 3 // Copyright(c) 2022 Mediatek Inc. All rights reserved. 4 // 5 // Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com> 6 // Tinghan Shen <tinghan.shen@mediatek.com> 7 8 /* 9 * Hardware interface for audio DSP on mt8186 10 */ 11 12 #include <linux/delay.h> 13 #include <linux/firmware.h> 14 #include <linux/io.h> 15 #include <linux/of_address.h> 16 #include <linux/of_irq.h> 17 #include <linux/of_platform.h> 18 #include <linux/of_reserved_mem.h> 19 #include <linux/module.h> 20 21 #include <sound/sof.h> 22 #include <sound/sof/xtensa.h> 23 #include "../../ops.h" 24 #include "../../sof-of-dev.h" 25 #include "../../sof-audio.h" 26 #include "../adsp_helper.h" 27 #include "mt8186.h" 28 #include "mt8186-clk.h" 29 30 static int mt8186_get_mailbox_offset(struct snd_sof_dev *sdev) 31 { 32 return MBOX_OFFSET; 33 } 34 35 static int mt8186_get_window_offset(struct snd_sof_dev *sdev, u32 id) 36 { 37 return MBOX_OFFSET; 38 } 39 40 static int mt8186_send_msg(struct snd_sof_dev *sdev, 41 struct snd_sof_ipc_msg *msg) 42 { 43 struct adsp_priv *priv = sdev->pdata->hw_pdata; 44 45 sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data, 46 msg->msg_size); 47 48 return mtk_adsp_ipc_send(priv->dsp_ipc, MTK_ADSP_IPC_REQ, MTK_ADSP_IPC_OP_REQ); 49 } 50 51 static void mt8186_dsp_handle_reply(struct mtk_adsp_ipc *ipc) 52 { 53 struct adsp_priv *priv = mtk_adsp_ipc_get_data(ipc); 54 unsigned long flags; 55 56 spin_lock_irqsave(&priv->sdev->ipc_lock, flags); 57 snd_sof_ipc_process_reply(priv->sdev, 0); 58 spin_unlock_irqrestore(&priv->sdev->ipc_lock, flags); 59 } 60 61 static void mt8186_dsp_handle_request(struct mtk_adsp_ipc *ipc) 62 { 63 struct adsp_priv *priv = mtk_adsp_ipc_get_data(ipc); 64 u32 p; /* panic code */ 65 int ret; 66 67 /* Read the message from the debug box. */ 68 sof_mailbox_read(priv->sdev, priv->sdev->debug_box.offset + 4, 69 &p, sizeof(p)); 70 71 /* Check to see if the message is a panic code 0x0dead*** */ 72 if ((p & SOF_IPC_PANIC_MAGIC_MASK) == SOF_IPC_PANIC_MAGIC) { 73 snd_sof_dsp_panic(priv->sdev, p, true); 74 } else { 75 snd_sof_ipc_msgs_rx(priv->sdev); 76 77 /* tell DSP cmd is done */ 78 ret = mtk_adsp_ipc_send(priv->dsp_ipc, MTK_ADSP_IPC_RSP, MTK_ADSP_IPC_OP_RSP); 79 if (ret) 80 dev_err(priv->dev, "request send ipc failed"); 81 } 82 } 83 84 static struct mtk_adsp_ipc_ops dsp_ops = { 85 .handle_reply = mt8186_dsp_handle_reply, 86 .handle_request = mt8186_dsp_handle_request, 87 }; 88 89 static int platform_parse_resource(struct platform_device *pdev, void *data) 90 { 91 struct resource *mmio; 92 struct resource res; 93 struct device_node *mem_region; 94 struct device *dev = &pdev->dev; 95 struct mtk_adsp_chip_info *adsp = data; 96 int ret; 97 98 mem_region = of_parse_phandle(dev->of_node, "memory-region", 0); 99 if (!mem_region) { 100 dev_err(dev, "no dma memory-region phandle\n"); 101 return -ENODEV; 102 } 103 104 ret = of_address_to_resource(mem_region, 0, &res); 105 of_node_put(mem_region); 106 if (ret) { 107 dev_err(dev, "of_address_to_resource dma failed\n"); 108 return ret; 109 } 110 111 dev_dbg(dev, "DMA %pR\n", &res); 112 113 ret = of_reserved_mem_device_init(dev); 114 if (ret) { 115 dev_err(dev, "of_reserved_mem_device_init failed\n"); 116 return ret; 117 } 118 119 mem_region = of_parse_phandle(dev->of_node, "memory-region", 1); 120 if (!mem_region) { 121 dev_err(dev, "no memory-region sysmem phandle\n"); 122 return -ENODEV; 123 } 124 125 ret = of_address_to_resource(mem_region, 0, &res); 126 of_node_put(mem_region); 127 if (ret) { 128 dev_err(dev, "of_address_to_resource sysmem failed\n"); 129 return ret; 130 } 131 132 adsp->pa_dram = (phys_addr_t)res.start; 133 if (adsp->pa_dram & DRAM_REMAP_MASK) { 134 dev_err(dev, "adsp memory(%#x) is not 4K-aligned\n", 135 (u32)adsp->pa_dram); 136 return -EINVAL; 137 } 138 139 adsp->dramsize = resource_size(&res); 140 if (adsp->dramsize < TOTAL_SIZE_SHARED_DRAM_FROM_TAIL) { 141 dev_err(dev, "adsp memory(%#x) is not enough for share\n", 142 adsp->dramsize); 143 return -EINVAL; 144 } 145 146 dev_dbg(dev, "dram pbase=%pa size=%#x\n", &adsp->pa_dram, adsp->dramsize); 147 148 mmio = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg"); 149 if (!mmio) { 150 dev_err(dev, "no ADSP-CFG register resource\n"); 151 return -ENXIO; 152 } 153 154 adsp->va_cfgreg = devm_ioremap_resource(dev, mmio); 155 if (IS_ERR(adsp->va_cfgreg)) 156 return PTR_ERR(adsp->va_cfgreg); 157 158 adsp->pa_cfgreg = (phys_addr_t)mmio->start; 159 adsp->cfgregsize = resource_size(mmio); 160 161 dev_dbg(dev, "cfgreg pbase=%pa size=%#x\n", &adsp->pa_cfgreg, adsp->cfgregsize); 162 163 mmio = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sram"); 164 if (!mmio) { 165 dev_err(dev, "no SRAM resource\n"); 166 return -ENXIO; 167 } 168 169 adsp->pa_sram = (phys_addr_t)mmio->start; 170 adsp->sramsize = resource_size(mmio); 171 172 dev_dbg(dev, "sram pbase=%pa size=%#x\n", &adsp->pa_sram, adsp->sramsize); 173 174 mmio = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sec"); 175 if (!mmio) { 176 dev_err(dev, "no SEC register resource\n"); 177 return -ENXIO; 178 } 179 180 adsp->va_secreg = devm_ioremap_resource(dev, mmio); 181 if (IS_ERR(adsp->va_secreg)) 182 return PTR_ERR(adsp->va_secreg); 183 184 adsp->pa_secreg = (phys_addr_t)mmio->start; 185 adsp->secregsize = resource_size(mmio); 186 187 dev_dbg(dev, "secreg pbase=%pa size=%#x\n", &adsp->pa_secreg, adsp->secregsize); 188 189 mmio = platform_get_resource_byname(pdev, IORESOURCE_MEM, "bus"); 190 if (!mmio) { 191 dev_err(dev, "no BUS register resource\n"); 192 return -ENXIO; 193 } 194 195 adsp->va_busreg = devm_ioremap_resource(dev, mmio); 196 if (IS_ERR(adsp->va_busreg)) 197 return PTR_ERR(adsp->va_busreg); 198 199 adsp->pa_busreg = (phys_addr_t)mmio->start; 200 adsp->busregsize = resource_size(mmio); 201 202 dev_dbg(dev, "busreg pbase=%pa size=%#x\n", &adsp->pa_busreg, adsp->busregsize); 203 204 return 0; 205 } 206 207 static void adsp_sram_power_on(struct snd_sof_dev *sdev) 208 { 209 snd_sof_dsp_update_bits(sdev, DSP_BUSREG_BAR, ADSP_SRAM_POOL_CON, 210 DSP_SRAM_POOL_PD_MASK, 0); 211 } 212 213 static void adsp_sram_power_off(struct snd_sof_dev *sdev) 214 { 215 snd_sof_dsp_update_bits(sdev, DSP_BUSREG_BAR, ADSP_SRAM_POOL_CON, 216 DSP_SRAM_POOL_PD_MASK, DSP_SRAM_POOL_PD_MASK); 217 } 218 219 /* Init the basic DSP DRAM address */ 220 static int adsp_memory_remap_init(struct snd_sof_dev *sdev, struct mtk_adsp_chip_info *adsp) 221 { 222 u32 offset; 223 224 offset = adsp->pa_dram - DRAM_PHYS_BASE_FROM_DSP_VIEW; 225 adsp->dram_offset = offset; 226 offset >>= DRAM_REMAP_SHIFT; 227 228 dev_dbg(sdev->dev, "adsp->pa_dram %pa, offset %#x\n", &adsp->pa_dram, offset); 229 230 snd_sof_dsp_write(sdev, DSP_BUSREG_BAR, DSP_C0_EMI_MAP_ADDR, offset); 231 snd_sof_dsp_write(sdev, DSP_BUSREG_BAR, DSP_C0_DMAEMI_MAP_ADDR, offset); 232 233 if (offset != snd_sof_dsp_read(sdev, DSP_BUSREG_BAR, DSP_C0_EMI_MAP_ADDR) || 234 offset != snd_sof_dsp_read(sdev, DSP_BUSREG_BAR, DSP_C0_DMAEMI_MAP_ADDR)) { 235 dev_err(sdev->dev, "emi remap fail\n"); 236 return -EIO; 237 } 238 239 return 0; 240 } 241 242 static int adsp_shared_base_ioremap(struct platform_device *pdev, void *data) 243 { 244 struct device *dev = &pdev->dev; 245 struct mtk_adsp_chip_info *adsp = data; 246 u32 shared_size; 247 248 /* remap shared-dram base to be non-cachable */ 249 shared_size = TOTAL_SIZE_SHARED_DRAM_FROM_TAIL; 250 adsp->pa_shared_dram = adsp->pa_dram + adsp->dramsize - shared_size; 251 if (adsp->va_dram) { 252 adsp->shared_dram = adsp->va_dram + DSP_DRAM_SIZE - shared_size; 253 } else { 254 adsp->shared_dram = devm_ioremap(dev, adsp->pa_shared_dram, 255 shared_size); 256 if (!adsp->shared_dram) { 257 dev_err(dev, "ioremap failed for shared DRAM\n"); 258 return -ENOMEM; 259 } 260 } 261 dev_dbg(dev, "shared-dram vbase=%p, phy addr :%pa, size=%#x\n", 262 adsp->shared_dram, &adsp->pa_shared_dram, shared_size); 263 264 return 0; 265 } 266 267 static int mt8186_run(struct snd_sof_dev *sdev) 268 { 269 u32 adsp_bootup_addr; 270 271 adsp_bootup_addr = SRAM_PHYS_BASE_FROM_DSP_VIEW; 272 dev_dbg(sdev->dev, "HIFIxDSP boot from base : 0x%08X\n", adsp_bootup_addr); 273 mt8186_sof_hifixdsp_boot_sequence(sdev, adsp_bootup_addr); 274 275 return 0; 276 } 277 278 static int mt8186_dsp_probe(struct snd_sof_dev *sdev) 279 { 280 struct platform_device *pdev = container_of(sdev->dev, struct platform_device, dev); 281 struct adsp_priv *priv; 282 int ret; 283 284 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 285 if (!priv) 286 return -ENOMEM; 287 288 sdev->pdata->hw_pdata = priv; 289 priv->dev = sdev->dev; 290 priv->sdev = sdev; 291 292 priv->adsp = devm_kzalloc(&pdev->dev, sizeof(struct mtk_adsp_chip_info), GFP_KERNEL); 293 if (!priv->adsp) 294 return -ENOMEM; 295 296 ret = platform_parse_resource(pdev, priv->adsp); 297 if (ret) 298 return ret; 299 300 sdev->bar[SOF_FW_BLK_TYPE_IRAM] = devm_ioremap(sdev->dev, 301 priv->adsp->pa_sram, 302 priv->adsp->sramsize); 303 if (!sdev->bar[SOF_FW_BLK_TYPE_IRAM]) { 304 dev_err(sdev->dev, "failed to ioremap base %pa size %#x\n", 305 &priv->adsp->pa_sram, priv->adsp->sramsize); 306 return -ENOMEM; 307 } 308 309 sdev->bar[SOF_FW_BLK_TYPE_SRAM] = devm_ioremap_wc(sdev->dev, 310 priv->adsp->pa_dram, 311 priv->adsp->dramsize); 312 if (!sdev->bar[SOF_FW_BLK_TYPE_SRAM]) { 313 dev_err(sdev->dev, "failed to ioremap base %pa size %#x\n", 314 &priv->adsp->pa_dram, priv->adsp->dramsize); 315 return -ENOMEM; 316 } 317 318 priv->adsp->va_dram = sdev->bar[SOF_FW_BLK_TYPE_SRAM]; 319 320 ret = adsp_shared_base_ioremap(pdev, priv->adsp); 321 if (ret) { 322 dev_err(sdev->dev, "adsp_shared_base_ioremap fail!\n"); 323 return ret; 324 } 325 326 sdev->bar[DSP_REG_BAR] = priv->adsp->va_cfgreg; 327 sdev->bar[DSP_SECREG_BAR] = priv->adsp->va_secreg; 328 sdev->bar[DSP_BUSREG_BAR] = priv->adsp->va_busreg; 329 330 sdev->mmio_bar = SOF_FW_BLK_TYPE_SRAM; 331 sdev->mailbox_bar = SOF_FW_BLK_TYPE_SRAM; 332 333 /* set default mailbox offset for FW ready message */ 334 sdev->dsp_box.offset = mt8186_get_mailbox_offset(sdev); 335 336 ret = adsp_memory_remap_init(sdev, priv->adsp); 337 if (ret) { 338 dev_err(sdev->dev, "adsp_memory_remap_init fail!\n"); 339 return ret; 340 } 341 342 /* enable adsp clock before touching registers */ 343 ret = mt8186_adsp_init_clock(sdev); 344 if (ret) { 345 dev_err(sdev->dev, "mt8186_adsp_init_clock failed\n"); 346 return ret; 347 } 348 349 ret = mt8186_adsp_clock_on(sdev); 350 if (ret) { 351 dev_err(sdev->dev, "mt8186_adsp_clock_on fail!\n"); 352 return ret; 353 } 354 355 adsp_sram_power_on(sdev); 356 357 priv->ipc_dev = platform_device_register_data(&pdev->dev, "mtk-adsp-ipc", 358 PLATFORM_DEVID_NONE, 359 pdev, sizeof(*pdev)); 360 if (IS_ERR(priv->ipc_dev)) { 361 ret = PTR_ERR(priv->ipc_dev); 362 dev_err(sdev->dev, "failed to create mtk-adsp-ipc device\n"); 363 goto err_adsp_off; 364 } 365 366 priv->dsp_ipc = dev_get_drvdata(&priv->ipc_dev->dev); 367 if (!priv->dsp_ipc) { 368 ret = -EPROBE_DEFER; 369 dev_err(sdev->dev, "failed to get drvdata\n"); 370 goto exit_pdev_unregister; 371 } 372 373 mtk_adsp_ipc_set_data(priv->dsp_ipc, priv); 374 priv->dsp_ipc->ops = &dsp_ops; 375 376 return 0; 377 378 exit_pdev_unregister: 379 platform_device_unregister(priv->ipc_dev); 380 err_adsp_off: 381 adsp_sram_power_off(sdev); 382 mt8186_adsp_clock_off(sdev); 383 384 return ret; 385 } 386 387 static int mt8186_dsp_remove(struct snd_sof_dev *sdev) 388 { 389 struct adsp_priv *priv = sdev->pdata->hw_pdata; 390 391 platform_device_unregister(priv->ipc_dev); 392 mt8186_sof_hifixdsp_shutdown(sdev); 393 adsp_sram_power_off(sdev); 394 mt8186_adsp_clock_off(sdev); 395 396 return 0; 397 } 398 399 static int mt8186_dsp_shutdown(struct snd_sof_dev *sdev) 400 { 401 return snd_sof_suspend(sdev->dev); 402 } 403 404 static int mt8186_dsp_suspend(struct snd_sof_dev *sdev, u32 target_state) 405 { 406 mt8186_sof_hifixdsp_shutdown(sdev); 407 adsp_sram_power_off(sdev); 408 mt8186_adsp_clock_off(sdev); 409 410 return 0; 411 } 412 413 static int mt8186_dsp_resume(struct snd_sof_dev *sdev) 414 { 415 int ret; 416 417 ret = mt8186_adsp_clock_on(sdev); 418 if (ret) { 419 dev_err(sdev->dev, "mt8186_adsp_clock_on fail!\n"); 420 return ret; 421 } 422 423 adsp_sram_power_on(sdev); 424 425 return ret; 426 } 427 428 /* on mt8186 there is 1 to 1 match between type and BAR idx */ 429 static int mt8186_get_bar_index(struct snd_sof_dev *sdev, u32 type) 430 { 431 return type; 432 } 433 434 static int mt8186_pcm_hw_params(struct snd_sof_dev *sdev, 435 struct snd_pcm_substream *substream, 436 struct snd_pcm_hw_params *params, 437 struct snd_sof_platform_stream_params *platform_params) 438 { 439 platform_params->cont_update_posn = 1; 440 441 return 0; 442 } 443 444 static snd_pcm_uframes_t mt8186_pcm_pointer(struct snd_sof_dev *sdev, 445 struct snd_pcm_substream *substream) 446 { 447 int ret; 448 snd_pcm_uframes_t pos; 449 struct snd_sof_pcm *spcm; 450 struct sof_ipc_stream_posn posn; 451 struct snd_sof_pcm_stream *stream; 452 struct snd_soc_component *scomp = sdev->component; 453 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); 454 455 spcm = snd_sof_find_spcm_dai(scomp, rtd); 456 if (!spcm) { 457 dev_warn_ratelimited(sdev->dev, "warn: can't find PCM with DAI ID %d\n", 458 rtd->dai_link->id); 459 return 0; 460 } 461 462 stream = &spcm->stream[substream->stream]; 463 ret = snd_sof_ipc_msg_data(sdev, stream, &posn, sizeof(posn)); 464 if (ret < 0) { 465 dev_warn(sdev->dev, "failed to read stream position: %d\n", ret); 466 return 0; 467 } 468 469 memcpy(&stream->posn, &posn, sizeof(posn)); 470 pos = spcm->stream[substream->stream].posn.host_posn; 471 pos = bytes_to_frames(substream->runtime, pos); 472 473 return pos; 474 } 475 476 static struct snd_soc_dai_driver mt8186_dai[] = { 477 { 478 .name = "SOF_DL1", 479 .playback = { 480 .channels_min = 1, 481 .channels_max = 2, 482 }, 483 }, 484 { 485 .name = "SOF_DL2", 486 .playback = { 487 .channels_min = 1, 488 .channels_max = 2, 489 }, 490 }, 491 { 492 .name = "SOF_UL1", 493 .capture = { 494 .channels_min = 1, 495 .channels_max = 2, 496 }, 497 }, 498 { 499 .name = "SOF_UL2", 500 .capture = { 501 .channels_min = 1, 502 .channels_max = 2, 503 }, 504 }, 505 }; 506 507 /* mt8186 ops */ 508 static struct snd_sof_dsp_ops sof_mt8186_ops = { 509 /* probe and remove */ 510 .probe = mt8186_dsp_probe, 511 .remove = mt8186_dsp_remove, 512 .shutdown = mt8186_dsp_shutdown, 513 514 /* DSP core boot */ 515 .run = mt8186_run, 516 517 /* Block IO */ 518 .block_read = sof_block_read, 519 .block_write = sof_block_write, 520 521 /* Mailbox IO */ 522 .mailbox_read = sof_mailbox_read, 523 .mailbox_write = sof_mailbox_write, 524 525 /* Register IO */ 526 .write = sof_io_write, 527 .read = sof_io_read, 528 .write64 = sof_io_write64, 529 .read64 = sof_io_read64, 530 531 /* ipc */ 532 .send_msg = mt8186_send_msg, 533 .get_mailbox_offset = mt8186_get_mailbox_offset, 534 .get_window_offset = mt8186_get_window_offset, 535 .ipc_msg_data = sof_ipc_msg_data, 536 .set_stream_data_offset = sof_set_stream_data_offset, 537 538 /* misc */ 539 .get_bar_index = mt8186_get_bar_index, 540 541 /* stream callbacks */ 542 .pcm_open = sof_stream_pcm_open, 543 .pcm_hw_params = mt8186_pcm_hw_params, 544 .pcm_pointer = mt8186_pcm_pointer, 545 .pcm_close = sof_stream_pcm_close, 546 547 /* firmware loading */ 548 .load_firmware = snd_sof_load_firmware_memcpy, 549 550 /* Firmware ops */ 551 .dsp_arch_ops = &sof_xtensa_arch_ops, 552 553 /* DAI drivers */ 554 .drv = mt8186_dai, 555 .num_drv = ARRAY_SIZE(mt8186_dai), 556 557 /* Debug information */ 558 .debugfs_add_region_item = snd_sof_debugfs_add_region_item_iomem, 559 560 /* PM */ 561 .suspend = mt8186_dsp_suspend, 562 .resume = mt8186_dsp_resume, 563 564 /* ALSA HW info flags */ 565 .hw_info = SNDRV_PCM_INFO_MMAP | 566 SNDRV_PCM_INFO_MMAP_VALID | 567 SNDRV_PCM_INFO_INTERLEAVED | 568 SNDRV_PCM_INFO_PAUSE | 569 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP, 570 }; 571 572 static struct snd_sof_of_mach sof_mt8186_machs[] = { 573 { 574 .compatible = "mediatek,mt8186", 575 .sof_tplg_filename = "sof-mt8186.tplg", 576 }, 577 {} 578 }; 579 580 static const struct sof_dev_desc sof_of_mt8186_desc = { 581 .of_machines = sof_mt8186_machs, 582 .ipc_supported_mask = BIT(SOF_IPC), 583 .ipc_default = SOF_IPC, 584 .default_fw_path = { 585 [SOF_IPC] = "mediatek/sof", 586 }, 587 .default_tplg_path = { 588 [SOF_IPC] = "mediatek/sof-tplg", 589 }, 590 .default_fw_filename = { 591 [SOF_IPC] = "sof-mt8186.ri", 592 }, 593 .nocodec_tplg_filename = "sof-mt8186-nocodec.tplg", 594 .ops = &sof_mt8186_ops, 595 }; 596 597 static const struct sof_dev_desc sof_of_mt8188_desc = { 598 .ipc_supported_mask = BIT(SOF_IPC), 599 .ipc_default = SOF_IPC, 600 .default_fw_path = { 601 [SOF_IPC] = "mediatek/sof", 602 }, 603 .default_tplg_path = { 604 [SOF_IPC] = "mediatek/sof-tplg", 605 }, 606 .default_fw_filename = { 607 [SOF_IPC] = "sof-mt8188.ri", 608 }, 609 .nocodec_tplg_filename = "sof-mt8188-nocodec.tplg", 610 .ops = &sof_mt8186_ops, 611 }; 612 613 static const struct of_device_id sof_of_mt8186_ids[] = { 614 { .compatible = "mediatek,mt8186-dsp", .data = &sof_of_mt8186_desc}, 615 { .compatible = "mediatek,mt8188-dsp", .data = &sof_of_mt8188_desc}, 616 { } 617 }; 618 MODULE_DEVICE_TABLE(of, sof_of_mt8186_ids); 619 620 /* DT driver definition */ 621 static struct platform_driver snd_sof_of_mt8186_driver = { 622 .probe = sof_of_probe, 623 .remove = sof_of_remove, 624 .shutdown = sof_of_shutdown, 625 .driver = { 626 .name = "sof-audio-of-mt8186", 627 .pm = &sof_of_pm, 628 .of_match_table = sof_of_mt8186_ids, 629 }, 630 }; 631 module_platform_driver(snd_sof_of_mt8186_driver); 632 633 MODULE_IMPORT_NS(SND_SOC_SOF_XTENSA); 634 MODULE_IMPORT_NS(SND_SOC_SOF_MTK_COMMON); 635 MODULE_LICENSE("Dual BSD/GPL"); 636