1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2 //
3 // Copyright(c) 2022 Mediatek Inc. All rights reserved.
4 //
5 // Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
6 //         Tinghan Shen <tinghan.shen@mediatek.com>
7 
8 /*
9  * Hardware interface for audio DSP on mt8186
10  */
11 
12 #include <linux/delay.h>
13 #include <linux/firmware.h>
14 #include <linux/io.h>
15 #include <linux/of_address.h>
16 #include <linux/of_irq.h>
17 #include <linux/of_platform.h>
18 #include <linux/of_reserved_mem.h>
19 #include <linux/module.h>
20 
21 #include <sound/sof.h>
22 #include <sound/sof/xtensa.h>
23 #include "../../ops.h"
24 #include "../../sof-of-dev.h"
25 #include "../../sof-audio.h"
26 #include "../adsp_helper.h"
27 #include "../mtk-adsp-common.h"
28 #include "mt8186.h"
29 #include "mt8186-clk.h"
30 
31 static int mt8186_get_mailbox_offset(struct snd_sof_dev *sdev)
32 {
33 	return MBOX_OFFSET;
34 }
35 
36 static int mt8186_get_window_offset(struct snd_sof_dev *sdev, u32 id)
37 {
38 	return MBOX_OFFSET;
39 }
40 
41 static int mt8186_send_msg(struct snd_sof_dev *sdev,
42 			   struct snd_sof_ipc_msg *msg)
43 {
44 	struct adsp_priv *priv = sdev->pdata->hw_pdata;
45 
46 	sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data,
47 			  msg->msg_size);
48 
49 	return mtk_adsp_ipc_send(priv->dsp_ipc, MTK_ADSP_IPC_REQ, MTK_ADSP_IPC_OP_REQ);
50 }
51 
52 static void mt8186_dsp_handle_reply(struct mtk_adsp_ipc *ipc)
53 {
54 	struct adsp_priv *priv = mtk_adsp_ipc_get_data(ipc);
55 	unsigned long flags;
56 
57 	spin_lock_irqsave(&priv->sdev->ipc_lock, flags);
58 	snd_sof_ipc_process_reply(priv->sdev, 0);
59 	spin_unlock_irqrestore(&priv->sdev->ipc_lock, flags);
60 }
61 
62 static void mt8186_dsp_handle_request(struct mtk_adsp_ipc *ipc)
63 {
64 	struct adsp_priv *priv = mtk_adsp_ipc_get_data(ipc);
65 	u32 p; /* panic code */
66 	int ret;
67 
68 	/* Read the message from the debug box. */
69 	sof_mailbox_read(priv->sdev, priv->sdev->debug_box.offset + 4,
70 			 &p, sizeof(p));
71 
72 	/* Check to see if the message is a panic code 0x0dead*** */
73 	if ((p & SOF_IPC_PANIC_MAGIC_MASK) == SOF_IPC_PANIC_MAGIC) {
74 		snd_sof_dsp_panic(priv->sdev, p, true);
75 	} else {
76 		snd_sof_ipc_msgs_rx(priv->sdev);
77 
78 		/* tell DSP cmd is done */
79 		ret = mtk_adsp_ipc_send(priv->dsp_ipc, MTK_ADSP_IPC_RSP, MTK_ADSP_IPC_OP_RSP);
80 		if (ret)
81 			dev_err(priv->dev, "request send ipc failed");
82 	}
83 }
84 
85 static struct mtk_adsp_ipc_ops dsp_ops = {
86 	.handle_reply		= mt8186_dsp_handle_reply,
87 	.handle_request		= mt8186_dsp_handle_request,
88 };
89 
90 static int platform_parse_resource(struct platform_device *pdev, void *data)
91 {
92 	struct resource *mmio;
93 	struct resource res;
94 	struct device_node *mem_region;
95 	struct device *dev = &pdev->dev;
96 	struct mtk_adsp_chip_info *adsp = data;
97 	int ret;
98 
99 	mem_region = of_parse_phandle(dev->of_node, "memory-region", 0);
100 	if (!mem_region) {
101 		dev_err(dev, "no dma memory-region phandle\n");
102 		return -ENODEV;
103 	}
104 
105 	ret = of_address_to_resource(mem_region, 0, &res);
106 	of_node_put(mem_region);
107 	if (ret) {
108 		dev_err(dev, "of_address_to_resource dma failed\n");
109 		return ret;
110 	}
111 
112 	dev_dbg(dev, "DMA %pR\n", &res);
113 
114 	ret = of_reserved_mem_device_init(dev);
115 	if (ret) {
116 		dev_err(dev, "of_reserved_mem_device_init failed\n");
117 		return ret;
118 	}
119 
120 	mem_region = of_parse_phandle(dev->of_node, "memory-region", 1);
121 	if (!mem_region) {
122 		dev_err(dev, "no memory-region sysmem phandle\n");
123 		return -ENODEV;
124 	}
125 
126 	ret = of_address_to_resource(mem_region, 0, &res);
127 	of_node_put(mem_region);
128 	if (ret) {
129 		dev_err(dev, "of_address_to_resource sysmem failed\n");
130 		return ret;
131 	}
132 
133 	adsp->pa_dram = (phys_addr_t)res.start;
134 	if (adsp->pa_dram & DRAM_REMAP_MASK) {
135 		dev_err(dev, "adsp memory(%#x) is not 4K-aligned\n",
136 			(u32)adsp->pa_dram);
137 		return -EINVAL;
138 	}
139 
140 	adsp->dramsize = resource_size(&res);
141 	if (adsp->dramsize < TOTAL_SIZE_SHARED_DRAM_FROM_TAIL) {
142 		dev_err(dev, "adsp memory(%#x) is not enough for share\n",
143 			adsp->dramsize);
144 		return -EINVAL;
145 	}
146 
147 	dev_dbg(dev, "dram pbase=%pa size=%#x\n", &adsp->pa_dram, adsp->dramsize);
148 
149 	mmio = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
150 	if (!mmio) {
151 		dev_err(dev, "no ADSP-CFG register resource\n");
152 		return -ENXIO;
153 	}
154 
155 	adsp->va_cfgreg = devm_ioremap_resource(dev, mmio);
156 	if (IS_ERR(adsp->va_cfgreg))
157 		return PTR_ERR(adsp->va_cfgreg);
158 
159 	adsp->pa_cfgreg = (phys_addr_t)mmio->start;
160 	adsp->cfgregsize = resource_size(mmio);
161 
162 	dev_dbg(dev, "cfgreg pbase=%pa size=%#x\n", &adsp->pa_cfgreg, adsp->cfgregsize);
163 
164 	mmio = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sram");
165 	if (!mmio) {
166 		dev_err(dev, "no SRAM resource\n");
167 		return -ENXIO;
168 	}
169 
170 	adsp->pa_sram = (phys_addr_t)mmio->start;
171 	adsp->sramsize = resource_size(mmio);
172 
173 	dev_dbg(dev, "sram pbase=%pa size=%#x\n", &adsp->pa_sram, adsp->sramsize);
174 
175 	mmio = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sec");
176 	if (!mmio) {
177 		dev_err(dev, "no SEC register resource\n");
178 		return -ENXIO;
179 	}
180 
181 	adsp->va_secreg = devm_ioremap_resource(dev, mmio);
182 	if (IS_ERR(adsp->va_secreg))
183 		return PTR_ERR(adsp->va_secreg);
184 
185 	adsp->pa_secreg = (phys_addr_t)mmio->start;
186 	adsp->secregsize = resource_size(mmio);
187 
188 	dev_dbg(dev, "secreg pbase=%pa size=%#x\n", &adsp->pa_secreg, adsp->secregsize);
189 
190 	mmio = platform_get_resource_byname(pdev, IORESOURCE_MEM, "bus");
191 	if (!mmio) {
192 		dev_err(dev, "no BUS register resource\n");
193 		return -ENXIO;
194 	}
195 
196 	adsp->va_busreg = devm_ioremap_resource(dev, mmio);
197 	if (IS_ERR(adsp->va_busreg))
198 		return PTR_ERR(adsp->va_busreg);
199 
200 	adsp->pa_busreg = (phys_addr_t)mmio->start;
201 	adsp->busregsize = resource_size(mmio);
202 
203 	dev_dbg(dev, "busreg pbase=%pa size=%#x\n", &adsp->pa_busreg, adsp->busregsize);
204 
205 	return 0;
206 }
207 
208 static void adsp_sram_power_on(struct snd_sof_dev *sdev)
209 {
210 	snd_sof_dsp_update_bits(sdev, DSP_BUSREG_BAR, ADSP_SRAM_POOL_CON,
211 				DSP_SRAM_POOL_PD_MASK, 0);
212 }
213 
214 static void adsp_sram_power_off(struct snd_sof_dev *sdev)
215 {
216 	snd_sof_dsp_update_bits(sdev, DSP_BUSREG_BAR, ADSP_SRAM_POOL_CON,
217 				DSP_SRAM_POOL_PD_MASK, DSP_SRAM_POOL_PD_MASK);
218 }
219 
220 /*  Init the basic DSP DRAM address */
221 static int adsp_memory_remap_init(struct snd_sof_dev *sdev, struct mtk_adsp_chip_info *adsp)
222 {
223 	u32 offset;
224 
225 	offset = adsp->pa_dram - DRAM_PHYS_BASE_FROM_DSP_VIEW;
226 	adsp->dram_offset = offset;
227 	offset >>= DRAM_REMAP_SHIFT;
228 
229 	dev_dbg(sdev->dev, "adsp->pa_dram %pa, offset %#x\n", &adsp->pa_dram, offset);
230 
231 	snd_sof_dsp_write(sdev, DSP_BUSREG_BAR, DSP_C0_EMI_MAP_ADDR, offset);
232 	snd_sof_dsp_write(sdev, DSP_BUSREG_BAR, DSP_C0_DMAEMI_MAP_ADDR, offset);
233 
234 	if (offset != snd_sof_dsp_read(sdev, DSP_BUSREG_BAR, DSP_C0_EMI_MAP_ADDR) ||
235 	    offset != snd_sof_dsp_read(sdev, DSP_BUSREG_BAR, DSP_C0_DMAEMI_MAP_ADDR)) {
236 		dev_err(sdev->dev, "emi remap fail\n");
237 		return -EIO;
238 	}
239 
240 	return 0;
241 }
242 
243 static int adsp_shared_base_ioremap(struct platform_device *pdev, void *data)
244 {
245 	struct device *dev = &pdev->dev;
246 	struct mtk_adsp_chip_info *adsp = data;
247 	u32 shared_size;
248 
249 	/* remap shared-dram base to be non-cachable */
250 	shared_size = TOTAL_SIZE_SHARED_DRAM_FROM_TAIL;
251 	adsp->pa_shared_dram = adsp->pa_dram + adsp->dramsize - shared_size;
252 	if (adsp->va_dram) {
253 		adsp->shared_dram = adsp->va_dram + DSP_DRAM_SIZE - shared_size;
254 	} else {
255 		adsp->shared_dram = devm_ioremap(dev, adsp->pa_shared_dram,
256 						 shared_size);
257 		if (!adsp->shared_dram) {
258 			dev_err(dev, "ioremap failed for shared DRAM\n");
259 			return -ENOMEM;
260 		}
261 	}
262 	dev_dbg(dev, "shared-dram vbase=%p, phy addr :%pa, size=%#x\n",
263 		adsp->shared_dram, &adsp->pa_shared_dram, shared_size);
264 
265 	return 0;
266 }
267 
268 static int mt8186_run(struct snd_sof_dev *sdev)
269 {
270 	u32 adsp_bootup_addr;
271 
272 	adsp_bootup_addr = SRAM_PHYS_BASE_FROM_DSP_VIEW;
273 	dev_dbg(sdev->dev, "HIFIxDSP boot from base : 0x%08X\n", adsp_bootup_addr);
274 	mt8186_sof_hifixdsp_boot_sequence(sdev, adsp_bootup_addr);
275 
276 	return 0;
277 }
278 
279 static int mt8186_dsp_probe(struct snd_sof_dev *sdev)
280 {
281 	struct platform_device *pdev = container_of(sdev->dev, struct platform_device, dev);
282 	struct adsp_priv *priv;
283 	int ret;
284 
285 	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
286 	if (!priv)
287 		return -ENOMEM;
288 
289 	sdev->pdata->hw_pdata = priv;
290 	priv->dev = sdev->dev;
291 	priv->sdev = sdev;
292 
293 	priv->adsp = devm_kzalloc(&pdev->dev, sizeof(struct mtk_adsp_chip_info), GFP_KERNEL);
294 	if (!priv->adsp)
295 		return -ENOMEM;
296 
297 	ret = platform_parse_resource(pdev, priv->adsp);
298 	if (ret)
299 		return ret;
300 
301 	sdev->bar[SOF_FW_BLK_TYPE_IRAM] = devm_ioremap(sdev->dev,
302 						       priv->adsp->pa_sram,
303 						       priv->adsp->sramsize);
304 	if (!sdev->bar[SOF_FW_BLK_TYPE_IRAM]) {
305 		dev_err(sdev->dev, "failed to ioremap base %pa size %#x\n",
306 			&priv->adsp->pa_sram, priv->adsp->sramsize);
307 		return -ENOMEM;
308 	}
309 
310 	sdev->bar[SOF_FW_BLK_TYPE_SRAM] = devm_ioremap_wc(sdev->dev,
311 							  priv->adsp->pa_dram,
312 							  priv->adsp->dramsize);
313 	if (!sdev->bar[SOF_FW_BLK_TYPE_SRAM]) {
314 		dev_err(sdev->dev, "failed to ioremap base %pa size %#x\n",
315 			&priv->adsp->pa_dram, priv->adsp->dramsize);
316 		return -ENOMEM;
317 	}
318 
319 	priv->adsp->va_dram = sdev->bar[SOF_FW_BLK_TYPE_SRAM];
320 
321 	ret = adsp_shared_base_ioremap(pdev, priv->adsp);
322 	if (ret) {
323 		dev_err(sdev->dev, "adsp_shared_base_ioremap fail!\n");
324 		return ret;
325 	}
326 
327 	sdev->bar[DSP_REG_BAR] = priv->adsp->va_cfgreg;
328 	sdev->bar[DSP_SECREG_BAR] = priv->adsp->va_secreg;
329 	sdev->bar[DSP_BUSREG_BAR] = priv->adsp->va_busreg;
330 
331 	sdev->mmio_bar = SOF_FW_BLK_TYPE_SRAM;
332 	sdev->mailbox_bar = SOF_FW_BLK_TYPE_SRAM;
333 
334 	/* set default mailbox offset for FW ready message */
335 	sdev->dsp_box.offset = mt8186_get_mailbox_offset(sdev);
336 
337 	ret = adsp_memory_remap_init(sdev, priv->adsp);
338 	if (ret) {
339 		dev_err(sdev->dev, "adsp_memory_remap_init fail!\n");
340 		return ret;
341 	}
342 
343 	/* enable adsp clock before touching registers */
344 	ret = mt8186_adsp_init_clock(sdev);
345 	if (ret) {
346 		dev_err(sdev->dev, "mt8186_adsp_init_clock failed\n");
347 		return ret;
348 	}
349 
350 	ret = mt8186_adsp_clock_on(sdev);
351 	if (ret) {
352 		dev_err(sdev->dev, "mt8186_adsp_clock_on fail!\n");
353 		return ret;
354 	}
355 
356 	adsp_sram_power_on(sdev);
357 
358 	priv->ipc_dev = platform_device_register_data(&pdev->dev, "mtk-adsp-ipc",
359 						      PLATFORM_DEVID_NONE,
360 						      pdev, sizeof(*pdev));
361 	if (IS_ERR(priv->ipc_dev)) {
362 		ret = PTR_ERR(priv->ipc_dev);
363 		dev_err(sdev->dev, "failed to create mtk-adsp-ipc device\n");
364 		goto err_adsp_off;
365 	}
366 
367 	priv->dsp_ipc = dev_get_drvdata(&priv->ipc_dev->dev);
368 	if (!priv->dsp_ipc) {
369 		ret = -EPROBE_DEFER;
370 		dev_err(sdev->dev, "failed to get drvdata\n");
371 		goto exit_pdev_unregister;
372 	}
373 
374 	mtk_adsp_ipc_set_data(priv->dsp_ipc, priv);
375 	priv->dsp_ipc->ops = &dsp_ops;
376 
377 	return 0;
378 
379 exit_pdev_unregister:
380 	platform_device_unregister(priv->ipc_dev);
381 err_adsp_off:
382 	adsp_sram_power_off(sdev);
383 	mt8186_adsp_clock_off(sdev);
384 
385 	return ret;
386 }
387 
388 static int mt8186_dsp_remove(struct snd_sof_dev *sdev)
389 {
390 	struct adsp_priv *priv = sdev->pdata->hw_pdata;
391 
392 	platform_device_unregister(priv->ipc_dev);
393 	mt8186_sof_hifixdsp_shutdown(sdev);
394 	adsp_sram_power_off(sdev);
395 	mt8186_adsp_clock_off(sdev);
396 
397 	return 0;
398 }
399 
400 static int mt8186_dsp_shutdown(struct snd_sof_dev *sdev)
401 {
402 	return snd_sof_suspend(sdev->dev);
403 }
404 
405 static int mt8186_dsp_suspend(struct snd_sof_dev *sdev, u32 target_state)
406 {
407 	mt8186_sof_hifixdsp_shutdown(sdev);
408 	adsp_sram_power_off(sdev);
409 	mt8186_adsp_clock_off(sdev);
410 
411 	return 0;
412 }
413 
414 static int mt8186_dsp_resume(struct snd_sof_dev *sdev)
415 {
416 	int ret;
417 
418 	ret = mt8186_adsp_clock_on(sdev);
419 	if (ret) {
420 		dev_err(sdev->dev, "mt8186_adsp_clock_on fail!\n");
421 		return ret;
422 	}
423 
424 	adsp_sram_power_on(sdev);
425 
426 	return ret;
427 }
428 
429 /* on mt8186 there is 1 to 1 match between type and BAR idx */
430 static int mt8186_get_bar_index(struct snd_sof_dev *sdev, u32 type)
431 {
432 	return type;
433 }
434 
435 static int mt8186_pcm_hw_params(struct snd_sof_dev *sdev,
436 				struct snd_pcm_substream *substream,
437 				struct snd_pcm_hw_params *params,
438 				struct snd_sof_platform_stream_params *platform_params)
439 {
440 	platform_params->cont_update_posn = 1;
441 
442 	return 0;
443 }
444 
445 static snd_pcm_uframes_t mt8186_pcm_pointer(struct snd_sof_dev *sdev,
446 					    struct snd_pcm_substream *substream)
447 {
448 	int ret;
449 	snd_pcm_uframes_t pos;
450 	struct snd_sof_pcm *spcm;
451 	struct sof_ipc_stream_posn posn;
452 	struct snd_sof_pcm_stream *stream;
453 	struct snd_soc_component *scomp = sdev->component;
454 	struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
455 
456 	spcm = snd_sof_find_spcm_dai(scomp, rtd);
457 	if (!spcm) {
458 		dev_warn_ratelimited(sdev->dev, "warn: can't find PCM with DAI ID %d\n",
459 				     rtd->dai_link->id);
460 		return 0;
461 	}
462 
463 	stream = &spcm->stream[substream->stream];
464 	ret = snd_sof_ipc_msg_data(sdev, stream, &posn, sizeof(posn));
465 	if (ret < 0) {
466 		dev_warn(sdev->dev, "failed to read stream position: %d\n", ret);
467 		return 0;
468 	}
469 
470 	memcpy(&stream->posn, &posn, sizeof(posn));
471 	pos = spcm->stream[substream->stream].posn.host_posn;
472 	pos = bytes_to_frames(substream->runtime, pos);
473 
474 	return pos;
475 }
476 
477 static void mt8186_adsp_dump(struct snd_sof_dev *sdev, u32 flags)
478 {
479 	u32 dbg_pc, dbg_data, dbg_inst, dbg_ls0stat, dbg_status, faultinfo;
480 
481 	/* dump debug registers */
482 	dbg_pc = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGPC);
483 	dbg_data = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGDATA);
484 	dbg_inst = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGINST);
485 	dbg_ls0stat = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGLS0STAT);
486 	dbg_status = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGSTATUS);
487 	faultinfo = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PFAULTINFO);
488 
489 	dev_info(sdev->dev, "adsp dump : pc %#x, data %#x, dbg_inst %#x,",
490 		 dbg_pc, dbg_data, dbg_inst);
491 	dev_info(sdev->dev, "ls0stat %#x, status %#x, faultinfo %#x",
492 		 dbg_ls0stat, dbg_status, faultinfo);
493 
494 	mtk_adsp_dump(sdev, flags);
495 }
496 
497 static struct snd_soc_dai_driver mt8186_dai[] = {
498 {
499 	.name = "SOF_DL1",
500 	.playback = {
501 		.channels_min = 1,
502 		.channels_max = 2,
503 	},
504 },
505 {
506 	.name = "SOF_DL2",
507 	.playback = {
508 		.channels_min = 1,
509 		.channels_max = 2,
510 	},
511 },
512 {
513 	.name = "SOF_UL1",
514 	.capture = {
515 		.channels_min = 1,
516 		.channels_max = 2,
517 	},
518 },
519 {
520 	.name = "SOF_UL2",
521 	.capture = {
522 		.channels_min = 1,
523 		.channels_max = 2,
524 	},
525 },
526 };
527 
528 /* mt8186 ops */
529 static struct snd_sof_dsp_ops sof_mt8186_ops = {
530 	/* probe and remove */
531 	.probe		= mt8186_dsp_probe,
532 	.remove		= mt8186_dsp_remove,
533 	.shutdown	= mt8186_dsp_shutdown,
534 
535 	/* DSP core boot */
536 	.run		= mt8186_run,
537 
538 	/* Block IO */
539 	.block_read	= sof_block_read,
540 	.block_write	= sof_block_write,
541 
542 	/* Mailbox IO */
543 	.mailbox_read	= sof_mailbox_read,
544 	.mailbox_write	= sof_mailbox_write,
545 
546 	/* Register IO */
547 	.write		= sof_io_write,
548 	.read		= sof_io_read,
549 	.write64	= sof_io_write64,
550 	.read64		= sof_io_read64,
551 
552 	/* ipc */
553 	.send_msg		= mt8186_send_msg,
554 	.get_mailbox_offset	= mt8186_get_mailbox_offset,
555 	.get_window_offset	= mt8186_get_window_offset,
556 	.ipc_msg_data		= sof_ipc_msg_data,
557 	.set_stream_data_offset = sof_set_stream_data_offset,
558 
559 	/* misc */
560 	.get_bar_index	= mt8186_get_bar_index,
561 
562 	/* stream callbacks */
563 	.pcm_open	= sof_stream_pcm_open,
564 	.pcm_hw_params	= mt8186_pcm_hw_params,
565 	.pcm_pointer	= mt8186_pcm_pointer,
566 	.pcm_close	= sof_stream_pcm_close,
567 
568 	/* firmware loading */
569 	.load_firmware	= snd_sof_load_firmware_memcpy,
570 
571 	/* Firmware ops */
572 	.dsp_arch_ops = &sof_xtensa_arch_ops,
573 
574 	/* DAI drivers */
575 	.drv		= mt8186_dai,
576 	.num_drv	= ARRAY_SIZE(mt8186_dai),
577 
578 	/* Debug information */
579 	.dbg_dump = mt8186_adsp_dump,
580 	.debugfs_add_region_item = snd_sof_debugfs_add_region_item_iomem,
581 
582 	/* PM */
583 	.suspend	= mt8186_dsp_suspend,
584 	.resume		= mt8186_dsp_resume,
585 
586 	/* ALSA HW info flags */
587 	.hw_info =	SNDRV_PCM_INFO_MMAP |
588 			SNDRV_PCM_INFO_MMAP_VALID |
589 			SNDRV_PCM_INFO_INTERLEAVED |
590 			SNDRV_PCM_INFO_PAUSE |
591 			SNDRV_PCM_INFO_NO_PERIOD_WAKEUP,
592 };
593 
594 static struct snd_sof_of_mach sof_mt8186_machs[] = {
595 	{
596 		.compatible = "mediatek,mt8186",
597 		.sof_tplg_filename = "sof-mt8186.tplg",
598 	},
599 	{}
600 };
601 
602 static const struct sof_dev_desc sof_of_mt8186_desc = {
603 	.of_machines = sof_mt8186_machs,
604 	.ipc_supported_mask	= BIT(SOF_IPC),
605 	.ipc_default		= SOF_IPC,
606 	.default_fw_path = {
607 		[SOF_IPC] = "mediatek/sof",
608 	},
609 	.default_tplg_path = {
610 		[SOF_IPC] = "mediatek/sof-tplg",
611 	},
612 	.default_fw_filename = {
613 		[SOF_IPC] = "sof-mt8186.ri",
614 	},
615 	.nocodec_tplg_filename = "sof-mt8186-nocodec.tplg",
616 	.ops = &sof_mt8186_ops,
617 };
618 
619 /*
620  * DL2, DL3, UL4, UL5 are registered as SOF FE, so creating the corresponding
621  * SOF BE to complete the pipeline.
622  */
623 static struct snd_soc_dai_driver mt8188_dai[] = {
624 {
625 	.name = "SOF_DL2",
626 	.playback = {
627 		.channels_min = 1,
628 		.channels_max = 2,
629 	},
630 },
631 {
632 	.name = "SOF_DL3",
633 	.playback = {
634 		.channels_min = 1,
635 		.channels_max = 2,
636 	},
637 },
638 {
639 	.name = "SOF_UL4",
640 	.capture = {
641 		.channels_min = 1,
642 		.channels_max = 2,
643 	},
644 },
645 {
646 	.name = "SOF_UL5",
647 	.capture = {
648 		.channels_min = 1,
649 		.channels_max = 2,
650 	},
651 },
652 };
653 
654 /* mt8188 ops */
655 static struct snd_sof_dsp_ops sof_mt8188_ops;
656 
657 static int sof_mt8188_ops_init(struct snd_sof_dev *sdev)
658 {
659 	/* common defaults */
660 	memcpy(&sof_mt8188_ops, &sof_mt8186_ops, sizeof(sof_mt8188_ops));
661 
662 	sof_mt8188_ops.drv = mt8188_dai;
663 	sof_mt8188_ops.num_drv = ARRAY_SIZE(mt8188_dai);
664 
665 	return 0;
666 }
667 
668 static struct snd_sof_of_mach sof_mt8188_machs[] = {
669 	{
670 		.compatible = "mediatek,mt8188",
671 		.sof_tplg_filename = "sof-mt8188.tplg",
672 	},
673 	{}
674 };
675 
676 static const struct sof_dev_desc sof_of_mt8188_desc = {
677 	.of_machines = sof_mt8188_machs,
678 	.ipc_supported_mask	= BIT(SOF_IPC),
679 	.ipc_default		= SOF_IPC,
680 	.default_fw_path = {
681 		[SOF_IPC] = "mediatek/sof",
682 	},
683 	.default_tplg_path = {
684 		[SOF_IPC] = "mediatek/sof-tplg",
685 	},
686 	.default_fw_filename = {
687 		[SOF_IPC] = "sof-mt8188.ri",
688 	},
689 	.nocodec_tplg_filename = "sof-mt8188-nocodec.tplg",
690 	.ops = &sof_mt8188_ops,
691 	.ops_init = sof_mt8188_ops_init,
692 };
693 
694 static const struct of_device_id sof_of_mt8186_ids[] = {
695 	{ .compatible = "mediatek,mt8186-dsp", .data = &sof_of_mt8186_desc},
696 	{ .compatible = "mediatek,mt8188-dsp", .data = &sof_of_mt8188_desc},
697 	{ }
698 };
699 MODULE_DEVICE_TABLE(of, sof_of_mt8186_ids);
700 
701 /* DT driver definition */
702 static struct platform_driver snd_sof_of_mt8186_driver = {
703 	.probe = sof_of_probe,
704 	.remove = sof_of_remove,
705 	.shutdown = sof_of_shutdown,
706 	.driver = {
707 	.name = "sof-audio-of-mt8186",
708 		.pm = &sof_of_pm,
709 		.of_match_table = sof_of_mt8186_ids,
710 	},
711 };
712 module_platform_driver(snd_sof_of_mt8186_driver);
713 
714 MODULE_IMPORT_NS(SND_SOC_SOF_XTENSA);
715 MODULE_IMPORT_NS(SND_SOC_SOF_MTK_COMMON);
716 MODULE_LICENSE("Dual BSD/GPL");
717