11f0214a8STinghan Shen // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 21f0214a8STinghan Shen // 31f0214a8STinghan Shen // Copyright(c) 2022 Mediatek Inc. All rights reserved. 41f0214a8STinghan Shen // 51f0214a8STinghan Shen // Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com> 61f0214a8STinghan Shen // Tinghan Shen <tinghan.shen@mediatek.com> 71f0214a8STinghan Shen 81f0214a8STinghan Shen /* 91f0214a8STinghan Shen * Hardware interface for audio DSP on mt8186 101f0214a8STinghan Shen */ 111f0214a8STinghan Shen 121f0214a8STinghan Shen #include <linux/delay.h> 131f0214a8STinghan Shen #include <linux/firmware.h> 141f0214a8STinghan Shen #include <linux/io.h> 151f0214a8STinghan Shen #include <linux/of_address.h> 161f0214a8STinghan Shen #include <linux/of_irq.h> 171f0214a8STinghan Shen #include <linux/of_platform.h> 181f0214a8STinghan Shen #include <linux/of_reserved_mem.h> 191f0214a8STinghan Shen #include <linux/module.h> 201f0214a8STinghan Shen 211f0214a8STinghan Shen #include <sound/sof.h> 221f0214a8STinghan Shen #include <sound/sof/xtensa.h> 231f0214a8STinghan Shen #include "../../ops.h" 241f0214a8STinghan Shen #include "../../sof-of-dev.h" 251f0214a8STinghan Shen #include "../../sof-audio.h" 261f0214a8STinghan Shen #include "../adsp_helper.h" 271f0214a8STinghan Shen #include "mt8186.h" 28210b3ab9STinghan Shen #include "mt8186-clk.h" 291f0214a8STinghan Shen 30e0100bfdSTinghan Shen static int mt8186_get_mailbox_offset(struct snd_sof_dev *sdev) 31e0100bfdSTinghan Shen { 32e0100bfdSTinghan Shen return MBOX_OFFSET; 33e0100bfdSTinghan Shen } 34e0100bfdSTinghan Shen 35e0100bfdSTinghan Shen static int mt8186_get_window_offset(struct snd_sof_dev *sdev, u32 id) 36e0100bfdSTinghan Shen { 37e0100bfdSTinghan Shen return MBOX_OFFSET; 38e0100bfdSTinghan Shen } 39e0100bfdSTinghan Shen 40e0100bfdSTinghan Shen static int mt8186_send_msg(struct snd_sof_dev *sdev, 41e0100bfdSTinghan Shen struct snd_sof_ipc_msg *msg) 42e0100bfdSTinghan Shen { 43e0100bfdSTinghan Shen struct adsp_priv *priv = sdev->pdata->hw_pdata; 44e0100bfdSTinghan Shen 45e0100bfdSTinghan Shen sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data, 46e0100bfdSTinghan Shen msg->msg_size); 47e0100bfdSTinghan Shen 48e0100bfdSTinghan Shen return mtk_adsp_ipc_send(priv->dsp_ipc, MTK_ADSP_IPC_REQ, MTK_ADSP_IPC_OP_REQ); 49e0100bfdSTinghan Shen } 50e0100bfdSTinghan Shen 51e0100bfdSTinghan Shen static void mt8186_dsp_handle_reply(struct mtk_adsp_ipc *ipc) 52e0100bfdSTinghan Shen { 53e0100bfdSTinghan Shen struct adsp_priv *priv = mtk_adsp_ipc_get_data(ipc); 54e0100bfdSTinghan Shen unsigned long flags; 55e0100bfdSTinghan Shen 56e0100bfdSTinghan Shen spin_lock_irqsave(&priv->sdev->ipc_lock, flags); 57*709f34b4SAngeloGioacchino Del Regno snd_sof_ipc_process_reply(priv->sdev, 0); 58e0100bfdSTinghan Shen spin_unlock_irqrestore(&priv->sdev->ipc_lock, flags); 59e0100bfdSTinghan Shen } 60e0100bfdSTinghan Shen 61e0100bfdSTinghan Shen static void mt8186_dsp_handle_request(struct mtk_adsp_ipc *ipc) 62e0100bfdSTinghan Shen { 63e0100bfdSTinghan Shen struct adsp_priv *priv = mtk_adsp_ipc_get_data(ipc); 64e0100bfdSTinghan Shen u32 p; /* panic code */ 65e0100bfdSTinghan Shen int ret; 66e0100bfdSTinghan Shen 67e0100bfdSTinghan Shen /* Read the message from the debug box. */ 68e0100bfdSTinghan Shen sof_mailbox_read(priv->sdev, priv->sdev->debug_box.offset + 4, 69e0100bfdSTinghan Shen &p, sizeof(p)); 70e0100bfdSTinghan Shen 71e0100bfdSTinghan Shen /* Check to see if the message is a panic code 0x0dead*** */ 72e0100bfdSTinghan Shen if ((p & SOF_IPC_PANIC_MAGIC_MASK) == SOF_IPC_PANIC_MAGIC) { 73e0100bfdSTinghan Shen snd_sof_dsp_panic(priv->sdev, p, true); 74e0100bfdSTinghan Shen } else { 75e0100bfdSTinghan Shen snd_sof_ipc_msgs_rx(priv->sdev); 76e0100bfdSTinghan Shen 77e0100bfdSTinghan Shen /* tell DSP cmd is done */ 78e0100bfdSTinghan Shen ret = mtk_adsp_ipc_send(priv->dsp_ipc, MTK_ADSP_IPC_RSP, MTK_ADSP_IPC_OP_RSP); 79e0100bfdSTinghan Shen if (ret) 80e0100bfdSTinghan Shen dev_err(priv->dev, "request send ipc failed"); 81e0100bfdSTinghan Shen } 82e0100bfdSTinghan Shen } 83e0100bfdSTinghan Shen 84e0100bfdSTinghan Shen static struct mtk_adsp_ipc_ops dsp_ops = { 85e0100bfdSTinghan Shen .handle_reply = mt8186_dsp_handle_reply, 86e0100bfdSTinghan Shen .handle_request = mt8186_dsp_handle_request, 87e0100bfdSTinghan Shen }; 88e0100bfdSTinghan Shen 891f0214a8STinghan Shen static int platform_parse_resource(struct platform_device *pdev, void *data) 901f0214a8STinghan Shen { 911f0214a8STinghan Shen struct resource *mmio; 921f0214a8STinghan Shen struct resource res; 931f0214a8STinghan Shen struct device_node *mem_region; 941f0214a8STinghan Shen struct device *dev = &pdev->dev; 951f0214a8STinghan Shen struct mtk_adsp_chip_info *adsp = data; 961f0214a8STinghan Shen int ret; 971f0214a8STinghan Shen 981f0214a8STinghan Shen mem_region = of_parse_phandle(dev->of_node, "memory-region", 0); 991f0214a8STinghan Shen if (!mem_region) { 1001f0214a8STinghan Shen dev_err(dev, "no dma memory-region phandle\n"); 1011f0214a8STinghan Shen return -ENODEV; 1021f0214a8STinghan Shen } 1031f0214a8STinghan Shen 1041f0214a8STinghan Shen ret = of_address_to_resource(mem_region, 0, &res); 1051f0214a8STinghan Shen of_node_put(mem_region); 1061f0214a8STinghan Shen if (ret) { 1071f0214a8STinghan Shen dev_err(dev, "of_address_to_resource dma failed\n"); 1081f0214a8STinghan Shen return ret; 1091f0214a8STinghan Shen } 1101f0214a8STinghan Shen 1111f0214a8STinghan Shen dev_dbg(dev, "DMA %pR\n", &res); 1121f0214a8STinghan Shen 1131f0214a8STinghan Shen ret = of_reserved_mem_device_init(dev); 1141f0214a8STinghan Shen if (ret) { 1151f0214a8STinghan Shen dev_err(dev, "of_reserved_mem_device_init failed\n"); 1161f0214a8STinghan Shen return ret; 1171f0214a8STinghan Shen } 1181f0214a8STinghan Shen 1191f0214a8STinghan Shen mem_region = of_parse_phandle(dev->of_node, "memory-region", 1); 1201f0214a8STinghan Shen if (!mem_region) { 1211f0214a8STinghan Shen dev_err(dev, "no memory-region sysmem phandle\n"); 1221f0214a8STinghan Shen return -ENODEV; 1231f0214a8STinghan Shen } 1241f0214a8STinghan Shen 1251f0214a8STinghan Shen ret = of_address_to_resource(mem_region, 0, &res); 1261f0214a8STinghan Shen of_node_put(mem_region); 1271f0214a8STinghan Shen if (ret) { 1281f0214a8STinghan Shen dev_err(dev, "of_address_to_resource sysmem failed\n"); 1291f0214a8STinghan Shen return ret; 1301f0214a8STinghan Shen } 1311f0214a8STinghan Shen 1321f0214a8STinghan Shen adsp->pa_dram = (phys_addr_t)res.start; 1331f0214a8STinghan Shen if (adsp->pa_dram & DRAM_REMAP_MASK) { 1341f0214a8STinghan Shen dev_err(dev, "adsp memory(%#x) is not 4K-aligned\n", 1351f0214a8STinghan Shen (u32)adsp->pa_dram); 1361f0214a8STinghan Shen return -EINVAL; 1371f0214a8STinghan Shen } 1381f0214a8STinghan Shen 1391f0214a8STinghan Shen adsp->dramsize = resource_size(&res); 1401f0214a8STinghan Shen if (adsp->dramsize < TOTAL_SIZE_SHARED_DRAM_FROM_TAIL) { 1411f0214a8STinghan Shen dev_err(dev, "adsp memory(%#x) is not enough for share\n", 1421f0214a8STinghan Shen adsp->dramsize); 1431f0214a8STinghan Shen return -EINVAL; 1441f0214a8STinghan Shen } 1451f0214a8STinghan Shen 1461f0214a8STinghan Shen dev_dbg(dev, "dram pbase=%pa size=%#x\n", &adsp->pa_dram, adsp->dramsize); 1471f0214a8STinghan Shen 1481f0214a8STinghan Shen mmio = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg"); 1491f0214a8STinghan Shen if (!mmio) { 1501f0214a8STinghan Shen dev_err(dev, "no ADSP-CFG register resource\n"); 1511f0214a8STinghan Shen return -ENXIO; 1521f0214a8STinghan Shen } 1531f0214a8STinghan Shen 1541f0214a8STinghan Shen adsp->va_cfgreg = devm_ioremap_resource(dev, mmio); 1551f0214a8STinghan Shen if (IS_ERR(adsp->va_cfgreg)) 1561f0214a8STinghan Shen return PTR_ERR(adsp->va_cfgreg); 1571f0214a8STinghan Shen 1581f0214a8STinghan Shen adsp->pa_cfgreg = (phys_addr_t)mmio->start; 1591f0214a8STinghan Shen adsp->cfgregsize = resource_size(mmio); 1601f0214a8STinghan Shen 1611f0214a8STinghan Shen dev_dbg(dev, "cfgreg pbase=%pa size=%#x\n", &adsp->pa_cfgreg, adsp->cfgregsize); 1621f0214a8STinghan Shen 1631f0214a8STinghan Shen mmio = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sram"); 1641f0214a8STinghan Shen if (!mmio) { 1651f0214a8STinghan Shen dev_err(dev, "no SRAM resource\n"); 1661f0214a8STinghan Shen return -ENXIO; 1671f0214a8STinghan Shen } 1681f0214a8STinghan Shen 1691f0214a8STinghan Shen adsp->pa_sram = (phys_addr_t)mmio->start; 1701f0214a8STinghan Shen adsp->sramsize = resource_size(mmio); 1711f0214a8STinghan Shen 1721f0214a8STinghan Shen dev_dbg(dev, "sram pbase=%pa size=%#x\n", &adsp->pa_sram, adsp->sramsize); 1731f0214a8STinghan Shen 1741f0214a8STinghan Shen mmio = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sec"); 1751f0214a8STinghan Shen if (!mmio) { 1761f0214a8STinghan Shen dev_err(dev, "no SEC register resource\n"); 1771f0214a8STinghan Shen return -ENXIO; 1781f0214a8STinghan Shen } 1791f0214a8STinghan Shen 1801f0214a8STinghan Shen adsp->va_secreg = devm_ioremap_resource(dev, mmio); 1811f0214a8STinghan Shen if (IS_ERR(adsp->va_secreg)) 1821f0214a8STinghan Shen return PTR_ERR(adsp->va_secreg); 1831f0214a8STinghan Shen 1841f0214a8STinghan Shen adsp->pa_secreg = (phys_addr_t)mmio->start; 1851f0214a8STinghan Shen adsp->secregsize = resource_size(mmio); 1861f0214a8STinghan Shen 1871f0214a8STinghan Shen dev_dbg(dev, "secreg pbase=%pa size=%#x\n", &adsp->pa_secreg, adsp->secregsize); 1881f0214a8STinghan Shen 1891f0214a8STinghan Shen mmio = platform_get_resource_byname(pdev, IORESOURCE_MEM, "bus"); 1901f0214a8STinghan Shen if (!mmio) { 1911f0214a8STinghan Shen dev_err(dev, "no BUS register resource\n"); 1921f0214a8STinghan Shen return -ENXIO; 1931f0214a8STinghan Shen } 1941f0214a8STinghan Shen 1951f0214a8STinghan Shen adsp->va_busreg = devm_ioremap_resource(dev, mmio); 1961f0214a8STinghan Shen if (IS_ERR(adsp->va_busreg)) 1971f0214a8STinghan Shen return PTR_ERR(adsp->va_busreg); 1981f0214a8STinghan Shen 1991f0214a8STinghan Shen adsp->pa_busreg = (phys_addr_t)mmio->start; 2001f0214a8STinghan Shen adsp->busregsize = resource_size(mmio); 2011f0214a8STinghan Shen 2021f0214a8STinghan Shen dev_dbg(dev, "busreg pbase=%pa size=%#x\n", &adsp->pa_busreg, adsp->busregsize); 2031f0214a8STinghan Shen 2041f0214a8STinghan Shen return 0; 2051f0214a8STinghan Shen } 2061f0214a8STinghan Shen 2071f0214a8STinghan Shen static void adsp_sram_power_on(struct snd_sof_dev *sdev) 2081f0214a8STinghan Shen { 2091f0214a8STinghan Shen snd_sof_dsp_update_bits(sdev, DSP_BUSREG_BAR, ADSP_SRAM_POOL_CON, 2101f0214a8STinghan Shen DSP_SRAM_POOL_PD_MASK, 0); 2111f0214a8STinghan Shen } 2121f0214a8STinghan Shen 2131f0214a8STinghan Shen static void adsp_sram_power_off(struct snd_sof_dev *sdev) 2141f0214a8STinghan Shen { 2151f0214a8STinghan Shen snd_sof_dsp_update_bits(sdev, DSP_BUSREG_BAR, ADSP_SRAM_POOL_CON, 2161f0214a8STinghan Shen DSP_SRAM_POOL_PD_MASK, DSP_SRAM_POOL_PD_MASK); 2171f0214a8STinghan Shen } 2181f0214a8STinghan Shen 2191f0214a8STinghan Shen /* Init the basic DSP DRAM address */ 2201f0214a8STinghan Shen static int adsp_memory_remap_init(struct snd_sof_dev *sdev, struct mtk_adsp_chip_info *adsp) 2211f0214a8STinghan Shen { 2221f0214a8STinghan Shen u32 offset; 2231f0214a8STinghan Shen 2241f0214a8STinghan Shen offset = adsp->pa_dram - DRAM_PHYS_BASE_FROM_DSP_VIEW; 2251f0214a8STinghan Shen adsp->dram_offset = offset; 2261f0214a8STinghan Shen offset >>= DRAM_REMAP_SHIFT; 2271f0214a8STinghan Shen 2281f0214a8STinghan Shen dev_dbg(sdev->dev, "adsp->pa_dram %pa, offset %#x\n", &adsp->pa_dram, offset); 2291f0214a8STinghan Shen 2301f0214a8STinghan Shen snd_sof_dsp_write(sdev, DSP_BUSREG_BAR, DSP_C0_EMI_MAP_ADDR, offset); 2311f0214a8STinghan Shen snd_sof_dsp_write(sdev, DSP_BUSREG_BAR, DSP_C0_DMAEMI_MAP_ADDR, offset); 2321f0214a8STinghan Shen 2331f0214a8STinghan Shen if (offset != snd_sof_dsp_read(sdev, DSP_BUSREG_BAR, DSP_C0_EMI_MAP_ADDR) || 2341f0214a8STinghan Shen offset != snd_sof_dsp_read(sdev, DSP_BUSREG_BAR, DSP_C0_DMAEMI_MAP_ADDR)) { 2351f0214a8STinghan Shen dev_err(sdev->dev, "emi remap fail\n"); 2361f0214a8STinghan Shen return -EIO; 2371f0214a8STinghan Shen } 2381f0214a8STinghan Shen 2391f0214a8STinghan Shen return 0; 2401f0214a8STinghan Shen } 2411f0214a8STinghan Shen 2421f0214a8STinghan Shen static int adsp_shared_base_ioremap(struct platform_device *pdev, void *data) 2431f0214a8STinghan Shen { 2441f0214a8STinghan Shen struct device *dev = &pdev->dev; 2451f0214a8STinghan Shen struct mtk_adsp_chip_info *adsp = data; 2461f0214a8STinghan Shen u32 shared_size; 2471f0214a8STinghan Shen 2481f0214a8STinghan Shen /* remap shared-dram base to be non-cachable */ 2491f0214a8STinghan Shen shared_size = TOTAL_SIZE_SHARED_DRAM_FROM_TAIL; 2501f0214a8STinghan Shen adsp->pa_shared_dram = adsp->pa_dram + adsp->dramsize - shared_size; 2511f0214a8STinghan Shen if (adsp->va_dram) { 2521f0214a8STinghan Shen adsp->shared_dram = adsp->va_dram + DSP_DRAM_SIZE - shared_size; 2531f0214a8STinghan Shen } else { 2541f0214a8STinghan Shen adsp->shared_dram = devm_ioremap(dev, adsp->pa_shared_dram, 2551f0214a8STinghan Shen shared_size); 2561f0214a8STinghan Shen if (!adsp->shared_dram) { 2571f0214a8STinghan Shen dev_err(dev, "ioremap failed for shared DRAM\n"); 2581f0214a8STinghan Shen return -ENOMEM; 2591f0214a8STinghan Shen } 2601f0214a8STinghan Shen } 2611f0214a8STinghan Shen dev_dbg(dev, "shared-dram vbase=%p, phy addr :%pa, size=%#x\n", 2621f0214a8STinghan Shen adsp->shared_dram, &adsp->pa_shared_dram, shared_size); 2631f0214a8STinghan Shen 2641f0214a8STinghan Shen return 0; 2651f0214a8STinghan Shen } 2661f0214a8STinghan Shen 267570c14dcSTinghan Shen static int mt8186_run(struct snd_sof_dev *sdev) 268570c14dcSTinghan Shen { 269570c14dcSTinghan Shen u32 adsp_bootup_addr; 270570c14dcSTinghan Shen 271570c14dcSTinghan Shen adsp_bootup_addr = SRAM_PHYS_BASE_FROM_DSP_VIEW; 272570c14dcSTinghan Shen dev_dbg(sdev->dev, "HIFIxDSP boot from base : 0x%08X\n", adsp_bootup_addr); 2739ce170dcSTinghan Shen mt8186_sof_hifixdsp_boot_sequence(sdev, adsp_bootup_addr); 274570c14dcSTinghan Shen 275570c14dcSTinghan Shen return 0; 276570c14dcSTinghan Shen } 277570c14dcSTinghan Shen 2781f0214a8STinghan Shen static int mt8186_dsp_probe(struct snd_sof_dev *sdev) 2791f0214a8STinghan Shen { 2801f0214a8STinghan Shen struct platform_device *pdev = container_of(sdev->dev, struct platform_device, dev); 2811f0214a8STinghan Shen struct adsp_priv *priv; 2821f0214a8STinghan Shen int ret; 2831f0214a8STinghan Shen 2841f0214a8STinghan Shen priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 2851f0214a8STinghan Shen if (!priv) 2861f0214a8STinghan Shen return -ENOMEM; 2871f0214a8STinghan Shen 2881f0214a8STinghan Shen sdev->pdata->hw_pdata = priv; 2891f0214a8STinghan Shen priv->dev = sdev->dev; 2901f0214a8STinghan Shen priv->sdev = sdev; 2911f0214a8STinghan Shen 2921f0214a8STinghan Shen priv->adsp = devm_kzalloc(&pdev->dev, sizeof(struct mtk_adsp_chip_info), GFP_KERNEL); 2931f0214a8STinghan Shen if (!priv->adsp) 2941f0214a8STinghan Shen return -ENOMEM; 2951f0214a8STinghan Shen 2961f0214a8STinghan Shen ret = platform_parse_resource(pdev, priv->adsp); 2971f0214a8STinghan Shen if (ret) 2981f0214a8STinghan Shen return ret; 2991f0214a8STinghan Shen 3001f0214a8STinghan Shen sdev->bar[SOF_FW_BLK_TYPE_IRAM] = devm_ioremap(sdev->dev, 3011f0214a8STinghan Shen priv->adsp->pa_sram, 3021f0214a8STinghan Shen priv->adsp->sramsize); 3031f0214a8STinghan Shen if (!sdev->bar[SOF_FW_BLK_TYPE_IRAM]) { 3041f0214a8STinghan Shen dev_err(sdev->dev, "failed to ioremap base %pa size %#x\n", 3051f0214a8STinghan Shen &priv->adsp->pa_sram, priv->adsp->sramsize); 3061f0214a8STinghan Shen return -ENOMEM; 3071f0214a8STinghan Shen } 3081f0214a8STinghan Shen 3091f0214a8STinghan Shen sdev->bar[SOF_FW_BLK_TYPE_SRAM] = devm_ioremap_wc(sdev->dev, 3101f0214a8STinghan Shen priv->adsp->pa_dram, 3111f0214a8STinghan Shen priv->adsp->dramsize); 3121f0214a8STinghan Shen if (!sdev->bar[SOF_FW_BLK_TYPE_SRAM]) { 3131f0214a8STinghan Shen dev_err(sdev->dev, "failed to ioremap base %pa size %#x\n", 3141f0214a8STinghan Shen &priv->adsp->pa_dram, priv->adsp->dramsize); 3151f0214a8STinghan Shen return -ENOMEM; 3161f0214a8STinghan Shen } 3171f0214a8STinghan Shen 3181f0214a8STinghan Shen priv->adsp->va_dram = sdev->bar[SOF_FW_BLK_TYPE_SRAM]; 3191f0214a8STinghan Shen 3201f0214a8STinghan Shen ret = adsp_shared_base_ioremap(pdev, priv->adsp); 3211f0214a8STinghan Shen if (ret) { 3221f0214a8STinghan Shen dev_err(sdev->dev, "adsp_shared_base_ioremap fail!\n"); 3231f0214a8STinghan Shen return ret; 3241f0214a8STinghan Shen } 3251f0214a8STinghan Shen 3261f0214a8STinghan Shen sdev->bar[DSP_REG_BAR] = priv->adsp->va_cfgreg; 3271f0214a8STinghan Shen sdev->bar[DSP_SECREG_BAR] = priv->adsp->va_secreg; 3281f0214a8STinghan Shen sdev->bar[DSP_BUSREG_BAR] = priv->adsp->va_busreg; 3291f0214a8STinghan Shen 3301f0214a8STinghan Shen sdev->mmio_bar = SOF_FW_BLK_TYPE_SRAM; 3311f0214a8STinghan Shen sdev->mailbox_bar = SOF_FW_BLK_TYPE_SRAM; 3321f0214a8STinghan Shen 333e0100bfdSTinghan Shen /* set default mailbox offset for FW ready message */ 334e0100bfdSTinghan Shen sdev->dsp_box.offset = mt8186_get_mailbox_offset(sdev); 335e0100bfdSTinghan Shen 3361f0214a8STinghan Shen ret = adsp_memory_remap_init(sdev, priv->adsp); 3371f0214a8STinghan Shen if (ret) { 3381f0214a8STinghan Shen dev_err(sdev->dev, "adsp_memory_remap_init fail!\n"); 3391f0214a8STinghan Shen return ret; 3401f0214a8STinghan Shen } 3411f0214a8STinghan Shen 342210b3ab9STinghan Shen /* enable adsp clock before touching registers */ 343210b3ab9STinghan Shen ret = mt8186_adsp_init_clock(sdev); 344210b3ab9STinghan Shen if (ret) { 345210b3ab9STinghan Shen dev_err(sdev->dev, "mt8186_adsp_init_clock failed\n"); 346210b3ab9STinghan Shen return ret; 347210b3ab9STinghan Shen } 348210b3ab9STinghan Shen 3499ce170dcSTinghan Shen ret = mt8186_adsp_clock_on(sdev); 350210b3ab9STinghan Shen if (ret) { 3519ce170dcSTinghan Shen dev_err(sdev->dev, "mt8186_adsp_clock_on fail!\n"); 352210b3ab9STinghan Shen return ret; 353210b3ab9STinghan Shen } 354210b3ab9STinghan Shen 3551f0214a8STinghan Shen adsp_sram_power_on(sdev); 3561f0214a8STinghan Shen 357e0100bfdSTinghan Shen priv->ipc_dev = platform_device_register_data(&pdev->dev, "mtk-adsp-ipc", 358e0100bfdSTinghan Shen PLATFORM_DEVID_NONE, 359e0100bfdSTinghan Shen pdev, sizeof(*pdev)); 360e0100bfdSTinghan Shen if (IS_ERR(priv->ipc_dev)) { 361427eb3e1SDan Carpenter ret = PTR_ERR(priv->ipc_dev); 362e0100bfdSTinghan Shen dev_err(sdev->dev, "failed to create mtk-adsp-ipc device\n"); 363e0100bfdSTinghan Shen goto err_adsp_off; 364e0100bfdSTinghan Shen } 365e0100bfdSTinghan Shen 366e0100bfdSTinghan Shen priv->dsp_ipc = dev_get_drvdata(&priv->ipc_dev->dev); 367e0100bfdSTinghan Shen if (!priv->dsp_ipc) { 368e0100bfdSTinghan Shen ret = -EPROBE_DEFER; 369e0100bfdSTinghan Shen dev_err(sdev->dev, "failed to get drvdata\n"); 370e0100bfdSTinghan Shen goto exit_pdev_unregister; 371e0100bfdSTinghan Shen } 372e0100bfdSTinghan Shen 373e0100bfdSTinghan Shen mtk_adsp_ipc_set_data(priv->dsp_ipc, priv); 374e0100bfdSTinghan Shen priv->dsp_ipc->ops = &dsp_ops; 375e0100bfdSTinghan Shen 3761f0214a8STinghan Shen return 0; 377e0100bfdSTinghan Shen 378e0100bfdSTinghan Shen exit_pdev_unregister: 379e0100bfdSTinghan Shen platform_device_unregister(priv->ipc_dev); 380e0100bfdSTinghan Shen err_adsp_off: 381e0100bfdSTinghan Shen adsp_sram_power_off(sdev); 382e0100bfdSTinghan Shen mt8186_adsp_clock_off(sdev); 383e0100bfdSTinghan Shen 384e0100bfdSTinghan Shen return ret; 3851f0214a8STinghan Shen } 3861f0214a8STinghan Shen 3871f0214a8STinghan Shen static int mt8186_dsp_remove(struct snd_sof_dev *sdev) 3881f0214a8STinghan Shen { 389e0100bfdSTinghan Shen struct adsp_priv *priv = sdev->pdata->hw_pdata; 390e0100bfdSTinghan Shen 391e0100bfdSTinghan Shen platform_device_unregister(priv->ipc_dev); 3929ce170dcSTinghan Shen mt8186_sof_hifixdsp_shutdown(sdev); 3931f0214a8STinghan Shen adsp_sram_power_off(sdev); 3949ce170dcSTinghan Shen mt8186_adsp_clock_off(sdev); 3951f0214a8STinghan Shen 3961f0214a8STinghan Shen return 0; 3971f0214a8STinghan Shen } 3981f0214a8STinghan Shen 399e063330aSRicardo Ribalda static int mt8186_dsp_shutdown(struct snd_sof_dev *sdev) 400e063330aSRicardo Ribalda { 401e063330aSRicardo Ribalda return snd_sof_suspend(sdev->dev); 402e063330aSRicardo Ribalda } 403e063330aSRicardo Ribalda 4040e0b83ccSTinghan Shen static int mt8186_dsp_suspend(struct snd_sof_dev *sdev, u32 target_state) 4050e0b83ccSTinghan Shen { 4069ce170dcSTinghan Shen mt8186_sof_hifixdsp_shutdown(sdev); 4070e0b83ccSTinghan Shen adsp_sram_power_off(sdev); 4089ce170dcSTinghan Shen mt8186_adsp_clock_off(sdev); 4090e0b83ccSTinghan Shen 4100e0b83ccSTinghan Shen return 0; 4110e0b83ccSTinghan Shen } 4120e0b83ccSTinghan Shen 4130e0b83ccSTinghan Shen static int mt8186_dsp_resume(struct snd_sof_dev *sdev) 4140e0b83ccSTinghan Shen { 4150e0b83ccSTinghan Shen int ret; 4160e0b83ccSTinghan Shen 4179ce170dcSTinghan Shen ret = mt8186_adsp_clock_on(sdev); 4180e0b83ccSTinghan Shen if (ret) { 4199ce170dcSTinghan Shen dev_err(sdev->dev, "mt8186_adsp_clock_on fail!\n"); 4200e0b83ccSTinghan Shen return ret; 4210e0b83ccSTinghan Shen } 4220e0b83ccSTinghan Shen 4230e0b83ccSTinghan Shen adsp_sram_power_on(sdev); 4240e0b83ccSTinghan Shen 4250e0b83ccSTinghan Shen return ret; 4260e0b83ccSTinghan Shen } 4270e0b83ccSTinghan Shen 4281f0214a8STinghan Shen /* on mt8186 there is 1 to 1 match between type and BAR idx */ 4291f0214a8STinghan Shen static int mt8186_get_bar_index(struct snd_sof_dev *sdev, u32 type) 4301f0214a8STinghan Shen { 4311f0214a8STinghan Shen return type; 4321f0214a8STinghan Shen } 4331f0214a8STinghan Shen 43478091edcSChunxu Li static int mt8186_pcm_hw_params(struct snd_sof_dev *sdev, 43578091edcSChunxu Li struct snd_pcm_substream *substream, 43678091edcSChunxu Li struct snd_pcm_hw_params *params, 43778091edcSChunxu Li struct snd_sof_platform_stream_params *platform_params) 43878091edcSChunxu Li { 43978091edcSChunxu Li platform_params->cont_update_posn = 1; 44078091edcSChunxu Li 44178091edcSChunxu Li return 0; 44278091edcSChunxu Li } 44378091edcSChunxu Li 444a921986fSChunxu Li static snd_pcm_uframes_t mt8186_pcm_pointer(struct snd_sof_dev *sdev, 445a921986fSChunxu Li struct snd_pcm_substream *substream) 446a921986fSChunxu Li { 447a921986fSChunxu Li int ret; 448a921986fSChunxu Li snd_pcm_uframes_t pos; 449a921986fSChunxu Li struct snd_sof_pcm *spcm; 450a921986fSChunxu Li struct sof_ipc_stream_posn posn; 451a921986fSChunxu Li struct snd_sof_pcm_stream *stream; 452a921986fSChunxu Li struct snd_soc_component *scomp = sdev->component; 453a921986fSChunxu Li struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); 454a921986fSChunxu Li 455a921986fSChunxu Li spcm = snd_sof_find_spcm_dai(scomp, rtd); 456a921986fSChunxu Li if (!spcm) { 457a921986fSChunxu Li dev_warn_ratelimited(sdev->dev, "warn: can't find PCM with DAI ID %d\n", 458a921986fSChunxu Li rtd->dai_link->id); 459a921986fSChunxu Li return 0; 460a921986fSChunxu Li } 461a921986fSChunxu Li 462a921986fSChunxu Li stream = &spcm->stream[substream->stream]; 4631b905942SDaniel Baluta ret = snd_sof_ipc_msg_data(sdev, stream, &posn, sizeof(posn)); 464a921986fSChunxu Li if (ret < 0) { 465a921986fSChunxu Li dev_warn(sdev->dev, "failed to read stream position: %d\n", ret); 466a921986fSChunxu Li return 0; 467a921986fSChunxu Li } 468a921986fSChunxu Li 469a921986fSChunxu Li memcpy(&stream->posn, &posn, sizeof(posn)); 470a921986fSChunxu Li pos = spcm->stream[substream->stream].posn.host_posn; 471a921986fSChunxu Li pos = bytes_to_frames(substream->runtime, pos); 472a921986fSChunxu Li 473a921986fSChunxu Li return pos; 474a921986fSChunxu Li } 475a921986fSChunxu Li 476f3b75e9bSChunxu Li static struct snd_soc_dai_driver mt8186_dai[] = { 477f3b75e9bSChunxu Li { 478f3b75e9bSChunxu Li .name = "SOF_DL1", 479f3b75e9bSChunxu Li .playback = { 480f3b75e9bSChunxu Li .channels_min = 1, 481f3b75e9bSChunxu Li .channels_max = 2, 482f3b75e9bSChunxu Li }, 483f3b75e9bSChunxu Li }, 484f3b75e9bSChunxu Li { 485f3b75e9bSChunxu Li .name = "SOF_DL2", 486f3b75e9bSChunxu Li .playback = { 487f3b75e9bSChunxu Li .channels_min = 1, 488f3b75e9bSChunxu Li .channels_max = 2, 489f3b75e9bSChunxu Li }, 490f3b75e9bSChunxu Li }, 491f3b75e9bSChunxu Li { 492f3b75e9bSChunxu Li .name = "SOF_UL1", 493f3b75e9bSChunxu Li .capture = { 494f3b75e9bSChunxu Li .channels_min = 1, 495f3b75e9bSChunxu Li .channels_max = 2, 496f3b75e9bSChunxu Li }, 497f3b75e9bSChunxu Li }, 498f3b75e9bSChunxu Li { 499f3b75e9bSChunxu Li .name = "SOF_UL2", 500f3b75e9bSChunxu Li .capture = { 501f3b75e9bSChunxu Li .channels_min = 1, 502f3b75e9bSChunxu Li .channels_max = 2, 503f3b75e9bSChunxu Li }, 504f3b75e9bSChunxu Li }, 505f3b75e9bSChunxu Li }; 506f3b75e9bSChunxu Li 5071f0214a8STinghan Shen /* mt8186 ops */ 5081f0214a8STinghan Shen static struct snd_sof_dsp_ops sof_mt8186_ops = { 5091f0214a8STinghan Shen /* probe and remove */ 5101f0214a8STinghan Shen .probe = mt8186_dsp_probe, 5111f0214a8STinghan Shen .remove = mt8186_dsp_remove, 512e063330aSRicardo Ribalda .shutdown = mt8186_dsp_shutdown, 5131f0214a8STinghan Shen 514570c14dcSTinghan Shen /* DSP core boot */ 515570c14dcSTinghan Shen .run = mt8186_run, 516570c14dcSTinghan Shen 5171f0214a8STinghan Shen /* Block IO */ 5181f0214a8STinghan Shen .block_read = sof_block_read, 5191f0214a8STinghan Shen .block_write = sof_block_write, 5201f0214a8STinghan Shen 52182e93430SChunxu Li /* Mailbox IO */ 52282e93430SChunxu Li .mailbox_read = sof_mailbox_read, 52382e93430SChunxu Li .mailbox_write = sof_mailbox_write, 52482e93430SChunxu Li 5251f0214a8STinghan Shen /* Register IO */ 5261f0214a8STinghan Shen .write = sof_io_write, 5271f0214a8STinghan Shen .read = sof_io_read, 5281f0214a8STinghan Shen .write64 = sof_io_write64, 5291f0214a8STinghan Shen .read64 = sof_io_read64, 5301f0214a8STinghan Shen 531e0100bfdSTinghan Shen /* ipc */ 532e0100bfdSTinghan Shen .send_msg = mt8186_send_msg, 533e0100bfdSTinghan Shen .get_mailbox_offset = mt8186_get_mailbox_offset, 534e0100bfdSTinghan Shen .get_window_offset = mt8186_get_window_offset, 53505984607SChunxu Li .ipc_msg_data = sof_ipc_msg_data, 536e0100bfdSTinghan Shen .set_stream_data_offset = sof_set_stream_data_offset, 537e0100bfdSTinghan Shen 5381f0214a8STinghan Shen /* misc */ 5391f0214a8STinghan Shen .get_bar_index = mt8186_get_bar_index, 5401f0214a8STinghan Shen 54182e93430SChunxu Li /* stream callbacks */ 54282e93430SChunxu Li .pcm_open = sof_stream_pcm_open, 54378091edcSChunxu Li .pcm_hw_params = mt8186_pcm_hw_params, 544a921986fSChunxu Li .pcm_pointer = mt8186_pcm_pointer, 54582e93430SChunxu Li .pcm_close = sof_stream_pcm_close, 54682e93430SChunxu Li 547570c14dcSTinghan Shen /* firmware loading */ 548570c14dcSTinghan Shen .load_firmware = snd_sof_load_firmware_memcpy, 549570c14dcSTinghan Shen 5501f0214a8STinghan Shen /* Firmware ops */ 5511f0214a8STinghan Shen .dsp_arch_ops = &sof_xtensa_arch_ops, 5521f0214a8STinghan Shen 553f3b75e9bSChunxu Li /* DAI drivers */ 554f3b75e9bSChunxu Li .drv = mt8186_dai, 555f3b75e9bSChunxu Li .num_drv = ARRAY_SIZE(mt8186_dai), 556f3b75e9bSChunxu Li 5576fa8c073STinghan Shen /* Debug information */ 5586fa8c073STinghan Shen .debugfs_add_region_item = snd_sof_debugfs_add_region_item_iomem, 5596fa8c073STinghan Shen 5600e0b83ccSTinghan Shen /* PM */ 5610e0b83ccSTinghan Shen .suspend = mt8186_dsp_suspend, 5620e0b83ccSTinghan Shen .resume = mt8186_dsp_resume, 5630e0b83ccSTinghan Shen 5641f0214a8STinghan Shen /* ALSA HW info flags */ 5651f0214a8STinghan Shen .hw_info = SNDRV_PCM_INFO_MMAP | 5661f0214a8STinghan Shen SNDRV_PCM_INFO_MMAP_VALID | 5671f0214a8STinghan Shen SNDRV_PCM_INFO_INTERLEAVED | 5681f0214a8STinghan Shen SNDRV_PCM_INFO_PAUSE | 5691f0214a8STinghan Shen SNDRV_PCM_INFO_NO_PERIOD_WAKEUP, 5701f0214a8STinghan Shen }; 5711f0214a8STinghan Shen 5722dec9e09SChunxu Li static struct snd_sof_of_mach sof_mt8186_machs[] = { 5732dec9e09SChunxu Li { 5742dec9e09SChunxu Li .compatible = "mediatek,mt8186", 5752dec9e09SChunxu Li .sof_tplg_filename = "sof-mt8186.tplg", 5762dec9e09SChunxu Li }, 5772dec9e09SChunxu Li {} 5782dec9e09SChunxu Li }; 5792dec9e09SChunxu Li 5801f0214a8STinghan Shen static const struct sof_dev_desc sof_of_mt8186_desc = { 5812dec9e09SChunxu Li .of_machines = sof_mt8186_machs, 5821f0214a8STinghan Shen .ipc_supported_mask = BIT(SOF_IPC), 5831f0214a8STinghan Shen .ipc_default = SOF_IPC, 5841f0214a8STinghan Shen .default_fw_path = { 5851f0214a8STinghan Shen [SOF_IPC] = "mediatek/sof", 5861f0214a8STinghan Shen }, 5871f0214a8STinghan Shen .default_tplg_path = { 5881f0214a8STinghan Shen [SOF_IPC] = "mediatek/sof-tplg", 5891f0214a8STinghan Shen }, 5901f0214a8STinghan Shen .default_fw_filename = { 5911f0214a8STinghan Shen [SOF_IPC] = "sof-mt8186.ri", 5921f0214a8STinghan Shen }, 5931f0214a8STinghan Shen .nocodec_tplg_filename = "sof-mt8186-nocodec.tplg", 5941f0214a8STinghan Shen .ops = &sof_mt8186_ops, 5951f0214a8STinghan Shen }; 5961f0214a8STinghan Shen 5976b43538fSTinghan Shen static const struct sof_dev_desc sof_of_mt8188_desc = { 5986b43538fSTinghan Shen .ipc_supported_mask = BIT(SOF_IPC), 5996b43538fSTinghan Shen .ipc_default = SOF_IPC, 6006b43538fSTinghan Shen .default_fw_path = { 6016b43538fSTinghan Shen [SOF_IPC] = "mediatek/sof", 6026b43538fSTinghan Shen }, 6036b43538fSTinghan Shen .default_tplg_path = { 6046b43538fSTinghan Shen [SOF_IPC] = "mediatek/sof-tplg", 6056b43538fSTinghan Shen }, 6066b43538fSTinghan Shen .default_fw_filename = { 6076b43538fSTinghan Shen [SOF_IPC] = "sof-mt8188.ri", 6086b43538fSTinghan Shen }, 6096b43538fSTinghan Shen .nocodec_tplg_filename = "sof-mt8188-nocodec.tplg", 6106b43538fSTinghan Shen .ops = &sof_mt8186_ops, 6116b43538fSTinghan Shen }; 6126b43538fSTinghan Shen 6131f0214a8STinghan Shen static const struct of_device_id sof_of_mt8186_ids[] = { 6141f0214a8STinghan Shen { .compatible = "mediatek,mt8186-dsp", .data = &sof_of_mt8186_desc}, 6156b43538fSTinghan Shen { .compatible = "mediatek,mt8188-dsp", .data = &sof_of_mt8188_desc}, 6161f0214a8STinghan Shen { } 6171f0214a8STinghan Shen }; 6181f0214a8STinghan Shen MODULE_DEVICE_TABLE(of, sof_of_mt8186_ids); 6191f0214a8STinghan Shen 6201f0214a8STinghan Shen /* DT driver definition */ 6211f0214a8STinghan Shen static struct platform_driver snd_sof_of_mt8186_driver = { 6221f0214a8STinghan Shen .probe = sof_of_probe, 6231f0214a8STinghan Shen .remove = sof_of_remove, 624e063330aSRicardo Ribalda .shutdown = sof_of_shutdown, 6251f0214a8STinghan Shen .driver = { 6261f0214a8STinghan Shen .name = "sof-audio-of-mt8186", 6271f0214a8STinghan Shen .pm = &sof_of_pm, 6281f0214a8STinghan Shen .of_match_table = sof_of_mt8186_ids, 6291f0214a8STinghan Shen }, 6301f0214a8STinghan Shen }; 6311f0214a8STinghan Shen module_platform_driver(snd_sof_of_mt8186_driver); 6321f0214a8STinghan Shen 6331f0214a8STinghan Shen MODULE_IMPORT_NS(SND_SOC_SOF_XTENSA); 6341f0214a8STinghan Shen MODULE_IMPORT_NS(SND_SOC_SOF_MTK_COMMON); 6351f0214a8STinghan Shen MODULE_LICENSE("Dual BSD/GPL"); 636