132d7e03dSYC Hung /* SPDX-License-Identifier: GPL-2.0 */ 232d7e03dSYC Hung 332d7e03dSYC Hung /* 432d7e03dSYC Hung * Copyright (c) 2021 MediaTek Corporation. All rights reserved. 532d7e03dSYC Hung */ 632d7e03dSYC Hung 732d7e03dSYC Hung #ifndef __MTK_ADSP_HELPER_H__ 832d7e03dSYC Hung #define __MTK_ADSP_HELPER_H__ 932d7e03dSYC Hung 1032d7e03dSYC Hung /* 1132d7e03dSYC Hung * Global important adsp data structure. 1232d7e03dSYC Hung */ 1332d7e03dSYC Hung #define DSP_MBOX_NUM 3 1432d7e03dSYC Hung 1532d7e03dSYC Hung struct mtk_adsp_chip_info { 1632d7e03dSYC Hung phys_addr_t pa_sram; 1732d7e03dSYC Hung phys_addr_t pa_dram; /* adsp dram physical base */ 1832d7e03dSYC Hung phys_addr_t pa_shared_dram; /* adsp dram physical base */ 1932d7e03dSYC Hung phys_addr_t pa_cfgreg; 2032d7e03dSYC Hung phys_addr_t pa_mboxreg[DSP_MBOX_NUM]; 2132d7e03dSYC Hung u32 sramsize; 2232d7e03dSYC Hung u32 dramsize; 2332d7e03dSYC Hung u32 cfgregsize; 2432d7e03dSYC Hung void __iomem *va_sram; /* corresponding to pa_sram */ 2532d7e03dSYC Hung void __iomem *va_dram; /* corresponding to pa_dram */ 2632d7e03dSYC Hung void __iomem *va_cfgreg; 2732d7e03dSYC Hung void __iomem *va_mboxreg[DSP_MBOX_NUM]; 2832d7e03dSYC Hung void __iomem *shared_sram; /* part of va_sram */ 2932d7e03dSYC Hung void __iomem *shared_dram; /* part of va_dram */ 3032d7e03dSYC Hung phys_addr_t adsp_bootup_addr; 3132d7e03dSYC Hung int dram_offset; /*dram offset between system and dsp view*/ 32*1f0214a8STinghan Shen 33*1f0214a8STinghan Shen phys_addr_t pa_secreg; 34*1f0214a8STinghan Shen u32 secregsize; 35*1f0214a8STinghan Shen void __iomem *va_secreg; 36*1f0214a8STinghan Shen 37*1f0214a8STinghan Shen phys_addr_t pa_busreg; 38*1f0214a8STinghan Shen u32 busregsize; 39*1f0214a8STinghan Shen void __iomem *va_busreg; 4032d7e03dSYC Hung }; 4132d7e03dSYC Hung 4232d7e03dSYC Hung struct adsp_priv { 4332d7e03dSYC Hung struct device *dev; 4432d7e03dSYC Hung struct snd_sof_dev *sdev; 4532d7e03dSYC Hung 4632d7e03dSYC Hung /* DSP IPC handler */ 4732d7e03dSYC Hung struct mbox_controller *adsp_mbox; 4832d7e03dSYC Hung 4932d7e03dSYC Hung struct mtk_adsp_chip_info *adsp; 50424d6d1aSYC Hung struct clk **clk; 5132d7e03dSYC Hung u32 (*ap2adsp_addr)(u32 addr, void *data); 5232d7e03dSYC Hung u32 (*adsp2ap_addr)(u32 addr, void *data); 5332d7e03dSYC Hung 5432d7e03dSYC Hung void *private_data; 5532d7e03dSYC Hung }; 5632d7e03dSYC Hung 5732d7e03dSYC Hung #endif 58