1*2740dcceSRander Wang /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ 2*2740dcceSRander Wang /* 3*2740dcceSRander Wang * This file is provided under a dual BSD/GPLv2 license. When using or 4*2740dcceSRander Wang * redistributing this file, you may do so under either license. 5*2740dcceSRander Wang * 6*2740dcceSRander Wang * Copyright(c) 2022 Intel Corporation. All rights reserved. 7*2740dcceSRander Wang */ 8*2740dcceSRander Wang 9*2740dcceSRander Wang #ifndef __IPC4_FW_REG_H__ 10*2740dcceSRander Wang #define __IPC4_FW_REG_H__ 11*2740dcceSRander Wang 12*2740dcceSRander Wang #define SOF_IPC4_INVALID_STREAM_POSITION ULLONG_MAX 13*2740dcceSRander Wang 14*2740dcceSRander Wang /** 15*2740dcceSRander Wang * struct sof_ipc4_pipeline_registers - Pipeline start and end information in fw 16*2740dcceSRander Wang * @stream_start_offset: Stream start offset (LPIB) reported by mixin 17*2740dcceSRander Wang * module allocated on pipeline attached to Host Output Gateway when 18*2740dcceSRander Wang * first data is being mixed to mixout module. When data is not mixed 19*2740dcceSRander Wang * (right after creation/after reset) value "(u64)-1" is reported 20*2740dcceSRander Wang * @stream_end_offset: Stream end offset (LPIB) reported by mixin 21*2740dcceSRander Wang * module allocated on pipeline attached to Host Output Gateway 22*2740dcceSRander Wang * during transition from RUNNING to PAUSED. When data is not mixed 23*2740dcceSRander Wang * (right after creation or after reset) value "(u64)-1" is reported. 24*2740dcceSRander Wang * When first data is mixed then value "0"is reported. 25*2740dcceSRander Wang */ 26*2740dcceSRander Wang struct sof_ipc4_pipeline_registers { 27*2740dcceSRander Wang u64 stream_start_offset; 28*2740dcceSRander Wang u64 stream_end_offset; 29*2740dcceSRander Wang } __packed __aligned(4); 30*2740dcceSRander Wang 31*2740dcceSRander Wang #define SOF_IPC4_PV_MAX_SUPPORTED_CHANNELS 8 32*2740dcceSRander Wang 33*2740dcceSRander Wang /** 34*2740dcceSRander Wang * struct sof_ipc4_peak_volume_regs - Volume information in fw 35*2740dcceSRander Wang * @peak_meter: Peak volume value in fw 36*2740dcceSRander Wang * @current_volume: Current volume value in fw 37*2740dcceSRander Wang * @target_volume: Target volume value in fw 38*2740dcceSRander Wang */ 39*2740dcceSRander Wang struct sof_ipc4_peak_volume_regs { 40*2740dcceSRander Wang u32 peak_meter[SOF_IPC4_PV_MAX_SUPPORTED_CHANNELS]; 41*2740dcceSRander Wang u32 current_volume[SOF_IPC4_PV_MAX_SUPPORTED_CHANNELS]; 42*2740dcceSRander Wang u32 target_volume[SOF_IPC4_PV_MAX_SUPPORTED_CHANNELS]; 43*2740dcceSRander Wang } __packed __aligned(4); 44*2740dcceSRander Wang 45*2740dcceSRander Wang /** 46*2740dcceSRander Wang * struct sof_ipc4_llp_reading - Llp information in fw 47*2740dcceSRander Wang * @llp_l: Lower part of 64-bit LLP 48*2740dcceSRander Wang * @llp_u: Upper part of 64-bit LLP 49*2740dcceSRander Wang * @wclk_l: Lower part of 64-bit Wallclock 50*2740dcceSRander Wang * @wclk_u: Upper part of 64-bit Wallclock 51*2740dcceSRander Wang */ 52*2740dcceSRander Wang struct sof_ipc4_llp_reading { 53*2740dcceSRander Wang u32 llp_l; 54*2740dcceSRander Wang u32 llp_u; 55*2740dcceSRander Wang u32 wclk_l; 56*2740dcceSRander Wang u32 wclk_u; 57*2740dcceSRander Wang } __packed __aligned(4); 58*2740dcceSRander Wang 59*2740dcceSRander Wang /** 60*2740dcceSRander Wang * struct of sof_ipc4_llp_reading_extended - Extended llp info 61*2740dcceSRander Wang * @llp_reading: Llp information in memory window 62*2740dcceSRander Wang * @tpd_low: Total processed data (low part) 63*2740dcceSRander Wang * @tpd_high: Total processed data (high part) 64*2740dcceSRander Wang */ 65*2740dcceSRander Wang struct sof_ipc4_llp_reading_extended { 66*2740dcceSRander Wang struct sof_ipc4_llp_reading llp_reading; 67*2740dcceSRander Wang u32 tpd_low; 68*2740dcceSRander Wang u32 tpd_high; 69*2740dcceSRander Wang } __packed __aligned(4); 70*2740dcceSRander Wang 71*2740dcceSRander Wang /** 72*2740dcceSRander Wang * struct sof_ipc4_llp_reading_slot - Llp slot information in memory window 73*2740dcceSRander Wang * @node_id: Dai gateway node id 74*2740dcceSRander Wang * @reading: Llp information in memory window 75*2740dcceSRander Wang */ 76*2740dcceSRander Wang struct sof_ipc4_llp_reading_slot { 77*2740dcceSRander Wang u32 node_id; 78*2740dcceSRander Wang struct sof_ipc4_llp_reading reading; 79*2740dcceSRander Wang } __packed __aligned(4); 80*2740dcceSRander Wang 81*2740dcceSRander Wang /* ROM information */ 82*2740dcceSRander Wang #define SOF_IPC4_FW_FUSE_VALUE_MASK GENMASK(7, 0) 83*2740dcceSRander Wang #define SOF_IPC4_FW_LOAD_METHOD_MASK BIT(8) 84*2740dcceSRander Wang #define SOF_IPC4_FW_DOWNLINK_IPC_USE_DMA_MASK BIT(9) 85*2740dcceSRander Wang #define SOF_IPC4_FW_LOAD_METHOD_REV_MASK GENMASK(11, 10) 86*2740dcceSRander Wang #define SOF_IPC4_FW_REVISION_MIN_MASK GENMASK(15, 12) 87*2740dcceSRander Wang #define SOF_IPC4_FW_REVISION_MAJ_MASK GENMASK(19, 16) 88*2740dcceSRander Wang #define SOF_IPC4_FW_VERSION_MIN_MASK GENMASK(23, 20) 89*2740dcceSRander Wang #define SOF_IPC4_FW_VERSION_MAJ_MASK GENMASK(27, 24) 90*2740dcceSRander Wang 91*2740dcceSRander Wang /* Number of dsp core supported in FW Regs. */ 92*2740dcceSRander Wang #define SOF_IPC4_MAX_SUPPORTED_ADSP_CORES 8 93*2740dcceSRander Wang 94*2740dcceSRander Wang /* Number of host pipeline registers slots in FW Regs. */ 95*2740dcceSRander Wang #define SOF_IPC4_MAX_PIPELINE_REG_SLOTS 16 96*2740dcceSRander Wang 97*2740dcceSRander Wang /* Number of PeakVol registers slots in FW Regs. */ 98*2740dcceSRander Wang #define SOF_IPC4_MAX_PEAK_VOL_REG_SLOTS 16 99*2740dcceSRander Wang 100*2740dcceSRander Wang /* Number of GPDMA LLP Reading slots in FW Regs. */ 101*2740dcceSRander Wang #define SOF_IPC4_MAX_LLP_GPDMA_READING_SLOTS 24 102*2740dcceSRander Wang 103*2740dcceSRander Wang /* Number of Aggregated SNDW Reading slots in FW Regs. */ 104*2740dcceSRander Wang #define SOF_IPC4_MAX_LLP_SNDW_READING_SLOTS 15 105*2740dcceSRander Wang 106*2740dcceSRander Wang /* Current ABI version of the Fw registers layout. */ 107*2740dcceSRander Wang #define SOF_IPC4_FW_REGS_ABI_VER 1 108*2740dcceSRander Wang 109*2740dcceSRander Wang /** 110*2740dcceSRander Wang * struct sof_ipc4_fw_registers - FW Registers exposes additional 111*2740dcceSRander Wang * DSP / FW state information to the driver 112*2740dcceSRander Wang * @fw_status: Current ROM / FW status 113*2740dcceSRander Wang * @lec: Last ROM / FW error code 114*2740dcceSRander Wang * @fps: Current DSP clock status 115*2740dcceSRander Wang * @lnec: Last Native Error Code(from external library) 116*2740dcceSRander Wang * @ltr: Copy of LTRC HW register value(FW only) 117*2740dcceSRander Wang * @rsvd0: Reserved0 118*2740dcceSRander Wang * @rom_info: ROM info 119*2740dcceSRander Wang * @abi_ver: Version of the layout, set to the current FW_REGS_ABI_VER 120*2740dcceSRander Wang * @slave_core_sts: Slave core states 121*2740dcceSRander Wang * @rsvd2: Reserved2 122*2740dcceSRander Wang * @pipeline_regs: State of pipelines attached to host output gateways 123*2740dcceSRander Wang * @peak_vol_regs: State of PeakVol instances indexed by the PeakVol's instance_id 124*2740dcceSRander Wang * @llp_gpdma_reading_slots: LLP Readings for single link gateways 125*2740dcceSRander Wang * @llp_sndw_reading_slots: SNDW aggregated link gateways 126*2740dcceSRander Wang * @llp_evad_reading_slot: LLP Readings for EVAD gateway 127*2740dcceSRander Wang */ 128*2740dcceSRander Wang struct sof_ipc4_fw_registers { 129*2740dcceSRander Wang u32 fw_status; 130*2740dcceSRander Wang u32 lec; 131*2740dcceSRander Wang u32 fps; 132*2740dcceSRander Wang u32 lnec; 133*2740dcceSRander Wang u32 ltr; 134*2740dcceSRander Wang u32 rsvd0; 135*2740dcceSRander Wang u32 rom_info; 136*2740dcceSRander Wang u32 abi_ver; 137*2740dcceSRander Wang u8 slave_core_sts[SOF_IPC4_MAX_SUPPORTED_ADSP_CORES]; 138*2740dcceSRander Wang u32 rsvd2[6]; 139*2740dcceSRander Wang 140*2740dcceSRander Wang struct sof_ipc4_pipeline_registers 141*2740dcceSRander Wang pipeline_regs[SOF_IPC4_MAX_PIPELINE_REG_SLOTS]; 142*2740dcceSRander Wang 143*2740dcceSRander Wang struct sof_ipc4_peak_volume_regs 144*2740dcceSRander Wang peak_vol_regs[SOF_IPC4_MAX_PEAK_VOL_REG_SLOTS]; 145*2740dcceSRander Wang 146*2740dcceSRander Wang struct sof_ipc4_llp_reading_slot 147*2740dcceSRander Wang llp_gpdma_reading_slots[SOF_IPC4_MAX_LLP_GPDMA_READING_SLOTS]; 148*2740dcceSRander Wang 149*2740dcceSRander Wang struct sof_ipc4_llp_reading_slot 150*2740dcceSRander Wang llp_sndw_reading_slots[SOF_IPC4_MAX_LLP_SNDW_READING_SLOTS]; 151*2740dcceSRander Wang 152*2740dcceSRander Wang struct sof_ipc4_llp_reading_slot llp_evad_reading_slot; 153*2740dcceSRander Wang } __packed __aligned(4); 154*2740dcceSRander Wang 155*2740dcceSRander Wang #endif 156