1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 // 3 // This file is provided under a dual BSD/GPLv2 license. When using or 4 // redistributing this file, you may do so under either license. 5 // 6 // Copyright(c) 2018 Intel Corporation. All rights reserved. 7 // 8 // Author: Liam Girdwood <liam.r.girdwood@linux.intel.com> 9 // 10 // Generic IPC layer that can work over MMIO and SPI/I2C. PHY layer provided 11 // by platform driver code. 12 // 13 14 #include <linux/mutex.h> 15 #include <linux/types.h> 16 17 #include "sof-priv.h" 18 #include "sof-audio.h" 19 #include "ops.h" 20 21 static void ipc_trace_message(struct snd_sof_dev *sdev, u32 msg_id); 22 static void ipc_stream_message(struct snd_sof_dev *sdev, u32 msg_cmd); 23 24 /* 25 * IPC message Tx/Rx message handling. 26 */ 27 28 /* SOF generic IPC data */ 29 struct snd_sof_ipc { 30 struct snd_sof_dev *sdev; 31 32 /* protects messages and the disable flag */ 33 struct mutex tx_mutex; 34 /* disables further sending of ipc's */ 35 bool disable_ipc_tx; 36 37 struct snd_sof_ipc_msg msg; 38 }; 39 40 struct sof_ipc_ctrl_data_params { 41 size_t msg_bytes; 42 size_t hdr_bytes; 43 size_t pl_size; 44 size_t elems; 45 u32 num_msg; 46 u8 *src; 47 u8 *dst; 48 }; 49 50 #if IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG_VERBOSE_IPC) 51 static void ipc_log_header(struct device *dev, u8 *text, u32 cmd) 52 { 53 u8 *str; 54 u8 *str2 = NULL; 55 u32 glb; 56 u32 type; 57 bool vdbg = false; 58 59 glb = cmd & SOF_GLB_TYPE_MASK; 60 type = cmd & SOF_CMD_TYPE_MASK; 61 62 switch (glb) { 63 case SOF_IPC_GLB_REPLY: 64 str = "GLB_REPLY"; break; 65 case SOF_IPC_GLB_COMPOUND: 66 str = "GLB_COMPOUND"; break; 67 case SOF_IPC_GLB_TPLG_MSG: 68 str = "GLB_TPLG_MSG"; 69 switch (type) { 70 case SOF_IPC_TPLG_COMP_NEW: 71 str2 = "COMP_NEW"; break; 72 case SOF_IPC_TPLG_COMP_FREE: 73 str2 = "COMP_FREE"; break; 74 case SOF_IPC_TPLG_COMP_CONNECT: 75 str2 = "COMP_CONNECT"; break; 76 case SOF_IPC_TPLG_PIPE_NEW: 77 str2 = "PIPE_NEW"; break; 78 case SOF_IPC_TPLG_PIPE_FREE: 79 str2 = "PIPE_FREE"; break; 80 case SOF_IPC_TPLG_PIPE_CONNECT: 81 str2 = "PIPE_CONNECT"; break; 82 case SOF_IPC_TPLG_PIPE_COMPLETE: 83 str2 = "PIPE_COMPLETE"; break; 84 case SOF_IPC_TPLG_BUFFER_NEW: 85 str2 = "BUFFER_NEW"; break; 86 case SOF_IPC_TPLG_BUFFER_FREE: 87 str2 = "BUFFER_FREE"; break; 88 default: 89 str2 = "unknown type"; break; 90 } 91 break; 92 case SOF_IPC_GLB_PM_MSG: 93 str = "GLB_PM_MSG"; 94 switch (type) { 95 case SOF_IPC_PM_CTX_SAVE: 96 str2 = "CTX_SAVE"; break; 97 case SOF_IPC_PM_CTX_RESTORE: 98 str2 = "CTX_RESTORE"; break; 99 case SOF_IPC_PM_CTX_SIZE: 100 str2 = "CTX_SIZE"; break; 101 case SOF_IPC_PM_CLK_SET: 102 str2 = "CLK_SET"; break; 103 case SOF_IPC_PM_CLK_GET: 104 str2 = "CLK_GET"; break; 105 case SOF_IPC_PM_CLK_REQ: 106 str2 = "CLK_REQ"; break; 107 case SOF_IPC_PM_CORE_ENABLE: 108 str2 = "CORE_ENABLE"; break; 109 default: 110 str2 = "unknown type"; break; 111 } 112 break; 113 case SOF_IPC_GLB_COMP_MSG: 114 str = "GLB_COMP_MSG"; 115 switch (type) { 116 case SOF_IPC_COMP_SET_VALUE: 117 str2 = "SET_VALUE"; break; 118 case SOF_IPC_COMP_GET_VALUE: 119 str2 = "GET_VALUE"; break; 120 case SOF_IPC_COMP_SET_DATA: 121 str2 = "SET_DATA"; break; 122 case SOF_IPC_COMP_GET_DATA: 123 str2 = "GET_DATA"; break; 124 default: 125 str2 = "unknown type"; break; 126 } 127 break; 128 case SOF_IPC_GLB_STREAM_MSG: 129 str = "GLB_STREAM_MSG"; 130 switch (type) { 131 case SOF_IPC_STREAM_PCM_PARAMS: 132 str2 = "PCM_PARAMS"; break; 133 case SOF_IPC_STREAM_PCM_PARAMS_REPLY: 134 str2 = "PCM_REPLY"; break; 135 case SOF_IPC_STREAM_PCM_FREE: 136 str2 = "PCM_FREE"; break; 137 case SOF_IPC_STREAM_TRIG_START: 138 str2 = "TRIG_START"; break; 139 case SOF_IPC_STREAM_TRIG_STOP: 140 str2 = "TRIG_STOP"; break; 141 case SOF_IPC_STREAM_TRIG_PAUSE: 142 str2 = "TRIG_PAUSE"; break; 143 case SOF_IPC_STREAM_TRIG_RELEASE: 144 str2 = "TRIG_RELEASE"; break; 145 case SOF_IPC_STREAM_TRIG_DRAIN: 146 str2 = "TRIG_DRAIN"; break; 147 case SOF_IPC_STREAM_TRIG_XRUN: 148 str2 = "TRIG_XRUN"; break; 149 case SOF_IPC_STREAM_POSITION: 150 vdbg = true; 151 str2 = "POSITION"; break; 152 case SOF_IPC_STREAM_VORBIS_PARAMS: 153 str2 = "VORBIS_PARAMS"; break; 154 case SOF_IPC_STREAM_VORBIS_FREE: 155 str2 = "VORBIS_FREE"; break; 156 default: 157 str2 = "unknown type"; break; 158 } 159 break; 160 case SOF_IPC_FW_READY: 161 str = "FW_READY"; break; 162 case SOF_IPC_GLB_DAI_MSG: 163 str = "GLB_DAI_MSG"; 164 switch (type) { 165 case SOF_IPC_DAI_CONFIG: 166 str2 = "CONFIG"; break; 167 case SOF_IPC_DAI_LOOPBACK: 168 str2 = "LOOPBACK"; break; 169 default: 170 str2 = "unknown type"; break; 171 } 172 break; 173 case SOF_IPC_GLB_TRACE_MSG: 174 str = "GLB_TRACE_MSG"; break; 175 case SOF_IPC_GLB_TEST_MSG: 176 str = "GLB_TEST_MSG"; 177 switch (type) { 178 case SOF_IPC_TEST_IPC_FLOOD: 179 str2 = "IPC_FLOOD"; break; 180 default: 181 str2 = "unknown type"; break; 182 } 183 break; 184 case SOF_IPC_GLB_DEBUG: 185 str = "GLB_DEBUG"; 186 switch (type) { 187 case SOF_IPC_DEBUG_MEM_USAGE: 188 str2 = "MEM_USAGE"; break; 189 default: 190 str2 = "unknown type"; break; 191 } 192 break; 193 default: 194 str = "unknown GLB command"; break; 195 } 196 197 if (str2) { 198 if (vdbg) 199 dev_vdbg(dev, "%s: 0x%x: %s: %s\n", text, cmd, str, str2); 200 else 201 dev_dbg(dev, "%s: 0x%x: %s: %s\n", text, cmd, str, str2); 202 } else { 203 dev_dbg(dev, "%s: 0x%x: %s\n", text, cmd, str); 204 } 205 } 206 #else 207 static inline void ipc_log_header(struct device *dev, u8 *text, u32 cmd) 208 { 209 if ((cmd & SOF_GLB_TYPE_MASK) != SOF_IPC_GLB_TRACE_MSG) 210 dev_dbg(dev, "%s: 0x%x\n", text, cmd); 211 } 212 #endif 213 214 /* wait for IPC message reply */ 215 static int tx_wait_done(struct snd_sof_ipc *ipc, struct snd_sof_ipc_msg *msg, 216 void *reply_data) 217 { 218 struct snd_sof_dev *sdev = ipc->sdev; 219 struct sof_ipc_cmd_hdr *hdr = msg->msg_data; 220 int ret; 221 222 /* wait for DSP IPC completion */ 223 ret = wait_event_timeout(msg->waitq, msg->ipc_complete, 224 msecs_to_jiffies(sdev->ipc_timeout)); 225 226 if (ret == 0) { 227 dev_err(sdev->dev, "error: ipc timed out for 0x%x size %d\n", 228 hdr->cmd, hdr->size); 229 snd_sof_handle_fw_exception(ipc->sdev); 230 ret = -ETIMEDOUT; 231 } else { 232 ret = msg->reply_error; 233 if (ret < 0) { 234 dev_err(sdev->dev, "error: ipc error for 0x%x size %zu\n", 235 hdr->cmd, msg->reply_size); 236 } else { 237 ipc_log_header(sdev->dev, "ipc tx succeeded", hdr->cmd); 238 if (msg->reply_size) 239 /* copy the data returned from DSP */ 240 memcpy(reply_data, msg->reply_data, 241 msg->reply_size); 242 } 243 } 244 245 return ret; 246 } 247 248 /* send IPC message from host to DSP */ 249 static int sof_ipc_tx_message_unlocked(struct snd_sof_ipc *ipc, u32 header, 250 void *msg_data, size_t msg_bytes, 251 void *reply_data, size_t reply_bytes) 252 { 253 struct snd_sof_dev *sdev = ipc->sdev; 254 struct snd_sof_ipc_msg *msg; 255 int ret; 256 257 if (ipc->disable_ipc_tx) 258 return -ENODEV; 259 260 /* 261 * The spin-lock is also still needed to protect message objects against 262 * other atomic contexts. 263 */ 264 spin_lock_irq(&sdev->ipc_lock); 265 266 /* initialise the message */ 267 msg = &ipc->msg; 268 269 msg->header = header; 270 msg->msg_size = msg_bytes; 271 msg->reply_size = reply_bytes; 272 msg->reply_error = 0; 273 274 /* attach any data */ 275 if (msg_bytes) 276 memcpy(msg->msg_data, msg_data, msg_bytes); 277 278 sdev->msg = msg; 279 280 ret = snd_sof_dsp_send_msg(sdev, msg); 281 /* Next reply that we receive will be related to this message */ 282 if (!ret) 283 msg->ipc_complete = false; 284 285 spin_unlock_irq(&sdev->ipc_lock); 286 287 if (ret < 0) { 288 dev_err_ratelimited(sdev->dev, 289 "error: ipc tx failed with error %d\n", 290 ret); 291 return ret; 292 } 293 294 ipc_log_header(sdev->dev, "ipc tx", msg->header); 295 296 /* now wait for completion */ 297 if (!ret) 298 ret = tx_wait_done(ipc, msg, reply_data); 299 300 return ret; 301 } 302 303 /* send IPC message from host to DSP */ 304 int sof_ipc_tx_message(struct snd_sof_ipc *ipc, u32 header, 305 void *msg_data, size_t msg_bytes, void *reply_data, 306 size_t reply_bytes) 307 { 308 const struct sof_dsp_power_state target_state = { 309 .state = SOF_DSP_PM_D0, 310 }; 311 int ret; 312 313 /* ensure the DSP is in D0 before sending a new IPC */ 314 ret = snd_sof_dsp_set_power_state(ipc->sdev, &target_state); 315 if (ret < 0) { 316 dev_err(ipc->sdev->dev, "error: resuming DSP %d\n", ret); 317 return ret; 318 } 319 320 return sof_ipc_tx_message_no_pm(ipc, header, msg_data, msg_bytes, 321 reply_data, reply_bytes); 322 } 323 EXPORT_SYMBOL(sof_ipc_tx_message); 324 325 /* 326 * send IPC message from host to DSP without modifying the DSP state. 327 * This will be used for IPC's that can be handled by the DSP 328 * even in a low-power D0 substate. 329 */ 330 int sof_ipc_tx_message_no_pm(struct snd_sof_ipc *ipc, u32 header, 331 void *msg_data, size_t msg_bytes, 332 void *reply_data, size_t reply_bytes) 333 { 334 int ret; 335 336 if (msg_bytes > SOF_IPC_MSG_MAX_SIZE || 337 reply_bytes > SOF_IPC_MSG_MAX_SIZE) 338 return -ENOBUFS; 339 340 /* Serialise IPC TX */ 341 mutex_lock(&ipc->tx_mutex); 342 343 ret = sof_ipc_tx_message_unlocked(ipc, header, msg_data, msg_bytes, 344 reply_data, reply_bytes); 345 346 mutex_unlock(&ipc->tx_mutex); 347 348 return ret; 349 } 350 EXPORT_SYMBOL(sof_ipc_tx_message_no_pm); 351 352 /* handle reply message from DSP */ 353 void snd_sof_ipc_reply(struct snd_sof_dev *sdev, u32 msg_id) 354 { 355 struct snd_sof_ipc_msg *msg = &sdev->ipc->msg; 356 357 if (msg->ipc_complete) { 358 dev_dbg(sdev->dev, 359 "no reply expected, received 0x%x, will be ignored", 360 msg_id); 361 return; 362 } 363 364 /* wake up and return the error if we have waiters on this message ? */ 365 msg->ipc_complete = true; 366 wake_up(&msg->waitq); 367 } 368 EXPORT_SYMBOL(snd_sof_ipc_reply); 369 370 /* DSP firmware has sent host a message */ 371 void snd_sof_ipc_msgs_rx(struct snd_sof_dev *sdev) 372 { 373 struct sof_ipc_cmd_hdr hdr; 374 u32 cmd, type; 375 int err = 0; 376 377 /* read back header */ 378 snd_sof_ipc_msg_data(sdev, NULL, &hdr, sizeof(hdr)); 379 ipc_log_header(sdev->dev, "ipc rx", hdr.cmd); 380 381 cmd = hdr.cmd & SOF_GLB_TYPE_MASK; 382 type = hdr.cmd & SOF_CMD_TYPE_MASK; 383 384 /* check message type */ 385 switch (cmd) { 386 case SOF_IPC_GLB_REPLY: 387 dev_err(sdev->dev, "error: ipc reply unknown\n"); 388 break; 389 case SOF_IPC_FW_READY: 390 /* check for FW boot completion */ 391 if (sdev->fw_state == SOF_FW_BOOT_IN_PROGRESS) { 392 err = sof_ops(sdev)->fw_ready(sdev, cmd); 393 if (err < 0) 394 sdev->fw_state = SOF_FW_BOOT_READY_FAILED; 395 else 396 sdev->fw_state = SOF_FW_BOOT_COMPLETE; 397 398 /* wake up firmware loader */ 399 wake_up(&sdev->boot_wait); 400 } 401 break; 402 case SOF_IPC_GLB_COMPOUND: 403 case SOF_IPC_GLB_TPLG_MSG: 404 case SOF_IPC_GLB_PM_MSG: 405 case SOF_IPC_GLB_COMP_MSG: 406 break; 407 case SOF_IPC_GLB_STREAM_MSG: 408 /* need to pass msg id into the function */ 409 ipc_stream_message(sdev, hdr.cmd); 410 break; 411 case SOF_IPC_GLB_TRACE_MSG: 412 ipc_trace_message(sdev, type); 413 break; 414 default: 415 dev_err(sdev->dev, "error: unknown DSP message 0x%x\n", cmd); 416 break; 417 } 418 419 ipc_log_header(sdev->dev, "ipc rx done", hdr.cmd); 420 } 421 EXPORT_SYMBOL(snd_sof_ipc_msgs_rx); 422 423 /* 424 * IPC trace mechanism. 425 */ 426 427 static void ipc_trace_message(struct snd_sof_dev *sdev, u32 msg_id) 428 { 429 struct sof_ipc_dma_trace_posn posn; 430 431 switch (msg_id) { 432 case SOF_IPC_TRACE_DMA_POSITION: 433 /* read back full message */ 434 snd_sof_ipc_msg_data(sdev, NULL, &posn, sizeof(posn)); 435 snd_sof_trace_update_pos(sdev, &posn); 436 break; 437 default: 438 dev_err(sdev->dev, "error: unhandled trace message %x\n", 439 msg_id); 440 break; 441 } 442 } 443 444 /* 445 * IPC stream position. 446 */ 447 448 static void ipc_period_elapsed(struct snd_sof_dev *sdev, u32 msg_id) 449 { 450 struct snd_soc_component *scomp = sdev->component; 451 struct snd_sof_pcm_stream *stream; 452 struct sof_ipc_stream_posn posn; 453 struct snd_sof_pcm *spcm; 454 int direction; 455 456 spcm = snd_sof_find_spcm_comp(scomp, msg_id, &direction); 457 if (!spcm) { 458 dev_err(sdev->dev, 459 "error: period elapsed for unknown stream, msg_id %d\n", 460 msg_id); 461 return; 462 } 463 464 stream = &spcm->stream[direction]; 465 snd_sof_ipc_msg_data(sdev, stream->substream, &posn, sizeof(posn)); 466 467 dev_vdbg(sdev->dev, "posn : host 0x%llx dai 0x%llx wall 0x%llx\n", 468 posn.host_posn, posn.dai_posn, posn.wallclock); 469 470 memcpy(&stream->posn, &posn, sizeof(posn)); 471 472 /* only inform ALSA for period_wakeup mode */ 473 if (!stream->substream->runtime->no_period_wakeup) 474 snd_sof_pcm_period_elapsed(stream->substream); 475 } 476 477 /* DSP notifies host of an XRUN within FW */ 478 static void ipc_xrun(struct snd_sof_dev *sdev, u32 msg_id) 479 { 480 struct snd_soc_component *scomp = sdev->component; 481 struct snd_sof_pcm_stream *stream; 482 struct sof_ipc_stream_posn posn; 483 struct snd_sof_pcm *spcm; 484 int direction; 485 486 spcm = snd_sof_find_spcm_comp(scomp, msg_id, &direction); 487 if (!spcm) { 488 dev_err(sdev->dev, "error: XRUN for unknown stream, msg_id %d\n", 489 msg_id); 490 return; 491 } 492 493 stream = &spcm->stream[direction]; 494 snd_sof_ipc_msg_data(sdev, stream->substream, &posn, sizeof(posn)); 495 496 dev_dbg(sdev->dev, "posn XRUN: host %llx comp %d size %d\n", 497 posn.host_posn, posn.xrun_comp_id, posn.xrun_size); 498 499 #if defined(CONFIG_SND_SOC_SOF_DEBUG_XRUN_STOP) 500 /* stop PCM on XRUN - used for pipeline debug */ 501 memcpy(&stream->posn, &posn, sizeof(posn)); 502 snd_pcm_stop_xrun(stream->substream); 503 #endif 504 } 505 506 /* stream notifications from DSP FW */ 507 static void ipc_stream_message(struct snd_sof_dev *sdev, u32 msg_cmd) 508 { 509 /* get msg cmd type and msd id */ 510 u32 msg_type = msg_cmd & SOF_CMD_TYPE_MASK; 511 u32 msg_id = SOF_IPC_MESSAGE_ID(msg_cmd); 512 513 switch (msg_type) { 514 case SOF_IPC_STREAM_POSITION: 515 ipc_period_elapsed(sdev, msg_id); 516 break; 517 case SOF_IPC_STREAM_TRIG_XRUN: 518 ipc_xrun(sdev, msg_id); 519 break; 520 default: 521 dev_err(sdev->dev, "error: unhandled stream message %x\n", 522 msg_id); 523 break; 524 } 525 } 526 527 /* get stream position IPC - use faster MMIO method if available on platform */ 528 int snd_sof_ipc_stream_posn(struct snd_soc_component *scomp, 529 struct snd_sof_pcm *spcm, int direction, 530 struct sof_ipc_stream_posn *posn) 531 { 532 struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(scomp); 533 struct sof_ipc_stream stream; 534 int err; 535 536 /* read position via slower IPC */ 537 stream.hdr.size = sizeof(stream); 538 stream.hdr.cmd = SOF_IPC_GLB_STREAM_MSG | SOF_IPC_STREAM_POSITION; 539 stream.comp_id = spcm->stream[direction].comp_id; 540 541 /* send IPC to the DSP */ 542 err = sof_ipc_tx_message(sdev->ipc, 543 stream.hdr.cmd, &stream, sizeof(stream), posn, 544 sizeof(*posn)); 545 if (err < 0) { 546 dev_err(sdev->dev, "error: failed to get stream %d position\n", 547 stream.comp_id); 548 return err; 549 } 550 551 return 0; 552 } 553 EXPORT_SYMBOL(snd_sof_ipc_stream_posn); 554 555 static int sof_get_ctrl_copy_params(enum sof_ipc_ctrl_type ctrl_type, 556 struct sof_ipc_ctrl_data *src, 557 struct sof_ipc_ctrl_data *dst, 558 struct sof_ipc_ctrl_data_params *sparams) 559 { 560 switch (ctrl_type) { 561 case SOF_CTRL_TYPE_VALUE_CHAN_GET: 562 case SOF_CTRL_TYPE_VALUE_CHAN_SET: 563 sparams->src = (u8 *)src->chanv; 564 sparams->dst = (u8 *)dst->chanv; 565 break; 566 case SOF_CTRL_TYPE_VALUE_COMP_GET: 567 case SOF_CTRL_TYPE_VALUE_COMP_SET: 568 sparams->src = (u8 *)src->compv; 569 sparams->dst = (u8 *)dst->compv; 570 break; 571 case SOF_CTRL_TYPE_DATA_GET: 572 case SOF_CTRL_TYPE_DATA_SET: 573 sparams->src = (u8 *)src->data->data; 574 sparams->dst = (u8 *)dst->data->data; 575 break; 576 default: 577 return -EINVAL; 578 } 579 580 /* calculate payload size and number of messages */ 581 sparams->pl_size = SOF_IPC_MSG_MAX_SIZE - sparams->hdr_bytes; 582 sparams->num_msg = DIV_ROUND_UP(sparams->msg_bytes, sparams->pl_size); 583 584 return 0; 585 } 586 587 static int sof_set_get_large_ctrl_data(struct snd_sof_dev *sdev, 588 struct sof_ipc_ctrl_data *cdata, 589 struct sof_ipc_ctrl_data_params *sparams, 590 bool send) 591 { 592 struct sof_ipc_ctrl_data *partdata; 593 size_t send_bytes; 594 size_t offset = 0; 595 size_t msg_bytes; 596 size_t pl_size; 597 int err; 598 int i; 599 600 /* allocate max ipc size because we have at least one */ 601 partdata = kzalloc(SOF_IPC_MSG_MAX_SIZE, GFP_KERNEL); 602 if (!partdata) 603 return -ENOMEM; 604 605 if (send) 606 err = sof_get_ctrl_copy_params(cdata->type, cdata, partdata, 607 sparams); 608 else 609 err = sof_get_ctrl_copy_params(cdata->type, partdata, cdata, 610 sparams); 611 if (err < 0) { 612 kfree(partdata); 613 return err; 614 } 615 616 msg_bytes = sparams->msg_bytes; 617 pl_size = sparams->pl_size; 618 619 /* copy the header data */ 620 memcpy(partdata, cdata, sparams->hdr_bytes); 621 622 /* Serialise IPC TX */ 623 mutex_lock(&sdev->ipc->tx_mutex); 624 625 /* copy the payload data in a loop */ 626 for (i = 0; i < sparams->num_msg; i++) { 627 send_bytes = min(msg_bytes, pl_size); 628 partdata->num_elems = send_bytes; 629 partdata->rhdr.hdr.size = sparams->hdr_bytes + send_bytes; 630 partdata->msg_index = i; 631 msg_bytes -= send_bytes; 632 partdata->elems_remaining = msg_bytes; 633 634 if (send) 635 memcpy(sparams->dst, sparams->src + offset, send_bytes); 636 637 err = sof_ipc_tx_message_unlocked(sdev->ipc, 638 partdata->rhdr.hdr.cmd, 639 partdata, 640 partdata->rhdr.hdr.size, 641 partdata, 642 partdata->rhdr.hdr.size); 643 if (err < 0) 644 break; 645 646 if (!send) 647 memcpy(sparams->dst + offset, sparams->src, send_bytes); 648 649 offset += pl_size; 650 } 651 652 mutex_unlock(&sdev->ipc->tx_mutex); 653 654 kfree(partdata); 655 return err; 656 } 657 658 /* 659 * IPC get()/set() for kcontrols. 660 */ 661 int snd_sof_ipc_set_get_comp_data(struct snd_sof_control *scontrol, 662 u32 ipc_cmd, 663 enum sof_ipc_ctrl_type ctrl_type, 664 enum sof_ipc_ctrl_cmd ctrl_cmd, 665 bool send) 666 { 667 struct snd_soc_component *scomp = scontrol->scomp; 668 struct sof_ipc_ctrl_data *cdata = scontrol->control_data; 669 struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(scomp); 670 struct sof_ipc_fw_ready *ready = &sdev->fw_ready; 671 struct sof_ipc_fw_version *v = &ready->version; 672 struct sof_ipc_ctrl_data_params sparams; 673 size_t send_bytes; 674 int err; 675 676 /* read or write firmware volume */ 677 if (scontrol->readback_offset != 0) { 678 /* write/read value header via mmaped region */ 679 send_bytes = sizeof(struct sof_ipc_ctrl_value_chan) * 680 cdata->num_elems; 681 if (send) 682 snd_sof_dsp_block_write(sdev, sdev->mmio_bar, 683 scontrol->readback_offset, 684 cdata->chanv, send_bytes); 685 686 else 687 snd_sof_dsp_block_read(sdev, sdev->mmio_bar, 688 scontrol->readback_offset, 689 cdata->chanv, send_bytes); 690 return 0; 691 } 692 693 cdata->rhdr.hdr.cmd = SOF_IPC_GLB_COMP_MSG | ipc_cmd; 694 cdata->cmd = ctrl_cmd; 695 cdata->type = ctrl_type; 696 cdata->comp_id = scontrol->comp_id; 697 cdata->msg_index = 0; 698 699 /* calculate header and data size */ 700 switch (cdata->type) { 701 case SOF_CTRL_TYPE_VALUE_CHAN_GET: 702 case SOF_CTRL_TYPE_VALUE_CHAN_SET: 703 sparams.msg_bytes = scontrol->num_channels * 704 sizeof(struct sof_ipc_ctrl_value_chan); 705 sparams.hdr_bytes = sizeof(struct sof_ipc_ctrl_data); 706 sparams.elems = scontrol->num_channels; 707 break; 708 case SOF_CTRL_TYPE_VALUE_COMP_GET: 709 case SOF_CTRL_TYPE_VALUE_COMP_SET: 710 sparams.msg_bytes = scontrol->num_channels * 711 sizeof(struct sof_ipc_ctrl_value_comp); 712 sparams.hdr_bytes = sizeof(struct sof_ipc_ctrl_data); 713 sparams.elems = scontrol->num_channels; 714 break; 715 case SOF_CTRL_TYPE_DATA_GET: 716 case SOF_CTRL_TYPE_DATA_SET: 717 sparams.msg_bytes = cdata->data->size; 718 sparams.hdr_bytes = sizeof(struct sof_ipc_ctrl_data) + 719 sizeof(struct sof_abi_hdr); 720 sparams.elems = cdata->data->size; 721 break; 722 default: 723 return -EINVAL; 724 } 725 726 cdata->rhdr.hdr.size = sparams.msg_bytes + sparams.hdr_bytes; 727 cdata->num_elems = sparams.elems; 728 cdata->elems_remaining = 0; 729 730 /* send normal size ipc in one part */ 731 if (cdata->rhdr.hdr.size <= SOF_IPC_MSG_MAX_SIZE) { 732 err = sof_ipc_tx_message(sdev->ipc, cdata->rhdr.hdr.cmd, cdata, 733 cdata->rhdr.hdr.size, cdata, 734 cdata->rhdr.hdr.size); 735 736 if (err < 0) 737 dev_err(sdev->dev, "error: set/get ctrl ipc comp %d\n", 738 cdata->comp_id); 739 740 return err; 741 } 742 743 /* data is bigger than max ipc size, chop into smaller pieces */ 744 dev_dbg(sdev->dev, "large ipc size %u, control size %u\n", 745 cdata->rhdr.hdr.size, scontrol->size); 746 747 /* large messages is only supported from ABI 3.3.0 onwards */ 748 if (v->abi_version < SOF_ABI_VER(3, 3, 0)) { 749 dev_err(sdev->dev, "error: incompatible FW ABI version\n"); 750 return -EINVAL; 751 } 752 753 err = sof_set_get_large_ctrl_data(sdev, cdata, &sparams, send); 754 755 if (err < 0) 756 dev_err(sdev->dev, "error: set/get large ctrl ipc comp %d\n", 757 cdata->comp_id); 758 759 return err; 760 } 761 EXPORT_SYMBOL(snd_sof_ipc_set_get_comp_data); 762 763 /* 764 * IPC layer enumeration. 765 */ 766 767 int snd_sof_dsp_mailbox_init(struct snd_sof_dev *sdev, u32 dspbox, 768 size_t dspbox_size, u32 hostbox, 769 size_t hostbox_size) 770 { 771 sdev->dsp_box.offset = dspbox; 772 sdev->dsp_box.size = dspbox_size; 773 sdev->host_box.offset = hostbox; 774 sdev->host_box.size = hostbox_size; 775 return 0; 776 } 777 EXPORT_SYMBOL(snd_sof_dsp_mailbox_init); 778 779 int snd_sof_ipc_valid(struct snd_sof_dev *sdev) 780 { 781 struct sof_ipc_fw_ready *ready = &sdev->fw_ready; 782 struct sof_ipc_fw_version *v = &ready->version; 783 784 dev_info(sdev->dev, 785 "Firmware info: version %d:%d:%d-%s\n", v->major, v->minor, 786 v->micro, v->tag); 787 dev_info(sdev->dev, 788 "Firmware: ABI %d:%d:%d Kernel ABI %d:%d:%d\n", 789 SOF_ABI_VERSION_MAJOR(v->abi_version), 790 SOF_ABI_VERSION_MINOR(v->abi_version), 791 SOF_ABI_VERSION_PATCH(v->abi_version), 792 SOF_ABI_MAJOR, SOF_ABI_MINOR, SOF_ABI_PATCH); 793 794 if (SOF_ABI_VERSION_INCOMPATIBLE(SOF_ABI_VERSION, v->abi_version)) { 795 dev_err(sdev->dev, "error: incompatible FW ABI version\n"); 796 return -EINVAL; 797 } 798 799 if (v->abi_version > SOF_ABI_VERSION) { 800 if (!IS_ENABLED(CONFIG_SND_SOC_SOF_STRICT_ABI_CHECKS)) { 801 dev_warn(sdev->dev, "warn: FW ABI is more recent than kernel\n"); 802 } else { 803 dev_err(sdev->dev, "error: FW ABI is more recent than kernel\n"); 804 return -EINVAL; 805 } 806 } 807 808 if (ready->flags & SOF_IPC_INFO_BUILD) { 809 dev_info(sdev->dev, 810 "Firmware debug build %d on %s-%s - options:\n" 811 " GDB: %s\n" 812 " lock debug: %s\n" 813 " lock vdebug: %s\n", 814 v->build, v->date, v->time, 815 (ready->flags & SOF_IPC_INFO_GDB) ? 816 "enabled" : "disabled", 817 (ready->flags & SOF_IPC_INFO_LOCKS) ? 818 "enabled" : "disabled", 819 (ready->flags & SOF_IPC_INFO_LOCKSV) ? 820 "enabled" : "disabled"); 821 } 822 823 /* copy the fw_version into debugfs at first boot */ 824 memcpy(&sdev->fw_version, v, sizeof(*v)); 825 826 return 0; 827 } 828 EXPORT_SYMBOL(snd_sof_ipc_valid); 829 830 struct snd_sof_ipc *snd_sof_ipc_init(struct snd_sof_dev *sdev) 831 { 832 struct snd_sof_ipc *ipc; 833 struct snd_sof_ipc_msg *msg; 834 835 ipc = devm_kzalloc(sdev->dev, sizeof(*ipc), GFP_KERNEL); 836 if (!ipc) 837 return NULL; 838 839 mutex_init(&ipc->tx_mutex); 840 ipc->sdev = sdev; 841 msg = &ipc->msg; 842 843 /* indicate that we aren't sending a message ATM */ 844 msg->ipc_complete = true; 845 846 /* pre-allocate message data */ 847 msg->msg_data = devm_kzalloc(sdev->dev, SOF_IPC_MSG_MAX_SIZE, 848 GFP_KERNEL); 849 if (!msg->msg_data) 850 return NULL; 851 852 msg->reply_data = devm_kzalloc(sdev->dev, SOF_IPC_MSG_MAX_SIZE, 853 GFP_KERNEL); 854 if (!msg->reply_data) 855 return NULL; 856 857 init_waitqueue_head(&msg->waitq); 858 859 return ipc; 860 } 861 EXPORT_SYMBOL(snd_sof_ipc_init); 862 863 void snd_sof_ipc_free(struct snd_sof_dev *sdev) 864 { 865 struct snd_sof_ipc *ipc = sdev->ipc; 866 867 if (!ipc) 868 return; 869 870 /* disable sending of ipc's */ 871 mutex_lock(&ipc->tx_mutex); 872 ipc->disable_ipc_tx = true; 873 mutex_unlock(&ipc->tx_mutex); 874 } 875 EXPORT_SYMBOL(snd_sof_ipc_free); 876