1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 // 3 // Copyright(c) 2020 Intel Corporation. All rights reserved. 4 // 5 // Authors: Ranjani Sridharan <ranjani.sridharan@linux.intel.com> 6 // 7 8 /* 9 * Hardware interface for audio DSP on Tigerlake. 10 */ 11 12 #include "../ops.h" 13 #include "hda.h" 14 #include "hda-ipc.h" 15 #include "../sof-audio.h" 16 17 static const struct snd_sof_debugfs_map tgl_dsp_debugfs[] = { 18 {"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS}, 19 {"pp", HDA_DSP_PP_BAR, 0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS}, 20 {"dsp", HDA_DSP_BAR, 0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS}, 21 }; 22 23 /* Tigerlake ops */ 24 const struct snd_sof_dsp_ops sof_tgl_ops = { 25 /* probe/remove/shutdown */ 26 .probe = hda_dsp_probe, 27 .remove = hda_dsp_remove, 28 .shutdown = hda_dsp_shutdown, 29 30 /* Register IO */ 31 .write = sof_io_write, 32 .read = sof_io_read, 33 .write64 = sof_io_write64, 34 .read64 = sof_io_read64, 35 36 /* Block IO */ 37 .block_read = sof_block_read, 38 .block_write = sof_block_write, 39 40 /* Mailbox IO */ 41 .mailbox_read = sof_mailbox_read, 42 .mailbox_write = sof_mailbox_write, 43 44 /* doorbell */ 45 .irq_thread = cnl_ipc_irq_thread, 46 47 /* ipc */ 48 .send_msg = cnl_ipc_send_msg, 49 .fw_ready = sof_fw_ready, 50 .get_mailbox_offset = hda_dsp_ipc_get_mailbox_offset, 51 .get_window_offset = hda_dsp_ipc_get_window_offset, 52 53 .ipc_msg_data = hda_ipc_msg_data, 54 .ipc_pcm_params = hda_ipc_pcm_params, 55 56 /* machine driver */ 57 .machine_select = hda_machine_select, 58 .machine_register = sof_machine_register, 59 .machine_unregister = sof_machine_unregister, 60 .set_mach_params = hda_set_mach_params, 61 62 /* debug */ 63 .debug_map = tgl_dsp_debugfs, 64 .debug_map_count = ARRAY_SIZE(tgl_dsp_debugfs), 65 .dbg_dump = hda_dsp_dump, 66 .ipc_dump = cnl_ipc_dump, 67 .debugfs_add_region_item = snd_sof_debugfs_add_region_item_iomem, 68 69 /* stream callbacks */ 70 .pcm_open = hda_dsp_pcm_open, 71 .pcm_close = hda_dsp_pcm_close, 72 .pcm_hw_params = hda_dsp_pcm_hw_params, 73 .pcm_hw_free = hda_dsp_stream_hw_free, 74 .pcm_trigger = hda_dsp_pcm_trigger, 75 .pcm_pointer = hda_dsp_pcm_pointer, 76 77 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_PROBES) 78 /* probe callbacks */ 79 .probe_assign = hda_probe_compr_assign, 80 .probe_free = hda_probe_compr_free, 81 .probe_set_params = hda_probe_compr_set_params, 82 .probe_trigger = hda_probe_compr_trigger, 83 .probe_pointer = hda_probe_compr_pointer, 84 #endif 85 86 /* firmware loading */ 87 .load_firmware = snd_sof_load_firmware_raw, 88 89 /* pre/post fw run */ 90 .pre_fw_run = hda_dsp_pre_fw_run, 91 .post_fw_run = hda_dsp_post_fw_run, 92 93 /* parse platform specific extended manifest */ 94 .parse_platform_ext_manifest = hda_dsp_ext_man_get_cavs_config_data, 95 96 /* dsp core power up/down */ 97 .core_power_up = hda_dsp_enable_core, 98 .core_power_down = hda_dsp_core_reset_power_down, 99 100 /* firmware run */ 101 .run = hda_dsp_cl_boot_firmware_iccmax, 102 103 /* trace callback */ 104 .trace_init = hda_dsp_trace_init, 105 .trace_release = hda_dsp_trace_release, 106 .trace_trigger = hda_dsp_trace_trigger, 107 108 /* DAI drivers */ 109 .drv = skl_dai, 110 .num_drv = SOF_SKL_NUM_DAIS, 111 112 /* PM */ 113 .suspend = hda_dsp_suspend, 114 .resume = hda_dsp_resume, 115 .runtime_suspend = hda_dsp_runtime_suspend, 116 .runtime_resume = hda_dsp_runtime_resume, 117 .runtime_idle = hda_dsp_runtime_idle, 118 .set_hw_params_upon_resume = hda_dsp_set_hw_params_upon_resume, 119 .set_power_state = hda_dsp_set_power_state, 120 121 /* ALSA HW info flags */ 122 .hw_info = SNDRV_PCM_INFO_MMAP | 123 SNDRV_PCM_INFO_MMAP_VALID | 124 SNDRV_PCM_INFO_INTERLEAVED | 125 SNDRV_PCM_INFO_PAUSE | 126 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP, 127 128 .dsp_arch_ops = &sof_xtensa_arch_ops, 129 }; 130 EXPORT_SYMBOL_NS(sof_tgl_ops, SND_SOC_SOF_INTEL_HDA_COMMON); 131 132 const struct sof_intel_dsp_desc tgl_chip_info = { 133 /* Tigerlake , Alderlake */ 134 .cores_num = 4, 135 .init_core_mask = 1, 136 .host_managed_cores_mask = BIT(0), 137 .ipc_req = CNL_DSP_REG_HIPCIDR, 138 .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY, 139 .ipc_ack = CNL_DSP_REG_HIPCIDA, 140 .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE, 141 .ipc_ctl = CNL_DSP_REG_HIPCCTL, 142 .rom_init_timeout = 300, 143 .ssp_count = ICL_SSP_COUNT, 144 .ssp_base_offset = CNL_SSP_BASE_OFFSET, 145 .sdw_shim_base = SDW_SHIM_BASE, 146 .sdw_alh_base = SDW_ALH_BASE, 147 .check_sdw_irq = hda_common_check_sdw_irq, 148 }; 149 EXPORT_SYMBOL_NS(tgl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); 150 151 const struct sof_intel_dsp_desc tglh_chip_info = { 152 /* Tigerlake-H */ 153 .cores_num = 2, 154 .init_core_mask = 1, 155 .host_managed_cores_mask = BIT(0), 156 .ipc_req = CNL_DSP_REG_HIPCIDR, 157 .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY, 158 .ipc_ack = CNL_DSP_REG_HIPCIDA, 159 .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE, 160 .ipc_ctl = CNL_DSP_REG_HIPCCTL, 161 .rom_init_timeout = 300, 162 .ssp_count = ICL_SSP_COUNT, 163 .ssp_base_offset = CNL_SSP_BASE_OFFSET, 164 .sdw_shim_base = SDW_SHIM_BASE, 165 .sdw_alh_base = SDW_ALH_BASE, 166 .check_sdw_irq = hda_common_check_sdw_irq, 167 }; 168 EXPORT_SYMBOL_NS(tglh_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); 169 170 const struct sof_intel_dsp_desc ehl_chip_info = { 171 /* Elkhartlake */ 172 .cores_num = 4, 173 .init_core_mask = 1, 174 .host_managed_cores_mask = BIT(0), 175 .ipc_req = CNL_DSP_REG_HIPCIDR, 176 .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY, 177 .ipc_ack = CNL_DSP_REG_HIPCIDA, 178 .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE, 179 .ipc_ctl = CNL_DSP_REG_HIPCCTL, 180 .rom_init_timeout = 300, 181 .ssp_count = ICL_SSP_COUNT, 182 .ssp_base_offset = CNL_SSP_BASE_OFFSET, 183 .sdw_shim_base = SDW_SHIM_BASE, 184 .sdw_alh_base = SDW_ALH_BASE, 185 .check_sdw_irq = hda_common_check_sdw_irq, 186 }; 187 EXPORT_SYMBOL_NS(ehl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); 188 189 const struct sof_intel_dsp_desc adls_chip_info = { 190 /* Alderlake-S */ 191 .cores_num = 2, 192 .init_core_mask = BIT(0), 193 .host_managed_cores_mask = BIT(0), 194 .ipc_req = CNL_DSP_REG_HIPCIDR, 195 .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY, 196 .ipc_ack = CNL_DSP_REG_HIPCIDA, 197 .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE, 198 .ipc_ctl = CNL_DSP_REG_HIPCCTL, 199 .rom_init_timeout = 300, 200 .ssp_count = ICL_SSP_COUNT, 201 .ssp_base_offset = CNL_SSP_BASE_OFFSET, 202 .sdw_shim_base = SDW_SHIM_BASE, 203 .sdw_alh_base = SDW_ALH_BASE, 204 .check_sdw_irq = hda_common_check_sdw_irq, 205 }; 206 EXPORT_SYMBOL_NS(adls_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); 207