1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 // 3 // Copyright(c) 2020 Intel Corporation. All rights reserved. 4 // 5 // Authors: Ranjani Sridharan <ranjani.sridharan@linux.intel.com> 6 // 7 8 /* 9 * Hardware interface for audio DSP on Tigerlake. 10 */ 11 12 #include <sound/sof/ext_manifest4.h> 13 #include "../ipc4-priv.h" 14 #include "../ops.h" 15 #include "hda.h" 16 #include "hda-ipc.h" 17 #include "../sof-audio.h" 18 19 static const struct snd_sof_debugfs_map tgl_dsp_debugfs[] = { 20 {"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS}, 21 {"pp", HDA_DSP_PP_BAR, 0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS}, 22 {"dsp", HDA_DSP_BAR, 0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS}, 23 }; 24 25 static int tgl_dsp_core_get(struct snd_sof_dev *sdev, int core) 26 { 27 const struct sof_ipc_pm_ops *pm_ops = sdev->ipc->ops->pm; 28 29 /* power up primary core if not already powered up and return */ 30 if (core == SOF_DSP_PRIMARY_CORE) 31 return hda_dsp_enable_core(sdev, BIT(core)); 32 33 if (pm_ops->set_core_state) 34 return pm_ops->set_core_state(sdev, core, true); 35 36 return 0; 37 } 38 39 static int tgl_dsp_core_put(struct snd_sof_dev *sdev, int core) 40 { 41 const struct sof_ipc_pm_ops *pm_ops = sdev->ipc->ops->pm; 42 43 /* power down primary core and return */ 44 if (core == SOF_DSP_PRIMARY_CORE) 45 return hda_dsp_core_reset_power_down(sdev, BIT(core)); 46 47 if (pm_ops->set_core_state) 48 return pm_ops->set_core_state(sdev, core, false); 49 50 return 0; 51 } 52 53 /* Tigerlake ops */ 54 struct snd_sof_dsp_ops sof_tgl_ops; 55 EXPORT_SYMBOL_NS(sof_tgl_ops, SND_SOC_SOF_INTEL_HDA_COMMON); 56 57 int sof_tgl_ops_init(struct snd_sof_dev *sdev) 58 { 59 /* common defaults */ 60 memcpy(&sof_tgl_ops, &sof_hda_common_ops, sizeof(struct snd_sof_dsp_ops)); 61 62 /* probe/remove/shutdown */ 63 sof_tgl_ops.shutdown = hda_dsp_shutdown; 64 65 if (sdev->pdata->ipc_type == SOF_IPC) { 66 /* doorbell */ 67 sof_tgl_ops.irq_thread = cnl_ipc_irq_thread; 68 69 /* ipc */ 70 sof_tgl_ops.send_msg = cnl_ipc_send_msg; 71 } 72 73 if (sdev->pdata->ipc_type == SOF_INTEL_IPC4) { 74 struct sof_ipc4_fw_data *ipc4_data; 75 76 sdev->private = devm_kzalloc(sdev->dev, sizeof(*ipc4_data), GFP_KERNEL); 77 if (!sdev->private) 78 return -ENOMEM; 79 80 ipc4_data = sdev->private; 81 ipc4_data->manifest_fw_hdr_offset = SOF_MAN4_FW_HDR_OFFSET; 82 83 ipc4_data->mtrace_type = SOF_IPC4_MTRACE_INTEL_CAVS_2; 84 85 /* doorbell */ 86 sof_tgl_ops.irq_thread = cnl_ipc4_irq_thread; 87 88 /* ipc */ 89 sof_tgl_ops.send_msg = cnl_ipc4_send_msg; 90 } 91 92 /* set DAI driver ops */ 93 hda_set_dai_drv_ops(sdev, &sof_tgl_ops); 94 95 /* debug */ 96 sof_tgl_ops.debug_map = tgl_dsp_debugfs; 97 sof_tgl_ops.debug_map_count = ARRAY_SIZE(tgl_dsp_debugfs); 98 sof_tgl_ops.ipc_dump = cnl_ipc_dump; 99 100 /* pre/post fw run */ 101 sof_tgl_ops.post_fw_run = hda_dsp_post_fw_run; 102 103 /* firmware run */ 104 sof_tgl_ops.run = hda_dsp_cl_boot_firmware_iccmax; 105 106 /* dsp core get/put */ 107 sof_tgl_ops.core_get = tgl_dsp_core_get; 108 sof_tgl_ops.core_put = tgl_dsp_core_put; 109 110 return 0; 111 }; 112 EXPORT_SYMBOL_NS(sof_tgl_ops_init, SND_SOC_SOF_INTEL_HDA_COMMON); 113 114 const struct sof_intel_dsp_desc tgl_chip_info = { 115 /* Tigerlake , Alderlake */ 116 .cores_num = 4, 117 .init_core_mask = 1, 118 .host_managed_cores_mask = BIT(0), 119 .ipc_req = CNL_DSP_REG_HIPCIDR, 120 .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY, 121 .ipc_ack = CNL_DSP_REG_HIPCIDA, 122 .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE, 123 .ipc_ctl = CNL_DSP_REG_HIPCCTL, 124 .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS, 125 .rom_init_timeout = 300, 126 .ssp_count = TGL_SSP_COUNT, 127 .ssp_base_offset = CNL_SSP_BASE_OFFSET, 128 .sdw_shim_base = SDW_SHIM_BASE, 129 .sdw_alh_base = SDW_ALH_BASE, 130 .check_sdw_irq = hda_common_check_sdw_irq, 131 .check_ipc_irq = hda_dsp_check_ipc_irq, 132 .cl_init = cl_dsp_init, 133 .power_down_dsp = hda_power_down_dsp, 134 .hw_ip_version = SOF_INTEL_CAVS_2_5, 135 }; 136 EXPORT_SYMBOL_NS(tgl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); 137 138 const struct sof_intel_dsp_desc tglh_chip_info = { 139 /* Tigerlake-H */ 140 .cores_num = 2, 141 .init_core_mask = 1, 142 .host_managed_cores_mask = BIT(0), 143 .ipc_req = CNL_DSP_REG_HIPCIDR, 144 .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY, 145 .ipc_ack = CNL_DSP_REG_HIPCIDA, 146 .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE, 147 .ipc_ctl = CNL_DSP_REG_HIPCCTL, 148 .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS, 149 .rom_init_timeout = 300, 150 .ssp_count = TGL_SSP_COUNT, 151 .ssp_base_offset = CNL_SSP_BASE_OFFSET, 152 .sdw_shim_base = SDW_SHIM_BASE, 153 .sdw_alh_base = SDW_ALH_BASE, 154 .check_sdw_irq = hda_common_check_sdw_irq, 155 .check_ipc_irq = hda_dsp_check_ipc_irq, 156 .cl_init = cl_dsp_init, 157 .power_down_dsp = hda_power_down_dsp, 158 .hw_ip_version = SOF_INTEL_CAVS_2_5, 159 }; 160 EXPORT_SYMBOL_NS(tglh_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); 161 162 const struct sof_intel_dsp_desc ehl_chip_info = { 163 /* Elkhartlake */ 164 .cores_num = 4, 165 .init_core_mask = 1, 166 .host_managed_cores_mask = BIT(0), 167 .ipc_req = CNL_DSP_REG_HIPCIDR, 168 .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY, 169 .ipc_ack = CNL_DSP_REG_HIPCIDA, 170 .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE, 171 .ipc_ctl = CNL_DSP_REG_HIPCCTL, 172 .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS, 173 .rom_init_timeout = 300, 174 .ssp_count = TGL_SSP_COUNT, 175 .ssp_base_offset = CNL_SSP_BASE_OFFSET, 176 .sdw_shim_base = SDW_SHIM_BASE, 177 .sdw_alh_base = SDW_ALH_BASE, 178 .check_sdw_irq = hda_common_check_sdw_irq, 179 .check_ipc_irq = hda_dsp_check_ipc_irq, 180 .cl_init = cl_dsp_init, 181 .power_down_dsp = hda_power_down_dsp, 182 .hw_ip_version = SOF_INTEL_CAVS_2_5, 183 }; 184 EXPORT_SYMBOL_NS(ehl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); 185 186 const struct sof_intel_dsp_desc adls_chip_info = { 187 /* Alderlake-S */ 188 .cores_num = 2, 189 .init_core_mask = BIT(0), 190 .host_managed_cores_mask = BIT(0), 191 .ipc_req = CNL_DSP_REG_HIPCIDR, 192 .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY, 193 .ipc_ack = CNL_DSP_REG_HIPCIDA, 194 .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE, 195 .ipc_ctl = CNL_DSP_REG_HIPCCTL, 196 .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS, 197 .rom_init_timeout = 300, 198 .ssp_count = TGL_SSP_COUNT, 199 .ssp_base_offset = CNL_SSP_BASE_OFFSET, 200 .sdw_shim_base = SDW_SHIM_BASE, 201 .sdw_alh_base = SDW_ALH_BASE, 202 .check_sdw_irq = hda_common_check_sdw_irq, 203 .check_ipc_irq = hda_dsp_check_ipc_irq, 204 .cl_init = cl_dsp_init, 205 .power_down_dsp = hda_power_down_dsp, 206 .hw_ip_version = SOF_INTEL_CAVS_2_5, 207 }; 208 EXPORT_SYMBOL_NS(adls_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); 209