1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 // 3 // Copyright(c) 2020 Intel Corporation. All rights reserved. 4 // 5 // Authors: Ranjani Sridharan <ranjani.sridharan@linux.intel.com> 6 // 7 8 /* 9 * Hardware interface for audio DSP on Tigerlake. 10 */ 11 12 #include <sound/sof/ext_manifest4.h> 13 #include "../ipc4-priv.h" 14 #include "../ops.h" 15 #include "hda.h" 16 #include "hda-ipc.h" 17 #include "../sof-audio.h" 18 19 static const struct snd_sof_debugfs_map tgl_dsp_debugfs[] = { 20 {"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS}, 21 {"pp", HDA_DSP_PP_BAR, 0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS}, 22 {"dsp", HDA_DSP_BAR, 0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS}, 23 }; 24 25 static int tgl_dsp_core_get(struct snd_sof_dev *sdev, int core) 26 { 27 const struct sof_ipc_pm_ops *pm_ops = sdev->ipc->ops->pm; 28 29 /* power up primary core if not already powered up and return */ 30 if (core == SOF_DSP_PRIMARY_CORE) 31 return hda_dsp_enable_core(sdev, BIT(core)); 32 33 if (pm_ops->set_core_state) 34 return pm_ops->set_core_state(sdev, core, true); 35 36 return 0; 37 } 38 39 static int tgl_dsp_core_put(struct snd_sof_dev *sdev, int core) 40 { 41 const struct sof_ipc_pm_ops *pm_ops = sdev->ipc->ops->pm; 42 43 /* power down primary core and return */ 44 if (core == SOF_DSP_PRIMARY_CORE) 45 return hda_dsp_core_reset_power_down(sdev, BIT(core)); 46 47 if (pm_ops->set_core_state) 48 return pm_ops->set_core_state(sdev, core, false); 49 50 return 0; 51 } 52 53 /* Tigerlake ops */ 54 struct snd_sof_dsp_ops sof_tgl_ops; 55 EXPORT_SYMBOL_NS(sof_tgl_ops, SND_SOC_SOF_INTEL_HDA_COMMON); 56 57 int sof_tgl_ops_init(struct snd_sof_dev *sdev) 58 { 59 /* common defaults */ 60 memcpy(&sof_tgl_ops, &sof_hda_common_ops, sizeof(struct snd_sof_dsp_ops)); 61 62 /* probe/remove/shutdown */ 63 sof_tgl_ops.shutdown = hda_dsp_shutdown; 64 65 if (sdev->pdata->ipc_type == SOF_IPC) { 66 /* doorbell */ 67 sof_tgl_ops.irq_thread = cnl_ipc_irq_thread; 68 69 /* ipc */ 70 sof_tgl_ops.send_msg = cnl_ipc_send_msg; 71 72 /* debug */ 73 sof_tgl_ops.ipc_dump = cnl_ipc_dump; 74 } 75 76 if (sdev->pdata->ipc_type == SOF_INTEL_IPC4) { 77 struct sof_ipc4_fw_data *ipc4_data; 78 79 sdev->private = devm_kzalloc(sdev->dev, sizeof(*ipc4_data), GFP_KERNEL); 80 if (!sdev->private) 81 return -ENOMEM; 82 83 ipc4_data = sdev->private; 84 ipc4_data->manifest_fw_hdr_offset = SOF_MAN4_FW_HDR_OFFSET; 85 86 ipc4_data->mtrace_type = SOF_IPC4_MTRACE_INTEL_CAVS_2; 87 88 /* doorbell */ 89 sof_tgl_ops.irq_thread = cnl_ipc4_irq_thread; 90 91 /* ipc */ 92 sof_tgl_ops.send_msg = cnl_ipc4_send_msg; 93 94 /* debug */ 95 sof_tgl_ops.ipc_dump = cnl_ipc4_dump; 96 } 97 98 /* set DAI driver ops */ 99 hda_set_dai_drv_ops(sdev, &sof_tgl_ops); 100 101 /* debug */ 102 sof_tgl_ops.debug_map = tgl_dsp_debugfs; 103 sof_tgl_ops.debug_map_count = ARRAY_SIZE(tgl_dsp_debugfs); 104 105 /* pre/post fw run */ 106 sof_tgl_ops.post_fw_run = hda_dsp_post_fw_run; 107 108 /* firmware run */ 109 sof_tgl_ops.run = hda_dsp_cl_boot_firmware_iccmax; 110 111 /* dsp core get/put */ 112 sof_tgl_ops.core_get = tgl_dsp_core_get; 113 sof_tgl_ops.core_put = tgl_dsp_core_put; 114 115 return 0; 116 }; 117 EXPORT_SYMBOL_NS(sof_tgl_ops_init, SND_SOC_SOF_INTEL_HDA_COMMON); 118 119 const struct sof_intel_dsp_desc tgl_chip_info = { 120 /* Tigerlake , Alderlake */ 121 .cores_num = 4, 122 .init_core_mask = 1, 123 .host_managed_cores_mask = BIT(0), 124 .ipc_req = CNL_DSP_REG_HIPCIDR, 125 .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY, 126 .ipc_ack = CNL_DSP_REG_HIPCIDA, 127 .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE, 128 .ipc_ctl = CNL_DSP_REG_HIPCCTL, 129 .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS, 130 .rom_init_timeout = 300, 131 .ssp_count = TGL_SSP_COUNT, 132 .ssp_base_offset = CNL_SSP_BASE_OFFSET, 133 .sdw_shim_base = SDW_SHIM_BASE, 134 .sdw_alh_base = SDW_ALH_BASE, 135 .check_sdw_irq = hda_common_check_sdw_irq, 136 .check_ipc_irq = hda_dsp_check_ipc_irq, 137 .cl_init = cl_dsp_init, 138 .hw_ip_version = SOF_INTEL_CAVS_2_5, 139 }; 140 EXPORT_SYMBOL_NS(tgl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); 141 142 const struct sof_intel_dsp_desc tglh_chip_info = { 143 /* Tigerlake-H */ 144 .cores_num = 2, 145 .init_core_mask = 1, 146 .host_managed_cores_mask = BIT(0), 147 .ipc_req = CNL_DSP_REG_HIPCIDR, 148 .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY, 149 .ipc_ack = CNL_DSP_REG_HIPCIDA, 150 .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE, 151 .ipc_ctl = CNL_DSP_REG_HIPCCTL, 152 .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS, 153 .rom_init_timeout = 300, 154 .ssp_count = TGL_SSP_COUNT, 155 .ssp_base_offset = CNL_SSP_BASE_OFFSET, 156 .sdw_shim_base = SDW_SHIM_BASE, 157 .sdw_alh_base = SDW_ALH_BASE, 158 .check_sdw_irq = hda_common_check_sdw_irq, 159 .check_ipc_irq = hda_dsp_check_ipc_irq, 160 .cl_init = cl_dsp_init, 161 .hw_ip_version = SOF_INTEL_CAVS_2_5, 162 }; 163 EXPORT_SYMBOL_NS(tglh_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); 164 165 const struct sof_intel_dsp_desc ehl_chip_info = { 166 /* Elkhartlake */ 167 .cores_num = 4, 168 .init_core_mask = 1, 169 .host_managed_cores_mask = BIT(0), 170 .ipc_req = CNL_DSP_REG_HIPCIDR, 171 .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY, 172 .ipc_ack = CNL_DSP_REG_HIPCIDA, 173 .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE, 174 .ipc_ctl = CNL_DSP_REG_HIPCCTL, 175 .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS, 176 .rom_init_timeout = 300, 177 .ssp_count = TGL_SSP_COUNT, 178 .ssp_base_offset = CNL_SSP_BASE_OFFSET, 179 .sdw_shim_base = SDW_SHIM_BASE, 180 .sdw_alh_base = SDW_ALH_BASE, 181 .check_sdw_irq = hda_common_check_sdw_irq, 182 .check_ipc_irq = hda_dsp_check_ipc_irq, 183 .cl_init = cl_dsp_init, 184 .hw_ip_version = SOF_INTEL_CAVS_2_5, 185 }; 186 EXPORT_SYMBOL_NS(ehl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); 187 188 const struct sof_intel_dsp_desc adls_chip_info = { 189 /* Alderlake-S */ 190 .cores_num = 2, 191 .init_core_mask = BIT(0), 192 .host_managed_cores_mask = BIT(0), 193 .ipc_req = CNL_DSP_REG_HIPCIDR, 194 .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY, 195 .ipc_ack = CNL_DSP_REG_HIPCIDA, 196 .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE, 197 .ipc_ctl = CNL_DSP_REG_HIPCCTL, 198 .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS, 199 .rom_init_timeout = 300, 200 .ssp_count = TGL_SSP_COUNT, 201 .ssp_base_offset = CNL_SSP_BASE_OFFSET, 202 .sdw_shim_base = SDW_SHIM_BASE, 203 .sdw_alh_base = SDW_ALH_BASE, 204 .check_sdw_irq = hda_common_check_sdw_irq, 205 .check_ipc_irq = hda_dsp_check_ipc_irq, 206 .cl_init = cl_dsp_init, 207 .hw_ip_version = SOF_INTEL_CAVS_2_5, 208 }; 209 EXPORT_SYMBOL_NS(adls_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); 210