1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 // 3 // Copyright(c) 2020 Intel Corporation. All rights reserved. 4 // 5 // Authors: Ranjani Sridharan <ranjani.sridharan@linux.intel.com> 6 // 7 8 /* 9 * Hardware interface for audio DSP on Tigerlake. 10 */ 11 12 #include "../ops.h" 13 #include "hda.h" 14 #include "hda-ipc.h" 15 #include "../sof-audio.h" 16 17 static const struct snd_sof_debugfs_map tgl_dsp_debugfs[] = { 18 {"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS}, 19 {"pp", HDA_DSP_PP_BAR, 0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS}, 20 {"dsp", HDA_DSP_BAR, 0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS}, 21 }; 22 23 static int tgl_dsp_core_get(struct snd_sof_dev *sdev, int core) 24 { 25 struct sof_ipc_pm_core_config pm_core_config = { 26 .hdr = { 27 .cmd = SOF_IPC_GLB_PM_MSG | SOF_IPC_PM_CORE_ENABLE, 28 .size = sizeof(pm_core_config), 29 }, 30 .enable_mask = sdev->enabled_cores_mask | BIT(core), 31 }; 32 33 /* power up primary core if not already powered up and return */ 34 if (core == SOF_DSP_PRIMARY_CORE) 35 return hda_dsp_enable_core(sdev, BIT(core)); 36 37 /* notify DSP for secondary cores */ 38 return sof_ipc_tx_message(sdev->ipc, pm_core_config.hdr.cmd, 39 &pm_core_config, sizeof(pm_core_config), 40 &pm_core_config, sizeof(pm_core_config)); 41 } 42 43 static int tgl_dsp_core_put(struct snd_sof_dev *sdev, int core) 44 { 45 struct sof_ipc_pm_core_config pm_core_config = { 46 .hdr = { 47 .cmd = SOF_IPC_GLB_PM_MSG | SOF_IPC_PM_CORE_ENABLE, 48 .size = sizeof(pm_core_config), 49 }, 50 .enable_mask = sdev->enabled_cores_mask & ~BIT(core), 51 }; 52 53 /* power down primary core and return */ 54 if (core == SOF_DSP_PRIMARY_CORE) 55 return hda_dsp_core_reset_power_down(sdev, BIT(core)); 56 57 /* notify DSP for secondary cores */ 58 return sof_ipc_tx_message(sdev->ipc, pm_core_config.hdr.cmd, 59 &pm_core_config, sizeof(pm_core_config), 60 &pm_core_config, sizeof(pm_core_config)); 61 } 62 63 /* Tigerlake ops */ 64 const struct snd_sof_dsp_ops sof_tgl_ops = { 65 /* probe/remove/shutdown */ 66 .probe = hda_dsp_probe, 67 .remove = hda_dsp_remove, 68 .shutdown = hda_dsp_shutdown, 69 70 /* Register IO */ 71 .write = sof_io_write, 72 .read = sof_io_read, 73 .write64 = sof_io_write64, 74 .read64 = sof_io_read64, 75 76 /* Block IO */ 77 .block_read = sof_block_read, 78 .block_write = sof_block_write, 79 80 /* Mailbox IO */ 81 .mailbox_read = sof_mailbox_read, 82 .mailbox_write = sof_mailbox_write, 83 84 /* doorbell */ 85 .irq_thread = cnl_ipc_irq_thread, 86 87 /* ipc */ 88 .send_msg = cnl_ipc_send_msg, 89 .fw_ready = sof_fw_ready, 90 .get_mailbox_offset = hda_dsp_ipc_get_mailbox_offset, 91 .get_window_offset = hda_dsp_ipc_get_window_offset, 92 93 .ipc_msg_data = hda_ipc_msg_data, 94 .ipc_pcm_params = hda_ipc_pcm_params, 95 96 /* machine driver */ 97 .machine_select = hda_machine_select, 98 .machine_register = sof_machine_register, 99 .machine_unregister = sof_machine_unregister, 100 .set_mach_params = hda_set_mach_params, 101 102 /* debug */ 103 .debug_map = tgl_dsp_debugfs, 104 .debug_map_count = ARRAY_SIZE(tgl_dsp_debugfs), 105 .dbg_dump = hda_dsp_dump, 106 .ipc_dump = cnl_ipc_dump, 107 .debugfs_add_region_item = snd_sof_debugfs_add_region_item_iomem, 108 109 /* stream callbacks */ 110 .pcm_open = hda_dsp_pcm_open, 111 .pcm_close = hda_dsp_pcm_close, 112 .pcm_hw_params = hda_dsp_pcm_hw_params, 113 .pcm_hw_free = hda_dsp_stream_hw_free, 114 .pcm_trigger = hda_dsp_pcm_trigger, 115 .pcm_pointer = hda_dsp_pcm_pointer, 116 .pcm_ack = hda_dsp_pcm_ack, 117 118 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_PROBES) 119 /* probe callbacks */ 120 .probe_assign = hda_probe_compr_assign, 121 .probe_free = hda_probe_compr_free, 122 .probe_set_params = hda_probe_compr_set_params, 123 .probe_trigger = hda_probe_compr_trigger, 124 .probe_pointer = hda_probe_compr_pointer, 125 #endif 126 127 /* firmware loading */ 128 .load_firmware = snd_sof_load_firmware_raw, 129 130 /* pre/post fw run */ 131 .pre_fw_run = hda_dsp_pre_fw_run, 132 .post_fw_run = hda_dsp_post_fw_run, 133 134 /* parse platform specific extended manifest */ 135 .parse_platform_ext_manifest = hda_dsp_ext_man_get_cavs_config_data, 136 137 /* dsp core get/put */ 138 .core_get = tgl_dsp_core_get, 139 .core_put = tgl_dsp_core_put, 140 141 /* firmware run */ 142 .run = hda_dsp_cl_boot_firmware_iccmax, 143 144 /* trace callback */ 145 .trace_init = hda_dsp_trace_init, 146 .trace_release = hda_dsp_trace_release, 147 .trace_trigger = hda_dsp_trace_trigger, 148 149 /* DAI drivers */ 150 .drv = skl_dai, 151 .num_drv = SOF_SKL_NUM_DAIS, 152 153 /* PM */ 154 .suspend = hda_dsp_suspend, 155 .resume = hda_dsp_resume, 156 .runtime_suspend = hda_dsp_runtime_suspend, 157 .runtime_resume = hda_dsp_runtime_resume, 158 .runtime_idle = hda_dsp_runtime_idle, 159 .set_hw_params_upon_resume = hda_dsp_set_hw_params_upon_resume, 160 .set_power_state = hda_dsp_set_power_state, 161 162 /* ALSA HW info flags */ 163 .hw_info = SNDRV_PCM_INFO_MMAP | 164 SNDRV_PCM_INFO_MMAP_VALID | 165 SNDRV_PCM_INFO_INTERLEAVED | 166 SNDRV_PCM_INFO_PAUSE | 167 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP, 168 169 .dsp_arch_ops = &sof_xtensa_arch_ops, 170 }; 171 EXPORT_SYMBOL_NS(sof_tgl_ops, SND_SOC_SOF_INTEL_HDA_COMMON); 172 173 const struct sof_intel_dsp_desc tgl_chip_info = { 174 /* Tigerlake , Alderlake */ 175 .cores_num = 4, 176 .init_core_mask = 1, 177 .host_managed_cores_mask = BIT(0), 178 .ipc_req = CNL_DSP_REG_HIPCIDR, 179 .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY, 180 .ipc_ack = CNL_DSP_REG_HIPCIDA, 181 .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE, 182 .ipc_ctl = CNL_DSP_REG_HIPCCTL, 183 .rom_init_timeout = 300, 184 .ssp_count = ICL_SSP_COUNT, 185 .ssp_base_offset = CNL_SSP_BASE_OFFSET, 186 .sdw_shim_base = SDW_SHIM_BASE, 187 .sdw_alh_base = SDW_ALH_BASE, 188 .check_sdw_irq = hda_common_check_sdw_irq, 189 }; 190 EXPORT_SYMBOL_NS(tgl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); 191 192 const struct sof_intel_dsp_desc tglh_chip_info = { 193 /* Tigerlake-H */ 194 .cores_num = 2, 195 .init_core_mask = 1, 196 .host_managed_cores_mask = BIT(0), 197 .ipc_req = CNL_DSP_REG_HIPCIDR, 198 .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY, 199 .ipc_ack = CNL_DSP_REG_HIPCIDA, 200 .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE, 201 .ipc_ctl = CNL_DSP_REG_HIPCCTL, 202 .rom_init_timeout = 300, 203 .ssp_count = ICL_SSP_COUNT, 204 .ssp_base_offset = CNL_SSP_BASE_OFFSET, 205 .sdw_shim_base = SDW_SHIM_BASE, 206 .sdw_alh_base = SDW_ALH_BASE, 207 .check_sdw_irq = hda_common_check_sdw_irq, 208 }; 209 EXPORT_SYMBOL_NS(tglh_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); 210 211 const struct sof_intel_dsp_desc ehl_chip_info = { 212 /* Elkhartlake */ 213 .cores_num = 4, 214 .init_core_mask = 1, 215 .host_managed_cores_mask = BIT(0), 216 .ipc_req = CNL_DSP_REG_HIPCIDR, 217 .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY, 218 .ipc_ack = CNL_DSP_REG_HIPCIDA, 219 .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE, 220 .ipc_ctl = CNL_DSP_REG_HIPCCTL, 221 .rom_init_timeout = 300, 222 .ssp_count = ICL_SSP_COUNT, 223 .ssp_base_offset = CNL_SSP_BASE_OFFSET, 224 .sdw_shim_base = SDW_SHIM_BASE, 225 .sdw_alh_base = SDW_ALH_BASE, 226 .check_sdw_irq = hda_common_check_sdw_irq, 227 }; 228 EXPORT_SYMBOL_NS(ehl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); 229 230 const struct sof_intel_dsp_desc adls_chip_info = { 231 /* Alderlake-S */ 232 .cores_num = 2, 233 .init_core_mask = BIT(0), 234 .host_managed_cores_mask = BIT(0), 235 .ipc_req = CNL_DSP_REG_HIPCIDR, 236 .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY, 237 .ipc_ack = CNL_DSP_REG_HIPCIDA, 238 .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE, 239 .ipc_ctl = CNL_DSP_REG_HIPCCTL, 240 .rom_init_timeout = 300, 241 .ssp_count = ICL_SSP_COUNT, 242 .ssp_base_offset = CNL_SSP_BASE_OFFSET, 243 .sdw_shim_base = SDW_SHIM_BASE, 244 .sdw_alh_base = SDW_ALH_BASE, 245 .check_sdw_irq = hda_common_check_sdw_irq, 246 }; 247 EXPORT_SYMBOL_NS(adls_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); 248