1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 // 3 // Copyright(c) 2020 Intel Corporation. All rights reserved. 4 // 5 // Authors: Ranjani Sridharan <ranjani.sridharan@linux.intel.com> 6 // 7 8 /* 9 * Hardware interface for audio DSP on Tigerlake. 10 */ 11 12 #include "../ops.h" 13 #include "hda.h" 14 #include "hda-ipc.h" 15 #include "../sof-audio.h" 16 17 static const struct snd_sof_debugfs_map tgl_dsp_debugfs[] = { 18 {"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS}, 19 {"pp", HDA_DSP_PP_BAR, 0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS}, 20 {"dsp", HDA_DSP_BAR, 0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS}, 21 }; 22 23 /* Tigerlake ops */ 24 const struct snd_sof_dsp_ops sof_tgl_ops = { 25 /* probe/remove/shutdown */ 26 .probe = hda_dsp_probe, 27 .remove = hda_dsp_remove, 28 .shutdown = hda_dsp_remove, 29 30 /* Register IO */ 31 .write = sof_io_write, 32 .read = sof_io_read, 33 .write64 = sof_io_write64, 34 .read64 = sof_io_read64, 35 36 /* Block IO */ 37 .block_read = sof_block_read, 38 .block_write = sof_block_write, 39 40 /* doorbell */ 41 .irq_thread = cnl_ipc_irq_thread, 42 43 /* ipc */ 44 .send_msg = cnl_ipc_send_msg, 45 .fw_ready = sof_fw_ready, 46 .get_mailbox_offset = hda_dsp_ipc_get_mailbox_offset, 47 .get_window_offset = hda_dsp_ipc_get_window_offset, 48 49 .ipc_msg_data = hda_ipc_msg_data, 50 .ipc_pcm_params = hda_ipc_pcm_params, 51 52 /* machine driver */ 53 .machine_select = hda_machine_select, 54 .machine_register = sof_machine_register, 55 .machine_unregister = sof_machine_unregister, 56 .set_mach_params = hda_set_mach_params, 57 58 /* debug */ 59 .debug_map = tgl_dsp_debugfs, 60 .debug_map_count = ARRAY_SIZE(tgl_dsp_debugfs), 61 .dbg_dump = hda_dsp_dump, 62 .ipc_dump = cnl_ipc_dump, 63 64 /* stream callbacks */ 65 .pcm_open = hda_dsp_pcm_open, 66 .pcm_close = hda_dsp_pcm_close, 67 .pcm_hw_params = hda_dsp_pcm_hw_params, 68 .pcm_hw_free = hda_dsp_stream_hw_free, 69 .pcm_trigger = hda_dsp_pcm_trigger, 70 .pcm_pointer = hda_dsp_pcm_pointer, 71 72 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_PROBES) 73 /* probe callbacks */ 74 .probe_assign = hda_probe_compr_assign, 75 .probe_free = hda_probe_compr_free, 76 .probe_set_params = hda_probe_compr_set_params, 77 .probe_trigger = hda_probe_compr_trigger, 78 .probe_pointer = hda_probe_compr_pointer, 79 #endif 80 81 /* firmware loading */ 82 .load_firmware = snd_sof_load_firmware_raw, 83 84 /* pre/post fw run */ 85 .pre_fw_run = hda_dsp_pre_fw_run, 86 .post_fw_run = hda_dsp_post_fw_run, 87 88 /* parse platform specific extended manifest */ 89 .parse_platform_ext_manifest = hda_dsp_ext_man_get_cavs_config_data, 90 91 /* dsp core power up/down */ 92 .core_power_up = hda_dsp_enable_core, 93 .core_power_down = hda_dsp_core_reset_power_down, 94 95 /* firmware run */ 96 .run = hda_dsp_cl_boot_firmware_iccmax, 97 98 /* trace callback */ 99 .trace_init = hda_dsp_trace_init, 100 .trace_release = hda_dsp_trace_release, 101 .trace_trigger = hda_dsp_trace_trigger, 102 103 /* DAI drivers */ 104 .drv = skl_dai, 105 .num_drv = SOF_SKL_NUM_DAIS, 106 107 /* PM */ 108 .suspend = hda_dsp_suspend, 109 .resume = hda_dsp_resume, 110 .runtime_suspend = hda_dsp_runtime_suspend, 111 .runtime_resume = hda_dsp_runtime_resume, 112 .runtime_idle = hda_dsp_runtime_idle, 113 .set_hw_params_upon_resume = hda_dsp_set_hw_params_upon_resume, 114 .set_power_state = hda_dsp_set_power_state, 115 116 /* ALSA HW info flags */ 117 .hw_info = SNDRV_PCM_INFO_MMAP | 118 SNDRV_PCM_INFO_MMAP_VALID | 119 SNDRV_PCM_INFO_INTERLEAVED | 120 SNDRV_PCM_INFO_PAUSE | 121 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP, 122 123 .arch_ops = &sof_xtensa_arch_ops, 124 }; 125 EXPORT_SYMBOL_NS(sof_tgl_ops, SND_SOC_SOF_INTEL_HDA_COMMON); 126 127 const struct sof_intel_dsp_desc tgl_chip_info = { 128 /* Tigerlake */ 129 .cores_num = 4, 130 .init_core_mask = 1, 131 .host_managed_cores_mask = BIT(0), 132 .ipc_req = CNL_DSP_REG_HIPCIDR, 133 .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY, 134 .ipc_ack = CNL_DSP_REG_HIPCIDA, 135 .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE, 136 .ipc_ctl = CNL_DSP_REG_HIPCCTL, 137 .rom_init_timeout = 300, 138 .ssp_count = ICL_SSP_COUNT, 139 .ssp_base_offset = CNL_SSP_BASE_OFFSET, 140 }; 141 EXPORT_SYMBOL_NS(tgl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); 142 143 const struct sof_intel_dsp_desc tglh_chip_info = { 144 /* Tigerlake-H */ 145 .cores_num = 2, 146 .init_core_mask = 1, 147 .host_managed_cores_mask = BIT(0), 148 .ipc_req = CNL_DSP_REG_HIPCIDR, 149 .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY, 150 .ipc_ack = CNL_DSP_REG_HIPCIDA, 151 .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE, 152 .ipc_ctl = CNL_DSP_REG_HIPCCTL, 153 .rom_init_timeout = 300, 154 .ssp_count = ICL_SSP_COUNT, 155 .ssp_base_offset = CNL_SSP_BASE_OFFSET, 156 }; 157 EXPORT_SYMBOL_NS(tglh_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); 158 159 const struct sof_intel_dsp_desc adls_chip_info = { 160 /* Alderlake-S */ 161 .cores_num = 2, 162 .init_core_mask = BIT(0), 163 .host_managed_cores_mask = BIT(0), 164 .ipc_req = CNL_DSP_REG_HIPCIDR, 165 .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY, 166 .ipc_ack = CNL_DSP_REG_HIPCIDA, 167 .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE, 168 .ipc_ctl = CNL_DSP_REG_HIPCCTL, 169 .rom_init_timeout = 300, 170 .ssp_count = ICL_SSP_COUNT, 171 .ssp_base_offset = CNL_SSP_BASE_OFFSET, 172 }; 173 EXPORT_SYMBOL_NS(adls_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); 174