1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 // 3 // Copyright(c) 2020 Intel Corporation. All rights reserved. 4 // 5 // Authors: Ranjani Sridharan <ranjani.sridharan@linux.intel.com> 6 // 7 8 /* 9 * Hardware interface for audio DSP on Tigerlake. 10 */ 11 12 #include "../ops.h" 13 #include "hda.h" 14 #include "hda-ipc.h" 15 #include "../sof-audio.h" 16 17 static const struct snd_sof_debugfs_map tgl_dsp_debugfs[] = { 18 {"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS}, 19 {"pp", HDA_DSP_PP_BAR, 0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS}, 20 {"dsp", HDA_DSP_BAR, 0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS}, 21 }; 22 23 static int tgl_dsp_core_get(struct snd_sof_dev *sdev, int core) 24 { 25 struct sof_ipc_pm_core_config pm_core_config = { 26 .hdr = { 27 .cmd = SOF_IPC_GLB_PM_MSG | SOF_IPC_PM_CORE_ENABLE, 28 .size = sizeof(pm_core_config), 29 }, 30 .enable_mask = sdev->enabled_cores_mask | BIT(core), 31 }; 32 33 /* power up primary core if not already powered up and return */ 34 if (core == SOF_DSP_PRIMARY_CORE) 35 return hda_dsp_enable_core(sdev, BIT(core)); 36 37 /* notify DSP for secondary cores */ 38 return sof_ipc_tx_message(sdev->ipc, &pm_core_config, sizeof(pm_core_config), 39 &pm_core_config, sizeof(pm_core_config)); 40 } 41 42 static int tgl_dsp_core_put(struct snd_sof_dev *sdev, int core) 43 { 44 struct sof_ipc_pm_core_config pm_core_config = { 45 .hdr = { 46 .cmd = SOF_IPC_GLB_PM_MSG | SOF_IPC_PM_CORE_ENABLE, 47 .size = sizeof(pm_core_config), 48 }, 49 .enable_mask = sdev->enabled_cores_mask & ~BIT(core), 50 }; 51 52 /* power down primary core and return */ 53 if (core == SOF_DSP_PRIMARY_CORE) 54 return hda_dsp_core_reset_power_down(sdev, BIT(core)); 55 56 /* notify DSP for secondary cores */ 57 return sof_ipc_tx_message(sdev->ipc, &pm_core_config, sizeof(pm_core_config), 58 &pm_core_config, sizeof(pm_core_config)); 59 } 60 61 /* Tigerlake ops */ 62 const struct snd_sof_dsp_ops sof_tgl_ops = { 63 /* probe/remove/shutdown */ 64 .probe = hda_dsp_probe, 65 .remove = hda_dsp_remove, 66 .shutdown = hda_dsp_shutdown, 67 68 /* Register IO */ 69 .write = sof_io_write, 70 .read = sof_io_read, 71 .write64 = sof_io_write64, 72 .read64 = sof_io_read64, 73 74 /* Block IO */ 75 .block_read = sof_block_read, 76 .block_write = sof_block_write, 77 78 /* Mailbox IO */ 79 .mailbox_read = sof_mailbox_read, 80 .mailbox_write = sof_mailbox_write, 81 82 /* doorbell */ 83 .irq_thread = cnl_ipc_irq_thread, 84 85 /* ipc */ 86 .send_msg = cnl_ipc_send_msg, 87 .fw_ready = sof_fw_ready, 88 .get_mailbox_offset = hda_dsp_ipc_get_mailbox_offset, 89 .get_window_offset = hda_dsp_ipc_get_window_offset, 90 91 .ipc_msg_data = hda_ipc_msg_data, 92 .set_stream_data_offset = hda_set_stream_data_offset, 93 94 /* machine driver */ 95 .machine_select = hda_machine_select, 96 .machine_register = sof_machine_register, 97 .machine_unregister = sof_machine_unregister, 98 .set_mach_params = hda_set_mach_params, 99 100 /* debug */ 101 .debug_map = tgl_dsp_debugfs, 102 .debug_map_count = ARRAY_SIZE(tgl_dsp_debugfs), 103 .dbg_dump = hda_dsp_dump, 104 .ipc_dump = cnl_ipc_dump, 105 .debugfs_add_region_item = snd_sof_debugfs_add_region_item_iomem, 106 107 /* stream callbacks */ 108 .pcm_open = hda_dsp_pcm_open, 109 .pcm_close = hda_dsp_pcm_close, 110 .pcm_hw_params = hda_dsp_pcm_hw_params, 111 .pcm_hw_free = hda_dsp_stream_hw_free, 112 .pcm_trigger = hda_dsp_pcm_trigger, 113 .pcm_pointer = hda_dsp_pcm_pointer, 114 .pcm_ack = hda_dsp_pcm_ack, 115 116 /* firmware loading */ 117 .load_firmware = snd_sof_load_firmware_raw, 118 119 /* pre/post fw run */ 120 .pre_fw_run = hda_dsp_pre_fw_run, 121 .post_fw_run = hda_dsp_post_fw_run, 122 123 /* parse platform specific extended manifest */ 124 .parse_platform_ext_manifest = hda_dsp_ext_man_get_cavs_config_data, 125 126 /* dsp core get/put */ 127 .core_get = tgl_dsp_core_get, 128 .core_put = tgl_dsp_core_put, 129 130 /* firmware run */ 131 .run = hda_dsp_cl_boot_firmware_iccmax, 132 133 /* trace callback */ 134 .trace_init = hda_dsp_trace_init, 135 .trace_release = hda_dsp_trace_release, 136 .trace_trigger = hda_dsp_trace_trigger, 137 138 /* client ops */ 139 .register_ipc_clients = hda_register_clients, 140 .unregister_ipc_clients = hda_unregister_clients, 141 142 /* DAI drivers */ 143 .drv = skl_dai, 144 .num_drv = SOF_SKL_NUM_DAIS, 145 146 /* PM */ 147 .suspend = hda_dsp_suspend, 148 .resume = hda_dsp_resume, 149 .runtime_suspend = hda_dsp_runtime_suspend, 150 .runtime_resume = hda_dsp_runtime_resume, 151 .runtime_idle = hda_dsp_runtime_idle, 152 .set_hw_params_upon_resume = hda_dsp_set_hw_params_upon_resume, 153 .set_power_state = hda_dsp_set_power_state, 154 155 /* ALSA HW info flags */ 156 .hw_info = SNDRV_PCM_INFO_MMAP | 157 SNDRV_PCM_INFO_MMAP_VALID | 158 SNDRV_PCM_INFO_INTERLEAVED | 159 SNDRV_PCM_INFO_PAUSE | 160 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP, 161 162 .dsp_arch_ops = &sof_xtensa_arch_ops, 163 }; 164 EXPORT_SYMBOL_NS(sof_tgl_ops, SND_SOC_SOF_INTEL_HDA_COMMON); 165 166 const struct sof_intel_dsp_desc tgl_chip_info = { 167 /* Tigerlake , Alderlake */ 168 .cores_num = 4, 169 .init_core_mask = 1, 170 .host_managed_cores_mask = BIT(0), 171 .ipc_req = CNL_DSP_REG_HIPCIDR, 172 .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY, 173 .ipc_ack = CNL_DSP_REG_HIPCIDA, 174 .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE, 175 .ipc_ctl = CNL_DSP_REG_HIPCCTL, 176 .rom_init_timeout = 300, 177 .ssp_count = ICL_SSP_COUNT, 178 .ssp_base_offset = CNL_SSP_BASE_OFFSET, 179 .sdw_shim_base = SDW_SHIM_BASE, 180 .sdw_alh_base = SDW_ALH_BASE, 181 .check_sdw_irq = hda_common_check_sdw_irq, 182 }; 183 EXPORT_SYMBOL_NS(tgl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); 184 185 const struct sof_intel_dsp_desc tglh_chip_info = { 186 /* Tigerlake-H */ 187 .cores_num = 2, 188 .init_core_mask = 1, 189 .host_managed_cores_mask = BIT(0), 190 .ipc_req = CNL_DSP_REG_HIPCIDR, 191 .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY, 192 .ipc_ack = CNL_DSP_REG_HIPCIDA, 193 .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE, 194 .ipc_ctl = CNL_DSP_REG_HIPCCTL, 195 .rom_init_timeout = 300, 196 .ssp_count = ICL_SSP_COUNT, 197 .ssp_base_offset = CNL_SSP_BASE_OFFSET, 198 .sdw_shim_base = SDW_SHIM_BASE, 199 .sdw_alh_base = SDW_ALH_BASE, 200 .check_sdw_irq = hda_common_check_sdw_irq, 201 }; 202 EXPORT_SYMBOL_NS(tglh_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); 203 204 const struct sof_intel_dsp_desc ehl_chip_info = { 205 /* Elkhartlake */ 206 .cores_num = 4, 207 .init_core_mask = 1, 208 .host_managed_cores_mask = BIT(0), 209 .ipc_req = CNL_DSP_REG_HIPCIDR, 210 .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY, 211 .ipc_ack = CNL_DSP_REG_HIPCIDA, 212 .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE, 213 .ipc_ctl = CNL_DSP_REG_HIPCCTL, 214 .rom_init_timeout = 300, 215 .ssp_count = ICL_SSP_COUNT, 216 .ssp_base_offset = CNL_SSP_BASE_OFFSET, 217 .sdw_shim_base = SDW_SHIM_BASE, 218 .sdw_alh_base = SDW_ALH_BASE, 219 .check_sdw_irq = hda_common_check_sdw_irq, 220 }; 221 EXPORT_SYMBOL_NS(ehl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); 222 223 const struct sof_intel_dsp_desc adls_chip_info = { 224 /* Alderlake-S */ 225 .cores_num = 2, 226 .init_core_mask = BIT(0), 227 .host_managed_cores_mask = BIT(0), 228 .ipc_req = CNL_DSP_REG_HIPCIDR, 229 .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY, 230 .ipc_ack = CNL_DSP_REG_HIPCIDA, 231 .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE, 232 .ipc_ctl = CNL_DSP_REG_HIPCCTL, 233 .rom_init_timeout = 300, 234 .ssp_count = ICL_SSP_COUNT, 235 .ssp_base_offset = CNL_SSP_BASE_OFFSET, 236 .sdw_shim_base = SDW_SHIM_BASE, 237 .sdw_alh_base = SDW_ALH_BASE, 238 .check_sdw_irq = hda_common_check_sdw_irq, 239 }; 240 EXPORT_SYMBOL_NS(adls_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); 241