1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 // 3 // Copyright(c) 2020 Intel Corporation. All rights reserved. 4 // 5 // Authors: Ranjani Sridharan <ranjani.sridharan@linux.intel.com> 6 // 7 8 /* 9 * Hardware interface for audio DSP on Tigerlake. 10 */ 11 12 #include "../ops.h" 13 #include "hda.h" 14 #include "hda-ipc.h" 15 #include "../sof-audio.h" 16 17 static const struct snd_sof_debugfs_map tgl_dsp_debugfs[] = { 18 {"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS}, 19 {"pp", HDA_DSP_PP_BAR, 0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS}, 20 {"dsp", HDA_DSP_BAR, 0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS}, 21 }; 22 23 static int tgl_dsp_core_get(struct snd_sof_dev *sdev, int core) 24 { 25 struct sof_ipc_pm_core_config pm_core_config = { 26 .hdr = { 27 .cmd = SOF_IPC_GLB_PM_MSG | SOF_IPC_PM_CORE_ENABLE, 28 .size = sizeof(pm_core_config), 29 }, 30 .enable_mask = sdev->enabled_cores_mask | BIT(core), 31 }; 32 33 /* power up primary core if not already powered up and return */ 34 if (core == SOF_DSP_PRIMARY_CORE) 35 return hda_dsp_enable_core(sdev, BIT(core)); 36 37 /* notify DSP for secondary cores */ 38 return sof_ipc_tx_message(sdev->ipc, pm_core_config.hdr.cmd, 39 &pm_core_config, sizeof(pm_core_config), 40 &pm_core_config, sizeof(pm_core_config)); 41 } 42 43 static int tgl_dsp_core_put(struct snd_sof_dev *sdev, int core) 44 { 45 struct sof_ipc_pm_core_config pm_core_config = { 46 .hdr = { 47 .cmd = SOF_IPC_GLB_PM_MSG | SOF_IPC_PM_CORE_ENABLE, 48 .size = sizeof(pm_core_config), 49 }, 50 .enable_mask = sdev->enabled_cores_mask & ~BIT(core), 51 }; 52 53 /* power down primary core and return */ 54 if (core == SOF_DSP_PRIMARY_CORE) 55 return hda_dsp_core_reset_power_down(sdev, BIT(core)); 56 57 /* notify DSP for secondary cores */ 58 return sof_ipc_tx_message(sdev->ipc, pm_core_config.hdr.cmd, 59 &pm_core_config, sizeof(pm_core_config), 60 &pm_core_config, sizeof(pm_core_config)); 61 } 62 63 /* Tigerlake ops */ 64 const struct snd_sof_dsp_ops sof_tgl_ops = { 65 /* probe/remove/shutdown */ 66 .probe = hda_dsp_probe, 67 .remove = hda_dsp_remove, 68 .shutdown = hda_dsp_shutdown, 69 70 /* Register IO */ 71 .write = sof_io_write, 72 .read = sof_io_read, 73 .write64 = sof_io_write64, 74 .read64 = sof_io_read64, 75 76 /* Block IO */ 77 .block_read = sof_block_read, 78 .block_write = sof_block_write, 79 80 /* Mailbox IO */ 81 .mailbox_read = sof_mailbox_read, 82 .mailbox_write = sof_mailbox_write, 83 84 /* doorbell */ 85 .irq_thread = cnl_ipc_irq_thread, 86 87 /* ipc */ 88 .send_msg = cnl_ipc_send_msg, 89 .fw_ready = sof_fw_ready, 90 .get_mailbox_offset = hda_dsp_ipc_get_mailbox_offset, 91 .get_window_offset = hda_dsp_ipc_get_window_offset, 92 93 .ipc_msg_data = hda_ipc_msg_data, 94 .set_stream_data_offset = hda_set_stream_data_offset, 95 96 /* machine driver */ 97 .machine_select = hda_machine_select, 98 .machine_register = sof_machine_register, 99 .machine_unregister = sof_machine_unregister, 100 .set_mach_params = hda_set_mach_params, 101 102 /* debug */ 103 .debug_map = tgl_dsp_debugfs, 104 .debug_map_count = ARRAY_SIZE(tgl_dsp_debugfs), 105 .dbg_dump = hda_dsp_dump, 106 .ipc_dump = cnl_ipc_dump, 107 .debugfs_add_region_item = snd_sof_debugfs_add_region_item_iomem, 108 109 /* stream callbacks */ 110 .pcm_open = hda_dsp_pcm_open, 111 .pcm_close = hda_dsp_pcm_close, 112 .pcm_hw_params = hda_dsp_pcm_hw_params, 113 .pcm_hw_free = hda_dsp_stream_hw_free, 114 .pcm_trigger = hda_dsp_pcm_trigger, 115 .pcm_pointer = hda_dsp_pcm_pointer, 116 .pcm_ack = hda_dsp_pcm_ack, 117 118 /* firmware loading */ 119 .load_firmware = snd_sof_load_firmware_raw, 120 121 /* pre/post fw run */ 122 .pre_fw_run = hda_dsp_pre_fw_run, 123 .post_fw_run = hda_dsp_post_fw_run, 124 125 /* parse platform specific extended manifest */ 126 .parse_platform_ext_manifest = hda_dsp_ext_man_get_cavs_config_data, 127 128 /* dsp core get/put */ 129 .core_get = tgl_dsp_core_get, 130 .core_put = tgl_dsp_core_put, 131 132 /* firmware run */ 133 .run = hda_dsp_cl_boot_firmware_iccmax, 134 135 /* trace callback */ 136 .trace_init = hda_dsp_trace_init, 137 .trace_release = hda_dsp_trace_release, 138 .trace_trigger = hda_dsp_trace_trigger, 139 140 /* client ops */ 141 .register_ipc_clients = hda_register_clients, 142 .unregister_ipc_clients = hda_unregister_clients, 143 144 /* DAI drivers */ 145 .drv = skl_dai, 146 .num_drv = SOF_SKL_NUM_DAIS, 147 148 /* PM */ 149 .suspend = hda_dsp_suspend, 150 .resume = hda_dsp_resume, 151 .runtime_suspend = hda_dsp_runtime_suspend, 152 .runtime_resume = hda_dsp_runtime_resume, 153 .runtime_idle = hda_dsp_runtime_idle, 154 .set_hw_params_upon_resume = hda_dsp_set_hw_params_upon_resume, 155 .set_power_state = hda_dsp_set_power_state, 156 157 /* ALSA HW info flags */ 158 .hw_info = SNDRV_PCM_INFO_MMAP | 159 SNDRV_PCM_INFO_MMAP_VALID | 160 SNDRV_PCM_INFO_INTERLEAVED | 161 SNDRV_PCM_INFO_PAUSE | 162 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP, 163 164 .dsp_arch_ops = &sof_xtensa_arch_ops, 165 }; 166 EXPORT_SYMBOL_NS(sof_tgl_ops, SND_SOC_SOF_INTEL_HDA_COMMON); 167 168 const struct sof_intel_dsp_desc tgl_chip_info = { 169 /* Tigerlake , Alderlake */ 170 .cores_num = 4, 171 .init_core_mask = 1, 172 .host_managed_cores_mask = BIT(0), 173 .ipc_req = CNL_DSP_REG_HIPCIDR, 174 .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY, 175 .ipc_ack = CNL_DSP_REG_HIPCIDA, 176 .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE, 177 .ipc_ctl = CNL_DSP_REG_HIPCCTL, 178 .rom_init_timeout = 300, 179 .ssp_count = ICL_SSP_COUNT, 180 .ssp_base_offset = CNL_SSP_BASE_OFFSET, 181 .sdw_shim_base = SDW_SHIM_BASE, 182 .sdw_alh_base = SDW_ALH_BASE, 183 .check_sdw_irq = hda_common_check_sdw_irq, 184 }; 185 EXPORT_SYMBOL_NS(tgl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); 186 187 const struct sof_intel_dsp_desc tglh_chip_info = { 188 /* Tigerlake-H */ 189 .cores_num = 2, 190 .init_core_mask = 1, 191 .host_managed_cores_mask = BIT(0), 192 .ipc_req = CNL_DSP_REG_HIPCIDR, 193 .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY, 194 .ipc_ack = CNL_DSP_REG_HIPCIDA, 195 .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE, 196 .ipc_ctl = CNL_DSP_REG_HIPCCTL, 197 .rom_init_timeout = 300, 198 .ssp_count = ICL_SSP_COUNT, 199 .ssp_base_offset = CNL_SSP_BASE_OFFSET, 200 .sdw_shim_base = SDW_SHIM_BASE, 201 .sdw_alh_base = SDW_ALH_BASE, 202 .check_sdw_irq = hda_common_check_sdw_irq, 203 }; 204 EXPORT_SYMBOL_NS(tglh_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); 205 206 const struct sof_intel_dsp_desc ehl_chip_info = { 207 /* Elkhartlake */ 208 .cores_num = 4, 209 .init_core_mask = 1, 210 .host_managed_cores_mask = BIT(0), 211 .ipc_req = CNL_DSP_REG_HIPCIDR, 212 .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY, 213 .ipc_ack = CNL_DSP_REG_HIPCIDA, 214 .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE, 215 .ipc_ctl = CNL_DSP_REG_HIPCCTL, 216 .rom_init_timeout = 300, 217 .ssp_count = ICL_SSP_COUNT, 218 .ssp_base_offset = CNL_SSP_BASE_OFFSET, 219 .sdw_shim_base = SDW_SHIM_BASE, 220 .sdw_alh_base = SDW_ALH_BASE, 221 .check_sdw_irq = hda_common_check_sdw_irq, 222 }; 223 EXPORT_SYMBOL_NS(ehl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); 224 225 const struct sof_intel_dsp_desc adls_chip_info = { 226 /* Alderlake-S */ 227 .cores_num = 2, 228 .init_core_mask = BIT(0), 229 .host_managed_cores_mask = BIT(0), 230 .ipc_req = CNL_DSP_REG_HIPCIDR, 231 .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY, 232 .ipc_ack = CNL_DSP_REG_HIPCIDA, 233 .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE, 234 .ipc_ctl = CNL_DSP_REG_HIPCCTL, 235 .rom_init_timeout = 300, 236 .ssp_count = ICL_SSP_COUNT, 237 .ssp_base_offset = CNL_SSP_BASE_OFFSET, 238 .sdw_shim_base = SDW_SHIM_BASE, 239 .sdw_alh_base = SDW_ALH_BASE, 240 .check_sdw_irq = hda_common_check_sdw_irq, 241 }; 242 EXPORT_SYMBOL_NS(adls_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); 243