1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 // 3 // Copyright(c) 2020 Intel Corporation. All rights reserved. 4 // 5 // Authors: Ranjani Sridharan <ranjani.sridharan@linux.intel.com> 6 // 7 8 /* 9 * Hardware interface for audio DSP on Tigerlake. 10 */ 11 12 #include "../ops.h" 13 #include "hda.h" 14 #include "hda-ipc.h" 15 #include "../sof-audio.h" 16 17 static const struct snd_sof_debugfs_map tgl_dsp_debugfs[] = { 18 {"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS}, 19 {"pp", HDA_DSP_PP_BAR, 0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS}, 20 {"dsp", HDA_DSP_BAR, 0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS}, 21 }; 22 23 static int tgl_dsp_core_get(struct snd_sof_dev *sdev, int core) 24 { 25 struct sof_ipc_pm_core_config pm_core_config = { 26 .hdr = { 27 .cmd = SOF_IPC_GLB_PM_MSG | SOF_IPC_PM_CORE_ENABLE, 28 .size = sizeof(pm_core_config), 29 }, 30 .enable_mask = sdev->enabled_cores_mask | BIT(core), 31 }; 32 33 /* power up primary core if not already powered up and return */ 34 if (core == SOF_DSP_PRIMARY_CORE) 35 return hda_dsp_enable_core(sdev, BIT(core)); 36 37 /* notify DSP for secondary cores */ 38 return sof_ipc_tx_message(sdev->ipc, &pm_core_config, sizeof(pm_core_config), 39 &pm_core_config, sizeof(pm_core_config)); 40 } 41 42 static int tgl_dsp_core_put(struct snd_sof_dev *sdev, int core) 43 { 44 struct sof_ipc_pm_core_config pm_core_config = { 45 .hdr = { 46 .cmd = SOF_IPC_GLB_PM_MSG | SOF_IPC_PM_CORE_ENABLE, 47 .size = sizeof(pm_core_config), 48 }, 49 .enable_mask = sdev->enabled_cores_mask & ~BIT(core), 50 }; 51 52 /* power down primary core and return */ 53 if (core == SOF_DSP_PRIMARY_CORE) 54 return hda_dsp_core_reset_power_down(sdev, BIT(core)); 55 56 /* notify DSP for secondary cores */ 57 return sof_ipc_tx_message(sdev->ipc, &pm_core_config, sizeof(pm_core_config), 58 &pm_core_config, sizeof(pm_core_config)); 59 } 60 61 /* Tigerlake ops */ 62 struct snd_sof_dsp_ops sof_tgl_ops; 63 EXPORT_SYMBOL_NS(sof_tgl_ops, SND_SOC_SOF_INTEL_HDA_COMMON); 64 65 int sof_tgl_ops_init(struct snd_sof_dev *sdev) 66 { 67 /* common defaults */ 68 memcpy(&sof_tgl_ops, &sof_hda_common_ops, sizeof(struct snd_sof_dsp_ops)); 69 70 /* probe/remove/shutdown */ 71 sof_tgl_ops.shutdown = hda_dsp_shutdown; 72 73 /* doorbell */ 74 sof_tgl_ops.irq_thread = cnl_ipc_irq_thread; 75 76 /* ipc */ 77 sof_tgl_ops.send_msg = cnl_ipc_send_msg; 78 79 /* debug */ 80 sof_tgl_ops.debug_map = tgl_dsp_debugfs; 81 sof_tgl_ops.debug_map_count = ARRAY_SIZE(tgl_dsp_debugfs); 82 sof_tgl_ops.ipc_dump = cnl_ipc_dump; 83 84 /* pre/post fw run */ 85 sof_tgl_ops.post_fw_run = hda_dsp_post_fw_run; 86 87 /* firmware run */ 88 sof_tgl_ops.run = hda_dsp_cl_boot_firmware_iccmax; 89 90 /* dsp core get/put */ 91 sof_tgl_ops.core_get = tgl_dsp_core_get; 92 sof_tgl_ops.core_put = tgl_dsp_core_put; 93 94 return 0; 95 }; 96 EXPORT_SYMBOL_NS(sof_tgl_ops_init, SND_SOC_SOF_INTEL_HDA_COMMON); 97 98 const struct sof_intel_dsp_desc tgl_chip_info = { 99 /* Tigerlake , Alderlake */ 100 .cores_num = 4, 101 .init_core_mask = 1, 102 .host_managed_cores_mask = BIT(0), 103 .ipc_req = CNL_DSP_REG_HIPCIDR, 104 .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY, 105 .ipc_ack = CNL_DSP_REG_HIPCIDA, 106 .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE, 107 .ipc_ctl = CNL_DSP_REG_HIPCCTL, 108 .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS, 109 .rom_init_timeout = 300, 110 .ssp_count = ICL_SSP_COUNT, 111 .ssp_base_offset = CNL_SSP_BASE_OFFSET, 112 .sdw_shim_base = SDW_SHIM_BASE, 113 .sdw_alh_base = SDW_ALH_BASE, 114 .check_sdw_irq = hda_common_check_sdw_irq, 115 .check_ipc_irq = hda_dsp_check_ipc_irq, 116 .hw_ip_version = SOF_INTEL_CAVS_2_5, 117 }; 118 EXPORT_SYMBOL_NS(tgl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); 119 120 const struct sof_intel_dsp_desc tglh_chip_info = { 121 /* Tigerlake-H */ 122 .cores_num = 2, 123 .init_core_mask = 1, 124 .host_managed_cores_mask = BIT(0), 125 .ipc_req = CNL_DSP_REG_HIPCIDR, 126 .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY, 127 .ipc_ack = CNL_DSP_REG_HIPCIDA, 128 .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE, 129 .ipc_ctl = CNL_DSP_REG_HIPCCTL, 130 .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS, 131 .rom_init_timeout = 300, 132 .ssp_count = ICL_SSP_COUNT, 133 .ssp_base_offset = CNL_SSP_BASE_OFFSET, 134 .sdw_shim_base = SDW_SHIM_BASE, 135 .sdw_alh_base = SDW_ALH_BASE, 136 .check_sdw_irq = hda_common_check_sdw_irq, 137 .check_ipc_irq = hda_dsp_check_ipc_irq, 138 .hw_ip_version = SOF_INTEL_CAVS_2_5, 139 }; 140 EXPORT_SYMBOL_NS(tglh_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); 141 142 const struct sof_intel_dsp_desc ehl_chip_info = { 143 /* Elkhartlake */ 144 .cores_num = 4, 145 .init_core_mask = 1, 146 .host_managed_cores_mask = BIT(0), 147 .ipc_req = CNL_DSP_REG_HIPCIDR, 148 .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY, 149 .ipc_ack = CNL_DSP_REG_HIPCIDA, 150 .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE, 151 .ipc_ctl = CNL_DSP_REG_HIPCCTL, 152 .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS, 153 .rom_init_timeout = 300, 154 .ssp_count = ICL_SSP_COUNT, 155 .ssp_base_offset = CNL_SSP_BASE_OFFSET, 156 .sdw_shim_base = SDW_SHIM_BASE, 157 .sdw_alh_base = SDW_ALH_BASE, 158 .check_sdw_irq = hda_common_check_sdw_irq, 159 .check_ipc_irq = hda_dsp_check_ipc_irq, 160 .hw_ip_version = SOF_INTEL_CAVS_2_5, 161 }; 162 EXPORT_SYMBOL_NS(ehl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); 163 164 const struct sof_intel_dsp_desc adls_chip_info = { 165 /* Alderlake-S */ 166 .cores_num = 2, 167 .init_core_mask = BIT(0), 168 .host_managed_cores_mask = BIT(0), 169 .ipc_req = CNL_DSP_REG_HIPCIDR, 170 .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY, 171 .ipc_ack = CNL_DSP_REG_HIPCIDA, 172 .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE, 173 .ipc_ctl = CNL_DSP_REG_HIPCCTL, 174 .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS, 175 .rom_init_timeout = 300, 176 .ssp_count = ICL_SSP_COUNT, 177 .ssp_base_offset = CNL_SSP_BASE_OFFSET, 178 .sdw_shim_base = SDW_SHIM_BASE, 179 .sdw_alh_base = SDW_ALH_BASE, 180 .check_sdw_irq = hda_common_check_sdw_irq, 181 .check_ipc_irq = hda_dsp_check_ipc_irq, 182 .hw_ip_version = SOF_INTEL_CAVS_2_5, 183 }; 184 EXPORT_SYMBOL_NS(adls_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); 185