18b98491aSRanjani Sridharan // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 28b98491aSRanjani Sridharan // 38b98491aSRanjani Sridharan // Copyright(c) 2020 Intel Corporation. All rights reserved. 48b98491aSRanjani Sridharan // 58b98491aSRanjani Sridharan // Authors: Ranjani Sridharan <ranjani.sridharan@linux.intel.com> 68b98491aSRanjani Sridharan // 78b98491aSRanjani Sridharan 88b98491aSRanjani Sridharan /* 98b98491aSRanjani Sridharan * Hardware interface for audio DSP on Tigerlake. 108b98491aSRanjani Sridharan */ 118b98491aSRanjani Sridharan 128b98491aSRanjani Sridharan #include "../ops.h" 138b98491aSRanjani Sridharan #include "hda.h" 148b98491aSRanjani Sridharan #include "hda-ipc.h" 158b98491aSRanjani Sridharan #include "../sof-audio.h" 168b98491aSRanjani Sridharan 178b98491aSRanjani Sridharan static const struct snd_sof_debugfs_map tgl_dsp_debugfs[] = { 188b98491aSRanjani Sridharan {"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS}, 198b98491aSRanjani Sridharan {"pp", HDA_DSP_PP_BAR, 0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS}, 208b98491aSRanjani Sridharan {"dsp", HDA_DSP_BAR, 0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS}, 218b98491aSRanjani Sridharan }; 228b98491aSRanjani Sridharan 2341dd63ccSRanjani Sridharan static int tgl_dsp_core_get(struct snd_sof_dev *sdev, int core) 2441dd63ccSRanjani Sridharan { 2541dd63ccSRanjani Sridharan struct sof_ipc_pm_core_config pm_core_config = { 2641dd63ccSRanjani Sridharan .hdr = { 2741dd63ccSRanjani Sridharan .cmd = SOF_IPC_GLB_PM_MSG | SOF_IPC_PM_CORE_ENABLE, 2841dd63ccSRanjani Sridharan .size = sizeof(pm_core_config), 2941dd63ccSRanjani Sridharan }, 3041dd63ccSRanjani Sridharan .enable_mask = sdev->enabled_cores_mask | BIT(core), 3141dd63ccSRanjani Sridharan }; 3241dd63ccSRanjani Sridharan 3341dd63ccSRanjani Sridharan /* power up primary core if not already powered up and return */ 3441dd63ccSRanjani Sridharan if (core == SOF_DSP_PRIMARY_CORE) 3541dd63ccSRanjani Sridharan return hda_dsp_enable_core(sdev, BIT(core)); 3641dd63ccSRanjani Sridharan 3741dd63ccSRanjani Sridharan /* notify DSP for secondary cores */ 382a51c0f8SPeter Ujfalusi return sof_ipc_tx_message(sdev->ipc, &pm_core_config, sizeof(pm_core_config), 3941dd63ccSRanjani Sridharan &pm_core_config, sizeof(pm_core_config)); 4041dd63ccSRanjani Sridharan } 4141dd63ccSRanjani Sridharan 4241dd63ccSRanjani Sridharan static int tgl_dsp_core_put(struct snd_sof_dev *sdev, int core) 4341dd63ccSRanjani Sridharan { 4441dd63ccSRanjani Sridharan struct sof_ipc_pm_core_config pm_core_config = { 4541dd63ccSRanjani Sridharan .hdr = { 4641dd63ccSRanjani Sridharan .cmd = SOF_IPC_GLB_PM_MSG | SOF_IPC_PM_CORE_ENABLE, 4741dd63ccSRanjani Sridharan .size = sizeof(pm_core_config), 4841dd63ccSRanjani Sridharan }, 4941dd63ccSRanjani Sridharan .enable_mask = sdev->enabled_cores_mask & ~BIT(core), 5041dd63ccSRanjani Sridharan }; 5141dd63ccSRanjani Sridharan 5241dd63ccSRanjani Sridharan /* power down primary core and return */ 5341dd63ccSRanjani Sridharan if (core == SOF_DSP_PRIMARY_CORE) 5441dd63ccSRanjani Sridharan return hda_dsp_core_reset_power_down(sdev, BIT(core)); 5541dd63ccSRanjani Sridharan 5641dd63ccSRanjani Sridharan /* notify DSP for secondary cores */ 572a51c0f8SPeter Ujfalusi return sof_ipc_tx_message(sdev->ipc, &pm_core_config, sizeof(pm_core_config), 5841dd63ccSRanjani Sridharan &pm_core_config, sizeof(pm_core_config)); 5941dd63ccSRanjani Sridharan } 6041dd63ccSRanjani Sridharan 618b98491aSRanjani Sridharan /* Tigerlake ops */ 6237e809d5SPierre-Louis Bossart struct snd_sof_dsp_ops sof_tgl_ops; 6337e809d5SPierre-Louis Bossart EXPORT_SYMBOL_NS(sof_tgl_ops, SND_SOC_SOF_INTEL_HDA_COMMON); 6437e809d5SPierre-Louis Bossart 6537e809d5SPierre-Louis Bossart int sof_tgl_ops_init(struct snd_sof_dev *sdev) 6637e809d5SPierre-Louis Bossart { 6737e809d5SPierre-Louis Bossart /* common defaults */ 6837e809d5SPierre-Louis Bossart memcpy(&sof_tgl_ops, &sof_hda_common_ops, sizeof(struct snd_sof_dsp_ops)); 6937e809d5SPierre-Louis Bossart 7044a4cfadSKeyon Jie /* probe/remove/shutdown */ 7137e809d5SPierre-Louis Bossart sof_tgl_ops.shutdown = hda_dsp_shutdown; 72f71f59ddSDaniel Baluta 73*e3105c0cSRanjani Sridharan if (sdev->pdata->ipc_type == SOF_IPC) { 748b98491aSRanjani Sridharan /* doorbell */ 7537e809d5SPierre-Louis Bossart sof_tgl_ops.irq_thread = cnl_ipc_irq_thread; 768b98491aSRanjani Sridharan 778b98491aSRanjani Sridharan /* ipc */ 7837e809d5SPierre-Louis Bossart sof_tgl_ops.send_msg = cnl_ipc_send_msg; 79*e3105c0cSRanjani Sridharan } 80*e3105c0cSRanjani Sridharan 81*e3105c0cSRanjani Sridharan if (sdev->pdata->ipc_type == SOF_INTEL_IPC4) { 82*e3105c0cSRanjani Sridharan /* doorbell */ 83*e3105c0cSRanjani Sridharan sof_tgl_ops.irq_thread = cnl_ipc4_irq_thread; 84*e3105c0cSRanjani Sridharan 85*e3105c0cSRanjani Sridharan /* ipc */ 86*e3105c0cSRanjani Sridharan sof_tgl_ops.send_msg = cnl_ipc4_send_msg; 87*e3105c0cSRanjani Sridharan } 888b98491aSRanjani Sridharan 8951ec71dcSRanjani Sridharan /* set DAI driver ops */ 9051ec71dcSRanjani Sridharan hda_set_dai_drv_ops(sdev, &sof_tgl_ops); 9151ec71dcSRanjani Sridharan 928b98491aSRanjani Sridharan /* debug */ 9337e809d5SPierre-Louis Bossart sof_tgl_ops.debug_map = tgl_dsp_debugfs; 9437e809d5SPierre-Louis Bossart sof_tgl_ops.debug_map_count = ARRAY_SIZE(tgl_dsp_debugfs); 9537e809d5SPierre-Louis Bossart sof_tgl_ops.ipc_dump = cnl_ipc_dump; 968b98491aSRanjani Sridharan 978b98491aSRanjani Sridharan /* pre/post fw run */ 9837e809d5SPierre-Louis Bossart sof_tgl_ops.post_fw_run = hda_dsp_post_fw_run; 998b98491aSRanjani Sridharan 1008b98491aSRanjani Sridharan /* firmware run */ 10137e809d5SPierre-Louis Bossart sof_tgl_ops.run = hda_dsp_cl_boot_firmware_iccmax; 1028b98491aSRanjani Sridharan 10337e809d5SPierre-Louis Bossart /* dsp core get/put */ 10437e809d5SPierre-Louis Bossart sof_tgl_ops.core_get = tgl_dsp_core_get; 10537e809d5SPierre-Louis Bossart sof_tgl_ops.core_put = tgl_dsp_core_put; 1068b98491aSRanjani Sridharan 10737e809d5SPierre-Louis Bossart return 0; 1088b98491aSRanjani Sridharan }; 10937e809d5SPierre-Louis Bossart EXPORT_SYMBOL_NS(sof_tgl_ops_init, SND_SOC_SOF_INTEL_HDA_COMMON); 1108b98491aSRanjani Sridharan 1118b98491aSRanjani Sridharan const struct sof_intel_dsp_desc tgl_chip_info = { 1124ad03f89SSathya Prakash M R /* Tigerlake , Alderlake */ 1138b98491aSRanjani Sridharan .cores_num = 4, 1148b98491aSRanjani Sridharan .init_core_mask = 1, 115fde10655SRanjani Sridharan .host_managed_cores_mask = BIT(0), 1168b98491aSRanjani Sridharan .ipc_req = CNL_DSP_REG_HIPCIDR, 1178b98491aSRanjani Sridharan .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY, 1188b98491aSRanjani Sridharan .ipc_ack = CNL_DSP_REG_HIPCIDA, 1198b98491aSRanjani Sridharan .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE, 1208b98491aSRanjani Sridharan .ipc_ctl = CNL_DSP_REG_HIPCCTL, 12171778f79SRanjani Sridharan .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS, 1228b98491aSRanjani Sridharan .rom_init_timeout = 300, 1238b98491aSRanjani Sridharan .ssp_count = ICL_SSP_COUNT, 1248b98491aSRanjani Sridharan .ssp_base_offset = CNL_SSP_BASE_OFFSET, 1251cbf6443SBard Liao .sdw_shim_base = SDW_SHIM_BASE, 1261cbf6443SBard Liao .sdw_alh_base = SDW_ALH_BASE, 127198fa4bcSBard Liao .check_sdw_irq = hda_common_check_sdw_irq, 1283dee239eSRanjani Sridharan .check_ipc_irq = hda_dsp_check_ipc_irq, 12903cf7262SPierre-Louis Bossart .hw_ip_version = SOF_INTEL_CAVS_2_5, 1308b98491aSRanjani Sridharan }; 1318b98491aSRanjani Sridharan EXPORT_SYMBOL_NS(tgl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); 13230ee3738SRander Wang 13330ee3738SRander Wang const struct sof_intel_dsp_desc tglh_chip_info = { 13430ee3738SRander Wang /* Tigerlake-H */ 13530ee3738SRander Wang .cores_num = 2, 13630ee3738SRander Wang .init_core_mask = 1, 13730ee3738SRander Wang .host_managed_cores_mask = BIT(0), 13830ee3738SRander Wang .ipc_req = CNL_DSP_REG_HIPCIDR, 13930ee3738SRander Wang .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY, 14030ee3738SRander Wang .ipc_ack = CNL_DSP_REG_HIPCIDA, 14130ee3738SRander Wang .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE, 14230ee3738SRander Wang .ipc_ctl = CNL_DSP_REG_HIPCCTL, 14371778f79SRanjani Sridharan .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS, 14430ee3738SRander Wang .rom_init_timeout = 300, 14530ee3738SRander Wang .ssp_count = ICL_SSP_COUNT, 14630ee3738SRander Wang .ssp_base_offset = CNL_SSP_BASE_OFFSET, 1471cbf6443SBard Liao .sdw_shim_base = SDW_SHIM_BASE, 1481cbf6443SBard Liao .sdw_alh_base = SDW_ALH_BASE, 149198fa4bcSBard Liao .check_sdw_irq = hda_common_check_sdw_irq, 1503dee239eSRanjani Sridharan .check_ipc_irq = hda_dsp_check_ipc_irq, 15103cf7262SPierre-Louis Bossart .hw_ip_version = SOF_INTEL_CAVS_2_5, 15230ee3738SRander Wang }; 15330ee3738SRander Wang EXPORT_SYMBOL_NS(tglh_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); 1546c2b6bb0SKai Vehmanen 1558bb84ca8SPierre-Louis Bossart const struct sof_intel_dsp_desc ehl_chip_info = { 1568bb84ca8SPierre-Louis Bossart /* Elkhartlake */ 1578bb84ca8SPierre-Louis Bossart .cores_num = 4, 1588bb84ca8SPierre-Louis Bossart .init_core_mask = 1, 1598bb84ca8SPierre-Louis Bossart .host_managed_cores_mask = BIT(0), 1608bb84ca8SPierre-Louis Bossart .ipc_req = CNL_DSP_REG_HIPCIDR, 1618bb84ca8SPierre-Louis Bossart .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY, 1628bb84ca8SPierre-Louis Bossart .ipc_ack = CNL_DSP_REG_HIPCIDA, 1638bb84ca8SPierre-Louis Bossart .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE, 1648bb84ca8SPierre-Louis Bossart .ipc_ctl = CNL_DSP_REG_HIPCCTL, 16571778f79SRanjani Sridharan .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS, 1668bb84ca8SPierre-Louis Bossart .rom_init_timeout = 300, 1678bb84ca8SPierre-Louis Bossart .ssp_count = ICL_SSP_COUNT, 1688bb84ca8SPierre-Louis Bossart .ssp_base_offset = CNL_SSP_BASE_OFFSET, 1691cbf6443SBard Liao .sdw_shim_base = SDW_SHIM_BASE, 1701cbf6443SBard Liao .sdw_alh_base = SDW_ALH_BASE, 171198fa4bcSBard Liao .check_sdw_irq = hda_common_check_sdw_irq, 1723dee239eSRanjani Sridharan .check_ipc_irq = hda_dsp_check_ipc_irq, 17303cf7262SPierre-Louis Bossart .hw_ip_version = SOF_INTEL_CAVS_2_5, 1748bb84ca8SPierre-Louis Bossart }; 1758bb84ca8SPierre-Louis Bossart EXPORT_SYMBOL_NS(ehl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); 1768bb84ca8SPierre-Louis Bossart 1776c2b6bb0SKai Vehmanen const struct sof_intel_dsp_desc adls_chip_info = { 1786c2b6bb0SKai Vehmanen /* Alderlake-S */ 1796c2b6bb0SKai Vehmanen .cores_num = 2, 1806c2b6bb0SKai Vehmanen .init_core_mask = BIT(0), 1816c2b6bb0SKai Vehmanen .host_managed_cores_mask = BIT(0), 1826c2b6bb0SKai Vehmanen .ipc_req = CNL_DSP_REG_HIPCIDR, 1836c2b6bb0SKai Vehmanen .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY, 1846c2b6bb0SKai Vehmanen .ipc_ack = CNL_DSP_REG_HIPCIDA, 1856c2b6bb0SKai Vehmanen .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE, 1866c2b6bb0SKai Vehmanen .ipc_ctl = CNL_DSP_REG_HIPCCTL, 18771778f79SRanjani Sridharan .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS, 1886c2b6bb0SKai Vehmanen .rom_init_timeout = 300, 1896c2b6bb0SKai Vehmanen .ssp_count = ICL_SSP_COUNT, 1906c2b6bb0SKai Vehmanen .ssp_base_offset = CNL_SSP_BASE_OFFSET, 1911cbf6443SBard Liao .sdw_shim_base = SDW_SHIM_BASE, 1921cbf6443SBard Liao .sdw_alh_base = SDW_ALH_BASE, 193198fa4bcSBard Liao .check_sdw_irq = hda_common_check_sdw_irq, 1943dee239eSRanjani Sridharan .check_ipc_irq = hda_dsp_check_ipc_irq, 19503cf7262SPierre-Louis Bossart .hw_ip_version = SOF_INTEL_CAVS_2_5, 1966c2b6bb0SKai Vehmanen }; 1976c2b6bb0SKai Vehmanen EXPORT_SYMBOL_NS(adls_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); 198