18b98491aSRanjani Sridharan // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 28b98491aSRanjani Sridharan // 38b98491aSRanjani Sridharan // Copyright(c) 2020 Intel Corporation. All rights reserved. 48b98491aSRanjani Sridharan // 58b98491aSRanjani Sridharan // Authors: Ranjani Sridharan <ranjani.sridharan@linux.intel.com> 68b98491aSRanjani Sridharan // 78b98491aSRanjani Sridharan 88b98491aSRanjani Sridharan /* 98b98491aSRanjani Sridharan * Hardware interface for audio DSP on Tigerlake. 108b98491aSRanjani Sridharan */ 118b98491aSRanjani Sridharan 12a4cfdebdSRanjani Sridharan #include <sound/sof/ext_manifest4.h> 13a4cfdebdSRanjani Sridharan #include "../ipc4-priv.h" 148b98491aSRanjani Sridharan #include "../ops.h" 158b98491aSRanjani Sridharan #include "hda.h" 168b98491aSRanjani Sridharan #include "hda-ipc.h" 178b98491aSRanjani Sridharan #include "../sof-audio.h" 188b98491aSRanjani Sridharan 198b98491aSRanjani Sridharan static const struct snd_sof_debugfs_map tgl_dsp_debugfs[] = { 208b98491aSRanjani Sridharan {"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS}, 218b98491aSRanjani Sridharan {"pp", HDA_DSP_PP_BAR, 0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS}, 228b98491aSRanjani Sridharan {"dsp", HDA_DSP_BAR, 0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS}, 238b98491aSRanjani Sridharan }; 248b98491aSRanjani Sridharan 2541dd63ccSRanjani Sridharan static int tgl_dsp_core_get(struct snd_sof_dev *sdev, int core) 2641dd63ccSRanjani Sridharan { 277a567740SPeter Ujfalusi const struct sof_ipc_pm_ops *pm_ops = sdev->ipc->ops->pm; 2841dd63ccSRanjani Sridharan 2941dd63ccSRanjani Sridharan /* power up primary core if not already powered up and return */ 3041dd63ccSRanjani Sridharan if (core == SOF_DSP_PRIMARY_CORE) 3141dd63ccSRanjani Sridharan return hda_dsp_enable_core(sdev, BIT(core)); 3241dd63ccSRanjani Sridharan 337a567740SPeter Ujfalusi if (pm_ops->set_core_state) 347a567740SPeter Ujfalusi return pm_ops->set_core_state(sdev, core, true); 357a567740SPeter Ujfalusi 367a567740SPeter Ujfalusi return 0; 3741dd63ccSRanjani Sridharan } 3841dd63ccSRanjani Sridharan 3941dd63ccSRanjani Sridharan static int tgl_dsp_core_put(struct snd_sof_dev *sdev, int core) 4041dd63ccSRanjani Sridharan { 417a567740SPeter Ujfalusi const struct sof_ipc_pm_ops *pm_ops = sdev->ipc->ops->pm; 4241dd63ccSRanjani Sridharan 4341dd63ccSRanjani Sridharan /* power down primary core and return */ 4441dd63ccSRanjani Sridharan if (core == SOF_DSP_PRIMARY_CORE) 4541dd63ccSRanjani Sridharan return hda_dsp_core_reset_power_down(sdev, BIT(core)); 4641dd63ccSRanjani Sridharan 477a567740SPeter Ujfalusi if (pm_ops->set_core_state) 487a567740SPeter Ujfalusi return pm_ops->set_core_state(sdev, core, false); 497a567740SPeter Ujfalusi 507a567740SPeter Ujfalusi return 0; 5141dd63ccSRanjani Sridharan } 5241dd63ccSRanjani Sridharan 538b98491aSRanjani Sridharan /* Tigerlake ops */ 5437e809d5SPierre-Louis Bossart struct snd_sof_dsp_ops sof_tgl_ops; 5537e809d5SPierre-Louis Bossart EXPORT_SYMBOL_NS(sof_tgl_ops, SND_SOC_SOF_INTEL_HDA_COMMON); 5637e809d5SPierre-Louis Bossart 5737e809d5SPierre-Louis Bossart int sof_tgl_ops_init(struct snd_sof_dev *sdev) 5837e809d5SPierre-Louis Bossart { 5937e809d5SPierre-Louis Bossart /* common defaults */ 6037e809d5SPierre-Louis Bossart memcpy(&sof_tgl_ops, &sof_hda_common_ops, sizeof(struct snd_sof_dsp_ops)); 6137e809d5SPierre-Louis Bossart 6244a4cfadSKeyon Jie /* probe/remove/shutdown */ 6337e809d5SPierre-Louis Bossart sof_tgl_ops.shutdown = hda_dsp_shutdown; 64f71f59ddSDaniel Baluta 65e3105c0cSRanjani Sridharan if (sdev->pdata->ipc_type == SOF_IPC) { 668b98491aSRanjani Sridharan /* doorbell */ 6737e809d5SPierre-Louis Bossart sof_tgl_ops.irq_thread = cnl_ipc_irq_thread; 688b98491aSRanjani Sridharan 698b98491aSRanjani Sridharan /* ipc */ 7037e809d5SPierre-Louis Bossart sof_tgl_ops.send_msg = cnl_ipc_send_msg; 71e3105c0cSRanjani Sridharan } 72e3105c0cSRanjani Sridharan 73e3105c0cSRanjani Sridharan if (sdev->pdata->ipc_type == SOF_INTEL_IPC4) { 74a4cfdebdSRanjani Sridharan struct sof_ipc4_fw_data *ipc4_data; 75a4cfdebdSRanjani Sridharan 76a4cfdebdSRanjani Sridharan sdev->private = devm_kzalloc(sdev->dev, sizeof(*ipc4_data), GFP_KERNEL); 77a4cfdebdSRanjani Sridharan if (!sdev->private) 78a4cfdebdSRanjani Sridharan return -ENOMEM; 79a4cfdebdSRanjani Sridharan 80a4cfdebdSRanjani Sridharan ipc4_data = sdev->private; 81a4cfdebdSRanjani Sridharan ipc4_data->manifest_fw_hdr_offset = SOF_MAN4_FW_HDR_OFFSET; 82a4cfdebdSRanjani Sridharan 83cc4a3a19SPeter Ujfalusi ipc4_data->mtrace_type = SOF_IPC4_MTRACE_INTEL_CAVS_2; 84cc4a3a19SPeter Ujfalusi 85e3105c0cSRanjani Sridharan /* doorbell */ 86e3105c0cSRanjani Sridharan sof_tgl_ops.irq_thread = cnl_ipc4_irq_thread; 87e3105c0cSRanjani Sridharan 88e3105c0cSRanjani Sridharan /* ipc */ 89e3105c0cSRanjani Sridharan sof_tgl_ops.send_msg = cnl_ipc4_send_msg; 90e3105c0cSRanjani Sridharan } 918b98491aSRanjani Sridharan 9251ec71dcSRanjani Sridharan /* set DAI driver ops */ 9351ec71dcSRanjani Sridharan hda_set_dai_drv_ops(sdev, &sof_tgl_ops); 9451ec71dcSRanjani Sridharan 958b98491aSRanjani Sridharan /* debug */ 9637e809d5SPierre-Louis Bossart sof_tgl_ops.debug_map = tgl_dsp_debugfs; 9737e809d5SPierre-Louis Bossart sof_tgl_ops.debug_map_count = ARRAY_SIZE(tgl_dsp_debugfs); 9837e809d5SPierre-Louis Bossart sof_tgl_ops.ipc_dump = cnl_ipc_dump; 998b98491aSRanjani Sridharan 1008b98491aSRanjani Sridharan /* pre/post fw run */ 10137e809d5SPierre-Louis Bossart sof_tgl_ops.post_fw_run = hda_dsp_post_fw_run; 1028b98491aSRanjani Sridharan 1038b98491aSRanjani Sridharan /* firmware run */ 10437e809d5SPierre-Louis Bossart sof_tgl_ops.run = hda_dsp_cl_boot_firmware_iccmax; 1058b98491aSRanjani Sridharan 10637e809d5SPierre-Louis Bossart /* dsp core get/put */ 10737e809d5SPierre-Louis Bossart sof_tgl_ops.core_get = tgl_dsp_core_get; 10837e809d5SPierre-Louis Bossart sof_tgl_ops.core_put = tgl_dsp_core_put; 1098b98491aSRanjani Sridharan 11037e809d5SPierre-Louis Bossart return 0; 1118b98491aSRanjani Sridharan }; 11237e809d5SPierre-Louis Bossart EXPORT_SYMBOL_NS(sof_tgl_ops_init, SND_SOC_SOF_INTEL_HDA_COMMON); 1138b98491aSRanjani Sridharan 1148b98491aSRanjani Sridharan const struct sof_intel_dsp_desc tgl_chip_info = { 1154ad03f89SSathya Prakash M R /* Tigerlake , Alderlake */ 1168b98491aSRanjani Sridharan .cores_num = 4, 1178b98491aSRanjani Sridharan .init_core_mask = 1, 118fde10655SRanjani Sridharan .host_managed_cores_mask = BIT(0), 1198b98491aSRanjani Sridharan .ipc_req = CNL_DSP_REG_HIPCIDR, 1208b98491aSRanjani Sridharan .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY, 1218b98491aSRanjani Sridharan .ipc_ack = CNL_DSP_REG_HIPCIDA, 1228b98491aSRanjani Sridharan .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE, 1238b98491aSRanjani Sridharan .ipc_ctl = CNL_DSP_REG_HIPCCTL, 12471778f79SRanjani Sridharan .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS, 1258b98491aSRanjani Sridharan .rom_init_timeout = 300, 126*9ccbc2e1SPierre-Louis Bossart .ssp_count = TGL_SSP_COUNT, 1278b98491aSRanjani Sridharan .ssp_base_offset = CNL_SSP_BASE_OFFSET, 1281cbf6443SBard Liao .sdw_shim_base = SDW_SHIM_BASE, 1291cbf6443SBard Liao .sdw_alh_base = SDW_ALH_BASE, 130198fa4bcSBard Liao .check_sdw_irq = hda_common_check_sdw_irq, 1313dee239eSRanjani Sridharan .check_ipc_irq = hda_dsp_check_ipc_irq, 132ab222a4aSBard Liao .cl_init = cl_dsp_init, 13303cf7262SPierre-Louis Bossart .hw_ip_version = SOF_INTEL_CAVS_2_5, 1348b98491aSRanjani Sridharan }; 1358b98491aSRanjani Sridharan EXPORT_SYMBOL_NS(tgl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); 13630ee3738SRander Wang 13730ee3738SRander Wang const struct sof_intel_dsp_desc tglh_chip_info = { 13830ee3738SRander Wang /* Tigerlake-H */ 13930ee3738SRander Wang .cores_num = 2, 14030ee3738SRander Wang .init_core_mask = 1, 14130ee3738SRander Wang .host_managed_cores_mask = BIT(0), 14230ee3738SRander Wang .ipc_req = CNL_DSP_REG_HIPCIDR, 14330ee3738SRander Wang .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY, 14430ee3738SRander Wang .ipc_ack = CNL_DSP_REG_HIPCIDA, 14530ee3738SRander Wang .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE, 14630ee3738SRander Wang .ipc_ctl = CNL_DSP_REG_HIPCCTL, 14771778f79SRanjani Sridharan .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS, 14830ee3738SRander Wang .rom_init_timeout = 300, 149*9ccbc2e1SPierre-Louis Bossart .ssp_count = TGL_SSP_COUNT, 15030ee3738SRander Wang .ssp_base_offset = CNL_SSP_BASE_OFFSET, 1511cbf6443SBard Liao .sdw_shim_base = SDW_SHIM_BASE, 1521cbf6443SBard Liao .sdw_alh_base = SDW_ALH_BASE, 153198fa4bcSBard Liao .check_sdw_irq = hda_common_check_sdw_irq, 1543dee239eSRanjani Sridharan .check_ipc_irq = hda_dsp_check_ipc_irq, 155ab222a4aSBard Liao .cl_init = cl_dsp_init, 15603cf7262SPierre-Louis Bossart .hw_ip_version = SOF_INTEL_CAVS_2_5, 15730ee3738SRander Wang }; 15830ee3738SRander Wang EXPORT_SYMBOL_NS(tglh_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); 1596c2b6bb0SKai Vehmanen 1608bb84ca8SPierre-Louis Bossart const struct sof_intel_dsp_desc ehl_chip_info = { 1618bb84ca8SPierre-Louis Bossart /* Elkhartlake */ 1628bb84ca8SPierre-Louis Bossart .cores_num = 4, 1638bb84ca8SPierre-Louis Bossart .init_core_mask = 1, 1648bb84ca8SPierre-Louis Bossart .host_managed_cores_mask = BIT(0), 1658bb84ca8SPierre-Louis Bossart .ipc_req = CNL_DSP_REG_HIPCIDR, 1668bb84ca8SPierre-Louis Bossart .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY, 1678bb84ca8SPierre-Louis Bossart .ipc_ack = CNL_DSP_REG_HIPCIDA, 1688bb84ca8SPierre-Louis Bossart .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE, 1698bb84ca8SPierre-Louis Bossart .ipc_ctl = CNL_DSP_REG_HIPCCTL, 17071778f79SRanjani Sridharan .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS, 1718bb84ca8SPierre-Louis Bossart .rom_init_timeout = 300, 172*9ccbc2e1SPierre-Louis Bossart .ssp_count = TGL_SSP_COUNT, 1738bb84ca8SPierre-Louis Bossart .ssp_base_offset = CNL_SSP_BASE_OFFSET, 1741cbf6443SBard Liao .sdw_shim_base = SDW_SHIM_BASE, 1751cbf6443SBard Liao .sdw_alh_base = SDW_ALH_BASE, 176198fa4bcSBard Liao .check_sdw_irq = hda_common_check_sdw_irq, 1773dee239eSRanjani Sridharan .check_ipc_irq = hda_dsp_check_ipc_irq, 178ab222a4aSBard Liao .cl_init = cl_dsp_init, 17903cf7262SPierre-Louis Bossart .hw_ip_version = SOF_INTEL_CAVS_2_5, 1808bb84ca8SPierre-Louis Bossart }; 1818bb84ca8SPierre-Louis Bossart EXPORT_SYMBOL_NS(ehl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); 1828bb84ca8SPierre-Louis Bossart 1836c2b6bb0SKai Vehmanen const struct sof_intel_dsp_desc adls_chip_info = { 1846c2b6bb0SKai Vehmanen /* Alderlake-S */ 1856c2b6bb0SKai Vehmanen .cores_num = 2, 1866c2b6bb0SKai Vehmanen .init_core_mask = BIT(0), 1876c2b6bb0SKai Vehmanen .host_managed_cores_mask = BIT(0), 1886c2b6bb0SKai Vehmanen .ipc_req = CNL_DSP_REG_HIPCIDR, 1896c2b6bb0SKai Vehmanen .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY, 1906c2b6bb0SKai Vehmanen .ipc_ack = CNL_DSP_REG_HIPCIDA, 1916c2b6bb0SKai Vehmanen .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE, 1926c2b6bb0SKai Vehmanen .ipc_ctl = CNL_DSP_REG_HIPCCTL, 19371778f79SRanjani Sridharan .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS, 1946c2b6bb0SKai Vehmanen .rom_init_timeout = 300, 195*9ccbc2e1SPierre-Louis Bossart .ssp_count = TGL_SSP_COUNT, 1966c2b6bb0SKai Vehmanen .ssp_base_offset = CNL_SSP_BASE_OFFSET, 1971cbf6443SBard Liao .sdw_shim_base = SDW_SHIM_BASE, 1981cbf6443SBard Liao .sdw_alh_base = SDW_ALH_BASE, 199198fa4bcSBard Liao .check_sdw_irq = hda_common_check_sdw_irq, 2003dee239eSRanjani Sridharan .check_ipc_irq = hda_dsp_check_ipc_irq, 201ab222a4aSBard Liao .cl_init = cl_dsp_init, 20203cf7262SPierre-Louis Bossart .hw_ip_version = SOF_INTEL_CAVS_2_5, 2036c2b6bb0SKai Vehmanen }; 2046c2b6bb0SKai Vehmanen EXPORT_SYMBOL_NS(adls_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); 205