18b98491aSRanjani Sridharan // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 28b98491aSRanjani Sridharan // 38b98491aSRanjani Sridharan // Copyright(c) 2020 Intel Corporation. All rights reserved. 48b98491aSRanjani Sridharan // 58b98491aSRanjani Sridharan // Authors: Ranjani Sridharan <ranjani.sridharan@linux.intel.com> 68b98491aSRanjani Sridharan // 78b98491aSRanjani Sridharan 88b98491aSRanjani Sridharan /* 98b98491aSRanjani Sridharan * Hardware interface for audio DSP on Tigerlake. 108b98491aSRanjani Sridharan */ 118b98491aSRanjani Sridharan 128b98491aSRanjani Sridharan #include "../ops.h" 138b98491aSRanjani Sridharan #include "hda.h" 148b98491aSRanjani Sridharan #include "hda-ipc.h" 158b98491aSRanjani Sridharan #include "../sof-audio.h" 168b98491aSRanjani Sridharan 178b98491aSRanjani Sridharan static const struct snd_sof_debugfs_map tgl_dsp_debugfs[] = { 188b98491aSRanjani Sridharan {"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS}, 198b98491aSRanjani Sridharan {"pp", HDA_DSP_PP_BAR, 0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS}, 208b98491aSRanjani Sridharan {"dsp", HDA_DSP_BAR, 0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS}, 218b98491aSRanjani Sridharan }; 228b98491aSRanjani Sridharan 238b98491aSRanjani Sridharan /* Tigerlake ops */ 248b98491aSRanjani Sridharan const struct snd_sof_dsp_ops sof_tgl_ops = { 2544a4cfadSKeyon Jie /* probe/remove/shutdown */ 268b98491aSRanjani Sridharan .probe = hda_dsp_probe, 278b98491aSRanjani Sridharan .remove = hda_dsp_remove, 2822aa9e02SLibin Yang .shutdown = hda_dsp_shutdown, 298b98491aSRanjani Sridharan 308b98491aSRanjani Sridharan /* Register IO */ 318b98491aSRanjani Sridharan .write = sof_io_write, 328b98491aSRanjani Sridharan .read = sof_io_read, 338b98491aSRanjani Sridharan .write64 = sof_io_write64, 348b98491aSRanjani Sridharan .read64 = sof_io_read64, 358b98491aSRanjani Sridharan 368b98491aSRanjani Sridharan /* Block IO */ 378b98491aSRanjani Sridharan .block_read = sof_block_read, 388b98491aSRanjani Sridharan .block_write = sof_block_write, 398b98491aSRanjani Sridharan 408b98491aSRanjani Sridharan /* doorbell */ 418b98491aSRanjani Sridharan .irq_thread = cnl_ipc_irq_thread, 428b98491aSRanjani Sridharan 438b98491aSRanjani Sridharan /* ipc */ 448b98491aSRanjani Sridharan .send_msg = cnl_ipc_send_msg, 458b98491aSRanjani Sridharan .fw_ready = sof_fw_ready, 468b98491aSRanjani Sridharan .get_mailbox_offset = hda_dsp_ipc_get_mailbox_offset, 478b98491aSRanjani Sridharan .get_window_offset = hda_dsp_ipc_get_window_offset, 488b98491aSRanjani Sridharan 498b98491aSRanjani Sridharan .ipc_msg_data = hda_ipc_msg_data, 508b98491aSRanjani Sridharan .ipc_pcm_params = hda_ipc_pcm_params, 518b98491aSRanjani Sridharan 528b98491aSRanjani Sridharan /* machine driver */ 538b98491aSRanjani Sridharan .machine_select = hda_machine_select, 548b98491aSRanjani Sridharan .machine_register = sof_machine_register, 558b98491aSRanjani Sridharan .machine_unregister = sof_machine_unregister, 568b98491aSRanjani Sridharan .set_mach_params = hda_set_mach_params, 578b98491aSRanjani Sridharan 588b98491aSRanjani Sridharan /* debug */ 598b98491aSRanjani Sridharan .debug_map = tgl_dsp_debugfs, 608b98491aSRanjani Sridharan .debug_map_count = ARRAY_SIZE(tgl_dsp_debugfs), 618b98491aSRanjani Sridharan .dbg_dump = hda_dsp_dump, 628b98491aSRanjani Sridharan .ipc_dump = cnl_ipc_dump, 638b98491aSRanjani Sridharan 648b98491aSRanjani Sridharan /* stream callbacks */ 658b98491aSRanjani Sridharan .pcm_open = hda_dsp_pcm_open, 668b98491aSRanjani Sridharan .pcm_close = hda_dsp_pcm_close, 678b98491aSRanjani Sridharan .pcm_hw_params = hda_dsp_pcm_hw_params, 688b98491aSRanjani Sridharan .pcm_hw_free = hda_dsp_stream_hw_free, 698b98491aSRanjani Sridharan .pcm_trigger = hda_dsp_pcm_trigger, 708b98491aSRanjani Sridharan .pcm_pointer = hda_dsp_pcm_pointer, 718b98491aSRanjani Sridharan 728b98491aSRanjani Sridharan #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_PROBES) 738b98491aSRanjani Sridharan /* probe callbacks */ 748b98491aSRanjani Sridharan .probe_assign = hda_probe_compr_assign, 758b98491aSRanjani Sridharan .probe_free = hda_probe_compr_free, 768b98491aSRanjani Sridharan .probe_set_params = hda_probe_compr_set_params, 778b98491aSRanjani Sridharan .probe_trigger = hda_probe_compr_trigger, 788b98491aSRanjani Sridharan .probe_pointer = hda_probe_compr_pointer, 798b98491aSRanjani Sridharan #endif 808b98491aSRanjani Sridharan 818b98491aSRanjani Sridharan /* firmware loading */ 828b98491aSRanjani Sridharan .load_firmware = snd_sof_load_firmware_raw, 838b98491aSRanjani Sridharan 848b98491aSRanjani Sridharan /* pre/post fw run */ 858b98491aSRanjani Sridharan .pre_fw_run = hda_dsp_pre_fw_run, 868b98491aSRanjani Sridharan .post_fw_run = hda_dsp_post_fw_run, 878b98491aSRanjani Sridharan 88edbaaadaSFred Oh /* parse platform specific extended manifest */ 89edbaaadaSFred Oh .parse_platform_ext_manifest = hda_dsp_ext_man_get_cavs_config_data, 90edbaaadaSFred Oh 918b98491aSRanjani Sridharan /* dsp core power up/down */ 928b98491aSRanjani Sridharan .core_power_up = hda_dsp_enable_core, 938b98491aSRanjani Sridharan .core_power_down = hda_dsp_core_reset_power_down, 948b98491aSRanjani Sridharan 958b98491aSRanjani Sridharan /* firmware run */ 968b98491aSRanjani Sridharan .run = hda_dsp_cl_boot_firmware_iccmax, 978b98491aSRanjani Sridharan 988b98491aSRanjani Sridharan /* trace callback */ 998b98491aSRanjani Sridharan .trace_init = hda_dsp_trace_init, 1008b98491aSRanjani Sridharan .trace_release = hda_dsp_trace_release, 1018b98491aSRanjani Sridharan .trace_trigger = hda_dsp_trace_trigger, 1028b98491aSRanjani Sridharan 1038b98491aSRanjani Sridharan /* DAI drivers */ 1048b98491aSRanjani Sridharan .drv = skl_dai, 1058b98491aSRanjani Sridharan .num_drv = SOF_SKL_NUM_DAIS, 1068b98491aSRanjani Sridharan 1078b98491aSRanjani Sridharan /* PM */ 1088b98491aSRanjani Sridharan .suspend = hda_dsp_suspend, 1098b98491aSRanjani Sridharan .resume = hda_dsp_resume, 1108b98491aSRanjani Sridharan .runtime_suspend = hda_dsp_runtime_suspend, 1118b98491aSRanjani Sridharan .runtime_resume = hda_dsp_runtime_resume, 1128b98491aSRanjani Sridharan .runtime_idle = hda_dsp_runtime_idle, 1138b98491aSRanjani Sridharan .set_hw_params_upon_resume = hda_dsp_set_hw_params_upon_resume, 1148b98491aSRanjani Sridharan .set_power_state = hda_dsp_set_power_state, 1158b98491aSRanjani Sridharan 1168b98491aSRanjani Sridharan /* ALSA HW info flags */ 1178b98491aSRanjani Sridharan .hw_info = SNDRV_PCM_INFO_MMAP | 1188b98491aSRanjani Sridharan SNDRV_PCM_INFO_MMAP_VALID | 1198b98491aSRanjani Sridharan SNDRV_PCM_INFO_INTERLEAVED | 1208b98491aSRanjani Sridharan SNDRV_PCM_INFO_PAUSE | 1218b98491aSRanjani Sridharan SNDRV_PCM_INFO_NO_PERIOD_WAKEUP, 1228b98491aSRanjani Sridharan 1238b98491aSRanjani Sridharan .arch_ops = &sof_xtensa_arch_ops, 1248b98491aSRanjani Sridharan }; 1258b98491aSRanjani Sridharan EXPORT_SYMBOL_NS(sof_tgl_ops, SND_SOC_SOF_INTEL_HDA_COMMON); 1268b98491aSRanjani Sridharan 1278b98491aSRanjani Sridharan const struct sof_intel_dsp_desc tgl_chip_info = { 1288b98491aSRanjani Sridharan /* Tigerlake */ 1298b98491aSRanjani Sridharan .cores_num = 4, 1308b98491aSRanjani Sridharan .init_core_mask = 1, 131fde10655SRanjani Sridharan .host_managed_cores_mask = BIT(0), 1328b98491aSRanjani Sridharan .ipc_req = CNL_DSP_REG_HIPCIDR, 1338b98491aSRanjani Sridharan .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY, 1348b98491aSRanjani Sridharan .ipc_ack = CNL_DSP_REG_HIPCIDA, 1358b98491aSRanjani Sridharan .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE, 1368b98491aSRanjani Sridharan .ipc_ctl = CNL_DSP_REG_HIPCCTL, 1378b98491aSRanjani Sridharan .rom_init_timeout = 300, 1388b98491aSRanjani Sridharan .ssp_count = ICL_SSP_COUNT, 1398b98491aSRanjani Sridharan .ssp_base_offset = CNL_SSP_BASE_OFFSET, 1408b98491aSRanjani Sridharan }; 1418b98491aSRanjani Sridharan EXPORT_SYMBOL_NS(tgl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); 14230ee3738SRander Wang 14330ee3738SRander Wang const struct sof_intel_dsp_desc tglh_chip_info = { 14430ee3738SRander Wang /* Tigerlake-H */ 14530ee3738SRander Wang .cores_num = 2, 14630ee3738SRander Wang .init_core_mask = 1, 14730ee3738SRander Wang .host_managed_cores_mask = BIT(0), 14830ee3738SRander Wang .ipc_req = CNL_DSP_REG_HIPCIDR, 14930ee3738SRander Wang .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY, 15030ee3738SRander Wang .ipc_ack = CNL_DSP_REG_HIPCIDA, 15130ee3738SRander Wang .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE, 15230ee3738SRander Wang .ipc_ctl = CNL_DSP_REG_HIPCCTL, 15330ee3738SRander Wang .rom_init_timeout = 300, 15430ee3738SRander Wang .ssp_count = ICL_SSP_COUNT, 15530ee3738SRander Wang .ssp_base_offset = CNL_SSP_BASE_OFFSET, 15630ee3738SRander Wang }; 15730ee3738SRander Wang EXPORT_SYMBOL_NS(tglh_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); 1586c2b6bb0SKai Vehmanen 159*8bb84ca8SPierre-Louis Bossart const struct sof_intel_dsp_desc ehl_chip_info = { 160*8bb84ca8SPierre-Louis Bossart /* Elkhartlake */ 161*8bb84ca8SPierre-Louis Bossart .cores_num = 4, 162*8bb84ca8SPierre-Louis Bossart .init_core_mask = 1, 163*8bb84ca8SPierre-Louis Bossart .host_managed_cores_mask = BIT(0), 164*8bb84ca8SPierre-Louis Bossart .ipc_req = CNL_DSP_REG_HIPCIDR, 165*8bb84ca8SPierre-Louis Bossart .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY, 166*8bb84ca8SPierre-Louis Bossart .ipc_ack = CNL_DSP_REG_HIPCIDA, 167*8bb84ca8SPierre-Louis Bossart .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE, 168*8bb84ca8SPierre-Louis Bossart .ipc_ctl = CNL_DSP_REG_HIPCCTL, 169*8bb84ca8SPierre-Louis Bossart .rom_init_timeout = 300, 170*8bb84ca8SPierre-Louis Bossart .ssp_count = ICL_SSP_COUNT, 171*8bb84ca8SPierre-Louis Bossart .ssp_base_offset = CNL_SSP_BASE_OFFSET, 172*8bb84ca8SPierre-Louis Bossart }; 173*8bb84ca8SPierre-Louis Bossart EXPORT_SYMBOL_NS(ehl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); 174*8bb84ca8SPierre-Louis Bossart 1756c2b6bb0SKai Vehmanen const struct sof_intel_dsp_desc adls_chip_info = { 1766c2b6bb0SKai Vehmanen /* Alderlake-S */ 1776c2b6bb0SKai Vehmanen .cores_num = 2, 1786c2b6bb0SKai Vehmanen .init_core_mask = BIT(0), 1796c2b6bb0SKai Vehmanen .host_managed_cores_mask = BIT(0), 1806c2b6bb0SKai Vehmanen .ipc_req = CNL_DSP_REG_HIPCIDR, 1816c2b6bb0SKai Vehmanen .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY, 1826c2b6bb0SKai Vehmanen .ipc_ack = CNL_DSP_REG_HIPCIDA, 1836c2b6bb0SKai Vehmanen .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE, 1846c2b6bb0SKai Vehmanen .ipc_ctl = CNL_DSP_REG_HIPCCTL, 1856c2b6bb0SKai Vehmanen .rom_init_timeout = 300, 1866c2b6bb0SKai Vehmanen .ssp_count = ICL_SSP_COUNT, 1876c2b6bb0SKai Vehmanen .ssp_base_offset = CNL_SSP_BASE_OFFSET, 1886c2b6bb0SKai Vehmanen }; 1896c2b6bb0SKai Vehmanen EXPORT_SYMBOL_NS(adls_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); 190