18b98491aSRanjani Sridharan // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
28b98491aSRanjani Sridharan //
38b98491aSRanjani Sridharan // Copyright(c) 2020 Intel Corporation. All rights reserved.
48b98491aSRanjani Sridharan //
58b98491aSRanjani Sridharan // Authors: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
68b98491aSRanjani Sridharan //
78b98491aSRanjani Sridharan
88b98491aSRanjani Sridharan /*
98b98491aSRanjani Sridharan * Hardware interface for audio DSP on Tigerlake.
108b98491aSRanjani Sridharan */
118b98491aSRanjani Sridharan
12a4cfdebdSRanjani Sridharan #include <sound/sof/ext_manifest4.h>
13a4cfdebdSRanjani Sridharan #include "../ipc4-priv.h"
148b98491aSRanjani Sridharan #include "../ops.h"
158b98491aSRanjani Sridharan #include "hda.h"
168b98491aSRanjani Sridharan #include "hda-ipc.h"
178b98491aSRanjani Sridharan #include "../sof-audio.h"
188b98491aSRanjani Sridharan
198b98491aSRanjani Sridharan static const struct snd_sof_debugfs_map tgl_dsp_debugfs[] = {
208b98491aSRanjani Sridharan {"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS},
218b98491aSRanjani Sridharan {"pp", HDA_DSP_PP_BAR, 0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS},
228b98491aSRanjani Sridharan {"dsp", HDA_DSP_BAR, 0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS},
238b98491aSRanjani Sridharan };
248b98491aSRanjani Sridharan
tgl_dsp_core_get(struct snd_sof_dev * sdev,int core)2541dd63ccSRanjani Sridharan static int tgl_dsp_core_get(struct snd_sof_dev *sdev, int core)
2641dd63ccSRanjani Sridharan {
277a567740SPeter Ujfalusi const struct sof_ipc_pm_ops *pm_ops = sdev->ipc->ops->pm;
2841dd63ccSRanjani Sridharan
2941dd63ccSRanjani Sridharan /* power up primary core if not already powered up and return */
3041dd63ccSRanjani Sridharan if (core == SOF_DSP_PRIMARY_CORE)
3141dd63ccSRanjani Sridharan return hda_dsp_enable_core(sdev, BIT(core));
3241dd63ccSRanjani Sridharan
337a567740SPeter Ujfalusi if (pm_ops->set_core_state)
347a567740SPeter Ujfalusi return pm_ops->set_core_state(sdev, core, true);
357a567740SPeter Ujfalusi
367a567740SPeter Ujfalusi return 0;
3741dd63ccSRanjani Sridharan }
3841dd63ccSRanjani Sridharan
tgl_dsp_core_put(struct snd_sof_dev * sdev,int core)3941dd63ccSRanjani Sridharan static int tgl_dsp_core_put(struct snd_sof_dev *sdev, int core)
4041dd63ccSRanjani Sridharan {
417a567740SPeter Ujfalusi const struct sof_ipc_pm_ops *pm_ops = sdev->ipc->ops->pm;
421b167ba8SRander Wang int ret;
431b167ba8SRander Wang
441b167ba8SRander Wang if (pm_ops->set_core_state) {
451b167ba8SRander Wang ret = pm_ops->set_core_state(sdev, core, false);
461b167ba8SRander Wang if (ret < 0)
471b167ba8SRander Wang return ret;
481b167ba8SRander Wang }
4941dd63ccSRanjani Sridharan
5041dd63ccSRanjani Sridharan /* power down primary core and return */
5141dd63ccSRanjani Sridharan if (core == SOF_DSP_PRIMARY_CORE)
5241dd63ccSRanjani Sridharan return hda_dsp_core_reset_power_down(sdev, BIT(core));
5341dd63ccSRanjani Sridharan
547a567740SPeter Ujfalusi return 0;
5541dd63ccSRanjani Sridharan }
5641dd63ccSRanjani Sridharan
578b98491aSRanjani Sridharan /* Tigerlake ops */
5837e809d5SPierre-Louis Bossart struct snd_sof_dsp_ops sof_tgl_ops;
5937e809d5SPierre-Louis Bossart EXPORT_SYMBOL_NS(sof_tgl_ops, SND_SOC_SOF_INTEL_HDA_COMMON);
6037e809d5SPierre-Louis Bossart
sof_tgl_ops_init(struct snd_sof_dev * sdev)6137e809d5SPierre-Louis Bossart int sof_tgl_ops_init(struct snd_sof_dev *sdev)
6237e809d5SPierre-Louis Bossart {
6337e809d5SPierre-Louis Bossart /* common defaults */
6437e809d5SPierre-Louis Bossart memcpy(&sof_tgl_ops, &sof_hda_common_ops, sizeof(struct snd_sof_dsp_ops));
6537e809d5SPierre-Louis Bossart
6644a4cfadSKeyon Jie /* probe/remove/shutdown */
672aa2a5eaSKai Vehmanen sof_tgl_ops.shutdown = hda_dsp_shutdown_dma_flush;
68f71f59ddSDaniel Baluta
69e3105c0cSRanjani Sridharan if (sdev->pdata->ipc_type == SOF_IPC) {
708b98491aSRanjani Sridharan /* doorbell */
7137e809d5SPierre-Louis Bossart sof_tgl_ops.irq_thread = cnl_ipc_irq_thread;
728b98491aSRanjani Sridharan
738b98491aSRanjani Sridharan /* ipc */
7437e809d5SPierre-Louis Bossart sof_tgl_ops.send_msg = cnl_ipc_send_msg;
75a996a333SPeter Ujfalusi
76a996a333SPeter Ujfalusi /* debug */
77a996a333SPeter Ujfalusi sof_tgl_ops.ipc_dump = cnl_ipc_dump;
78996b07efSRanjani Sridharan
79996b07efSRanjani Sridharan sof_tgl_ops.set_power_state = hda_dsp_set_power_state_ipc3;
80e3105c0cSRanjani Sridharan }
81e3105c0cSRanjani Sridharan
82e3105c0cSRanjani Sridharan if (sdev->pdata->ipc_type == SOF_INTEL_IPC4) {
83a4cfdebdSRanjani Sridharan struct sof_ipc4_fw_data *ipc4_data;
84a4cfdebdSRanjani Sridharan
85a4cfdebdSRanjani Sridharan sdev->private = devm_kzalloc(sdev->dev, sizeof(*ipc4_data), GFP_KERNEL);
86a4cfdebdSRanjani Sridharan if (!sdev->private)
87a4cfdebdSRanjani Sridharan return -ENOMEM;
88a4cfdebdSRanjani Sridharan
89a4cfdebdSRanjani Sridharan ipc4_data = sdev->private;
90a4cfdebdSRanjani Sridharan ipc4_data->manifest_fw_hdr_offset = SOF_MAN4_FW_HDR_OFFSET;
91a4cfdebdSRanjani Sridharan
92cc4a3a19SPeter Ujfalusi ipc4_data->mtrace_type = SOF_IPC4_MTRACE_INTEL_CAVS_2;
93cc4a3a19SPeter Ujfalusi
943ab2c21eSPeter Ujfalusi /* External library loading support */
953ab2c21eSPeter Ujfalusi ipc4_data->load_library = hda_dsp_ipc4_load_library;
963ab2c21eSPeter Ujfalusi
97e3105c0cSRanjani Sridharan /* doorbell */
98e3105c0cSRanjani Sridharan sof_tgl_ops.irq_thread = cnl_ipc4_irq_thread;
99e3105c0cSRanjani Sridharan
100e3105c0cSRanjani Sridharan /* ipc */
101e3105c0cSRanjani Sridharan sof_tgl_ops.send_msg = cnl_ipc4_send_msg;
102a996a333SPeter Ujfalusi
103a996a333SPeter Ujfalusi /* debug */
104a996a333SPeter Ujfalusi sof_tgl_ops.ipc_dump = cnl_ipc4_dump;
105996b07efSRanjani Sridharan
106996b07efSRanjani Sridharan sof_tgl_ops.set_power_state = hda_dsp_set_power_state_ipc4;
107e3105c0cSRanjani Sridharan }
1088b98491aSRanjani Sridharan
10951ec71dcSRanjani Sridharan /* set DAI driver ops */
11051ec71dcSRanjani Sridharan hda_set_dai_drv_ops(sdev, &sof_tgl_ops);
11151ec71dcSRanjani Sridharan
1128b98491aSRanjani Sridharan /* debug */
11337e809d5SPierre-Louis Bossart sof_tgl_ops.debug_map = tgl_dsp_debugfs;
11437e809d5SPierre-Louis Bossart sof_tgl_ops.debug_map_count = ARRAY_SIZE(tgl_dsp_debugfs);
1158b98491aSRanjani Sridharan
1168b98491aSRanjani Sridharan /* pre/post fw run */
11737e809d5SPierre-Louis Bossart sof_tgl_ops.post_fw_run = hda_dsp_post_fw_run;
1188b98491aSRanjani Sridharan
1198b98491aSRanjani Sridharan /* firmware run */
12037e809d5SPierre-Louis Bossart sof_tgl_ops.run = hda_dsp_cl_boot_firmware_iccmax;
1218b98491aSRanjani Sridharan
12237e809d5SPierre-Louis Bossart /* dsp core get/put */
12337e809d5SPierre-Louis Bossart sof_tgl_ops.core_get = tgl_dsp_core_get;
12437e809d5SPierre-Louis Bossart sof_tgl_ops.core_put = tgl_dsp_core_put;
1258b98491aSRanjani Sridharan
12637e809d5SPierre-Louis Bossart return 0;
1278b98491aSRanjani Sridharan };
12837e809d5SPierre-Louis Bossart EXPORT_SYMBOL_NS(sof_tgl_ops_init, SND_SOC_SOF_INTEL_HDA_COMMON);
1298b98491aSRanjani Sridharan
1308b98491aSRanjani Sridharan const struct sof_intel_dsp_desc tgl_chip_info = {
1314ad03f89SSathya Prakash M R /* Tigerlake , Alderlake */
1328b98491aSRanjani Sridharan .cores_num = 4,
1338b98491aSRanjani Sridharan .init_core_mask = 1,
134fde10655SRanjani Sridharan .host_managed_cores_mask = BIT(0),
1358b98491aSRanjani Sridharan .ipc_req = CNL_DSP_REG_HIPCIDR,
1368b98491aSRanjani Sridharan .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
1378b98491aSRanjani Sridharan .ipc_ack = CNL_DSP_REG_HIPCIDA,
1388b98491aSRanjani Sridharan .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
1398b98491aSRanjani Sridharan .ipc_ctl = CNL_DSP_REG_HIPCCTL,
14071778f79SRanjani Sridharan .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS,
1418b98491aSRanjani Sridharan .rom_init_timeout = 300,
1429ccbc2e1SPierre-Louis Bossart .ssp_count = TGL_SSP_COUNT,
1438b98491aSRanjani Sridharan .ssp_base_offset = CNL_SSP_BASE_OFFSET,
1441cbf6443SBard Liao .sdw_shim_base = SDW_SHIM_BASE,
1451cbf6443SBard Liao .sdw_alh_base = SDW_ALH_BASE,
146f8632adcSRander Wang .d0i3_offset = SOF_HDA_VS_D0I3C,
147625339caSPierre-Louis Bossart .read_sdw_lcount = hda_sdw_check_lcount_common,
1488ebc9074SPierre-Louis Bossart .enable_sdw_irq = hda_common_enable_sdw_irq,
149198fa4bcSBard Liao .check_sdw_irq = hda_common_check_sdw_irq,
150*9362ab78SPierre-Louis Bossart .check_sdw_wakeen_irq = hda_sdw_check_wakeen_irq_common,
1513dee239eSRanjani Sridharan .check_ipc_irq = hda_dsp_check_ipc_irq,
152ab222a4aSBard Liao .cl_init = cl_dsp_init,
153c714031fSFred Oh .power_down_dsp = hda_power_down_dsp,
154b2520dbcSRanjani Sridharan .disable_interrupts = hda_dsp_disable_interrupts,
15503cf7262SPierre-Louis Bossart .hw_ip_version = SOF_INTEL_CAVS_2_5,
1568b98491aSRanjani Sridharan };
1578b98491aSRanjani Sridharan EXPORT_SYMBOL_NS(tgl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
15830ee3738SRander Wang
15930ee3738SRander Wang const struct sof_intel_dsp_desc tglh_chip_info = {
16030ee3738SRander Wang /* Tigerlake-H */
16130ee3738SRander Wang .cores_num = 2,
16230ee3738SRander Wang .init_core_mask = 1,
16330ee3738SRander Wang .host_managed_cores_mask = BIT(0),
16430ee3738SRander Wang .ipc_req = CNL_DSP_REG_HIPCIDR,
16530ee3738SRander Wang .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
16630ee3738SRander Wang .ipc_ack = CNL_DSP_REG_HIPCIDA,
16730ee3738SRander Wang .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
16830ee3738SRander Wang .ipc_ctl = CNL_DSP_REG_HIPCCTL,
16971778f79SRanjani Sridharan .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS,
17030ee3738SRander Wang .rom_init_timeout = 300,
1719ccbc2e1SPierre-Louis Bossart .ssp_count = TGL_SSP_COUNT,
17230ee3738SRander Wang .ssp_base_offset = CNL_SSP_BASE_OFFSET,
1731cbf6443SBard Liao .sdw_shim_base = SDW_SHIM_BASE,
1741cbf6443SBard Liao .sdw_alh_base = SDW_ALH_BASE,
175f8632adcSRander Wang .d0i3_offset = SOF_HDA_VS_D0I3C,
176625339caSPierre-Louis Bossart .read_sdw_lcount = hda_sdw_check_lcount_common,
1778ebc9074SPierre-Louis Bossart .enable_sdw_irq = hda_common_enable_sdw_irq,
178198fa4bcSBard Liao .check_sdw_irq = hda_common_check_sdw_irq,
179*9362ab78SPierre-Louis Bossart .check_sdw_wakeen_irq = hda_sdw_check_wakeen_irq_common,
1803dee239eSRanjani Sridharan .check_ipc_irq = hda_dsp_check_ipc_irq,
181ab222a4aSBard Liao .cl_init = cl_dsp_init,
182c714031fSFred Oh .power_down_dsp = hda_power_down_dsp,
183b2520dbcSRanjani Sridharan .disable_interrupts = hda_dsp_disable_interrupts,
18403cf7262SPierre-Louis Bossart .hw_ip_version = SOF_INTEL_CAVS_2_5,
18530ee3738SRander Wang };
18630ee3738SRander Wang EXPORT_SYMBOL_NS(tglh_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
1876c2b6bb0SKai Vehmanen
1888bb84ca8SPierre-Louis Bossart const struct sof_intel_dsp_desc ehl_chip_info = {
1898bb84ca8SPierre-Louis Bossart /* Elkhartlake */
1908bb84ca8SPierre-Louis Bossart .cores_num = 4,
1918bb84ca8SPierre-Louis Bossart .init_core_mask = 1,
1928bb84ca8SPierre-Louis Bossart .host_managed_cores_mask = BIT(0),
1938bb84ca8SPierre-Louis Bossart .ipc_req = CNL_DSP_REG_HIPCIDR,
1948bb84ca8SPierre-Louis Bossart .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
1958bb84ca8SPierre-Louis Bossart .ipc_ack = CNL_DSP_REG_HIPCIDA,
1968bb84ca8SPierre-Louis Bossart .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
1978bb84ca8SPierre-Louis Bossart .ipc_ctl = CNL_DSP_REG_HIPCCTL,
19871778f79SRanjani Sridharan .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS,
1998bb84ca8SPierre-Louis Bossart .rom_init_timeout = 300,
2009ccbc2e1SPierre-Louis Bossart .ssp_count = TGL_SSP_COUNT,
2018bb84ca8SPierre-Louis Bossart .ssp_base_offset = CNL_SSP_BASE_OFFSET,
2021cbf6443SBard Liao .sdw_shim_base = SDW_SHIM_BASE,
2031cbf6443SBard Liao .sdw_alh_base = SDW_ALH_BASE,
204f8632adcSRander Wang .d0i3_offset = SOF_HDA_VS_D0I3C,
205625339caSPierre-Louis Bossart .read_sdw_lcount = hda_sdw_check_lcount_common,
2068ebc9074SPierre-Louis Bossart .enable_sdw_irq = hda_common_enable_sdw_irq,
207198fa4bcSBard Liao .check_sdw_irq = hda_common_check_sdw_irq,
208*9362ab78SPierre-Louis Bossart .check_sdw_wakeen_irq = hda_sdw_check_wakeen_irq_common,
2093dee239eSRanjani Sridharan .check_ipc_irq = hda_dsp_check_ipc_irq,
210ab222a4aSBard Liao .cl_init = cl_dsp_init,
211c714031fSFred Oh .power_down_dsp = hda_power_down_dsp,
212b2520dbcSRanjani Sridharan .disable_interrupts = hda_dsp_disable_interrupts,
21303cf7262SPierre-Louis Bossart .hw_ip_version = SOF_INTEL_CAVS_2_5,
2148bb84ca8SPierre-Louis Bossart };
2158bb84ca8SPierre-Louis Bossart EXPORT_SYMBOL_NS(ehl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
2168bb84ca8SPierre-Louis Bossart
2176c2b6bb0SKai Vehmanen const struct sof_intel_dsp_desc adls_chip_info = {
2186c2b6bb0SKai Vehmanen /* Alderlake-S */
2196c2b6bb0SKai Vehmanen .cores_num = 2,
2206c2b6bb0SKai Vehmanen .init_core_mask = BIT(0),
2216c2b6bb0SKai Vehmanen .host_managed_cores_mask = BIT(0),
2226c2b6bb0SKai Vehmanen .ipc_req = CNL_DSP_REG_HIPCIDR,
2236c2b6bb0SKai Vehmanen .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
2246c2b6bb0SKai Vehmanen .ipc_ack = CNL_DSP_REG_HIPCIDA,
2256c2b6bb0SKai Vehmanen .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
2266c2b6bb0SKai Vehmanen .ipc_ctl = CNL_DSP_REG_HIPCCTL,
22771778f79SRanjani Sridharan .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS,
2286c2b6bb0SKai Vehmanen .rom_init_timeout = 300,
2299ccbc2e1SPierre-Louis Bossart .ssp_count = TGL_SSP_COUNT,
2306c2b6bb0SKai Vehmanen .ssp_base_offset = CNL_SSP_BASE_OFFSET,
2311cbf6443SBard Liao .sdw_shim_base = SDW_SHIM_BASE,
2321cbf6443SBard Liao .sdw_alh_base = SDW_ALH_BASE,
233f8632adcSRander Wang .d0i3_offset = SOF_HDA_VS_D0I3C,
234625339caSPierre-Louis Bossart .read_sdw_lcount = hda_sdw_check_lcount_common,
2358ebc9074SPierre-Louis Bossart .enable_sdw_irq = hda_common_enable_sdw_irq,
236198fa4bcSBard Liao .check_sdw_irq = hda_common_check_sdw_irq,
237*9362ab78SPierre-Louis Bossart .check_sdw_wakeen_irq = hda_sdw_check_wakeen_irq_common,
2383dee239eSRanjani Sridharan .check_ipc_irq = hda_dsp_check_ipc_irq,
239ab222a4aSBard Liao .cl_init = cl_dsp_init,
240c714031fSFred Oh .power_down_dsp = hda_power_down_dsp,
241b2520dbcSRanjani Sridharan .disable_interrupts = hda_dsp_disable_interrupts,
24203cf7262SPierre-Louis Bossart .hw_ip_version = SOF_INTEL_CAVS_2_5,
2436c2b6bb0SKai Vehmanen };
2446c2b6bb0SKai Vehmanen EXPORT_SYMBOL_NS(adls_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
245