1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 // 3 // This file is provided under a dual BSD/GPLv2 license. When using or 4 // redistributing this file, you may do so under either license. 5 // 6 // Copyright(c) 2018-2022 Intel Corporation. All rights reserved. 7 // 8 9 /* 10 * Hardware interface for audio DSP on Skylake and Kabylake. 11 */ 12 13 #include <linux/delay.h> 14 #include <linux/device.h> 15 #include <linux/dma-mapping.h> 16 #include <linux/firmware.h> 17 #include <linux/fs.h> 18 #include <linux/interrupt.h> 19 #include <linux/module.h> 20 #include <linux/slab.h> 21 #include <linux/pci.h> 22 #include <linux/pm_runtime.h> 23 #include <sound/hdaudio_ext.h> 24 #include <sound/pcm_params.h> 25 #include <sound/sof.h> 26 #include <sound/sof/ext_manifest4.h> 27 28 #include "../sof-priv.h" 29 #include "../ipc4-priv.h" 30 #include "../ops.h" 31 #include "hda.h" 32 #include "../sof-audio.h" 33 34 #define SRAM_MEMORY_WINDOW_BASE 0x8000 35 36 static const __maybe_unused struct snd_sof_debugfs_map skl_dsp_debugfs[] = { 37 {"hda", HDA_DSP_HDA_BAR, 0, 0x4000}, 38 {"pp", HDA_DSP_PP_BAR, 0, 0x1000}, 39 {"dsp", HDA_DSP_BAR, 0, 0x10000}, 40 }; 41 42 static int skl_dsp_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id) 43 { 44 return SRAM_MEMORY_WINDOW_BASE + (0x2000 * id); 45 } 46 47 static int skl_dsp_ipc_get_mailbox_offset(struct snd_sof_dev *sdev) 48 { 49 return SRAM_MEMORY_WINDOW_BASE + 0x1000; 50 } 51 52 /* skylake ops */ 53 struct snd_sof_dsp_ops sof_skl_ops; 54 EXPORT_SYMBOL_NS(sof_skl_ops, SND_SOC_SOF_INTEL_HDA_COMMON); 55 56 int sof_skl_ops_init(struct snd_sof_dev *sdev) 57 { 58 struct sof_ipc4_fw_data *ipc4_data; 59 60 /* common defaults */ 61 memcpy(&sof_skl_ops, &sof_hda_common_ops, sizeof(struct snd_sof_dsp_ops)); 62 63 /* probe/remove/shutdown */ 64 sof_skl_ops.shutdown = hda_dsp_shutdown; 65 66 sdev->private = devm_kzalloc(sdev->dev, sizeof(*ipc4_data), GFP_KERNEL); 67 if (!sdev->private) 68 return -ENOMEM; 69 70 ipc4_data = sdev->private; 71 ipc4_data->manifest_fw_hdr_offset = SOF_MAN4_FW_HDR_OFFSET_CAVS_1_5; 72 73 ipc4_data->mtrace_type = SOF_IPC4_MTRACE_INTEL_CAVS_1_5; 74 75 sof_skl_ops.get_window_offset = skl_dsp_ipc_get_window_offset; 76 sof_skl_ops.get_mailbox_offset = skl_dsp_ipc_get_mailbox_offset; 77 78 /* doorbell */ 79 sof_skl_ops.irq_thread = hda_dsp_ipc4_irq_thread; 80 81 /* ipc */ 82 sof_skl_ops.send_msg = hda_dsp_ipc4_send_msg; 83 84 /* set DAI driver ops */ 85 hda_set_dai_drv_ops(sdev, &sof_skl_ops); 86 87 /* debug */ 88 sof_skl_ops.debug_map = skl_dsp_debugfs; 89 sof_skl_ops.debug_map_count = ARRAY_SIZE(skl_dsp_debugfs); 90 sof_skl_ops.ipc_dump = hda_ipc4_dump; 91 92 /* firmware run */ 93 sof_skl_ops.run = hda_dsp_cl_boot_firmware_skl; 94 95 /* pre/post fw run */ 96 sof_skl_ops.post_fw_run = hda_dsp_post_fw_run; 97 98 return 0; 99 }; 100 EXPORT_SYMBOL_NS(sof_skl_ops_init, SND_SOC_SOF_INTEL_HDA_COMMON); 101 102 const struct sof_intel_dsp_desc skl_chip_info = { 103 .cores_num = 2, 104 .init_core_mask = 1, 105 .host_managed_cores_mask = GENMASK(1, 0), 106 .ipc_req = HDA_DSP_REG_HIPCI, 107 .ipc_req_mask = HDA_DSP_REG_HIPCI_BUSY, 108 .ipc_ack = HDA_DSP_REG_HIPCIE, 109 .ipc_ack_mask = HDA_DSP_REG_HIPCIE_DONE, 110 .ipc_ctl = HDA_DSP_REG_HIPCCTL, 111 .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS_SKL, 112 .rom_init_timeout = 300, 113 .check_ipc_irq = hda_dsp_check_ipc_irq, 114 .power_down_dsp = hda_power_down_dsp, 115 .disable_interrupts = hda_dsp_disable_interrupts, 116 .hw_ip_version = SOF_INTEL_CAVS_1_5, 117 }; 118 EXPORT_SYMBOL_NS(skl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); 119