1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 // 3 // Copyright(c) 2022 Intel Corporation. All rights reserved. 4 // 5 // Authors: Ranjani Sridharan <ranjani.sridharan@linux.intel.com> 6 // 7 8 /* 9 * Hardware interface for audio DSP on Meteorlake. 10 */ 11 12 #include <linux/firmware.h> 13 #include <sound/sof/ipc4/header.h> 14 #include <trace/events/sof_intel.h> 15 #include "../ipc4-priv.h" 16 #include "../ops.h" 17 #include "hda.h" 18 #include "hda-ipc.h" 19 #include "../sof-audio.h" 20 #include "mtl.h" 21 22 static const struct snd_sof_debugfs_map mtl_dsp_debugfs[] = { 23 {"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS}, 24 {"pp", HDA_DSP_PP_BAR, 0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS}, 25 {"dsp", HDA_DSP_BAR, 0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS}, 26 }; 27 28 static void mtl_ipc_host_done(struct snd_sof_dev *sdev) 29 { 30 /* 31 * clear busy interrupt to tell dsp controller this interrupt has been accepted, 32 * not trigger it again 33 */ 34 snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDR, 35 MTL_DSP_REG_HFIPCXTDR_BUSY, MTL_DSP_REG_HFIPCXTDR_BUSY); 36 /* 37 * clear busy bit to ack dsp the msg has been processed and send reply msg to dsp 38 */ 39 snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDA, 40 MTL_DSP_REG_HFIPCXTDA_BUSY, 0); 41 } 42 43 static void mtl_ipc_dsp_done(struct snd_sof_dev *sdev) 44 { 45 /* 46 * set DONE bit - tell DSP we have received the reply msg from DSP, and processed it, 47 * don't send more reply to host 48 */ 49 snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDA, 50 MTL_DSP_REG_HFIPCXIDA_DONE, MTL_DSP_REG_HFIPCXIDA_DONE); 51 52 /* unmask Done interrupt */ 53 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXCTL, 54 MTL_DSP_REG_HFIPCXCTL_DONE, MTL_DSP_REG_HFIPCXCTL_DONE); 55 } 56 57 /* Check if an IPC IRQ occurred */ 58 static bool mtl_dsp_check_ipc_irq(struct snd_sof_dev *sdev) 59 { 60 u32 irq_status; 61 u32 hfintipptr; 62 63 /* read Interrupt IP Pointer */ 64 hfintipptr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_HFINTIPPTR) & MTL_HFINTIPPTR_PTR_MASK; 65 irq_status = snd_sof_dsp_read(sdev, HDA_DSP_BAR, hfintipptr + MTL_DSP_IRQSTS); 66 67 trace_sof_intel_hda_irq_ipc_check(sdev, irq_status); 68 69 if (irq_status != U32_MAX && (irq_status & MTL_DSP_IRQSTS_IPC)) 70 return true; 71 72 return false; 73 } 74 75 /* Check if an SDW IRQ occurred */ 76 static bool mtl_dsp_check_sdw_irq(struct snd_sof_dev *sdev) 77 { 78 u32 irq_status; 79 u32 hfintipptr; 80 81 /* read Interrupt IP Pointer */ 82 hfintipptr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_HFINTIPPTR) & MTL_HFINTIPPTR_PTR_MASK; 83 irq_status = snd_sof_dsp_read(sdev, HDA_DSP_BAR, hfintipptr + MTL_DSP_IRQSTS); 84 85 if (irq_status != U32_MAX && (irq_status & MTL_DSP_IRQSTS_SDW)) 86 return true; 87 88 return false; 89 } 90 91 static int mtl_ipc_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg) 92 { 93 struct sof_ipc4_msg *msg_data = msg->msg_data; 94 95 /* send the message via mailbox */ 96 if (msg_data->data_size) 97 sof_mailbox_write(sdev, sdev->host_box.offset, msg_data->data_ptr, 98 msg_data->data_size); 99 100 snd_sof_dsp_write(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDDY, 101 msg_data->extension); 102 snd_sof_dsp_write(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDR, 103 msg_data->primary | MTL_DSP_REG_HFIPCXIDR_BUSY); 104 105 return 0; 106 } 107 108 static void mtl_enable_ipc_interrupts(struct snd_sof_dev *sdev) 109 { 110 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 111 const struct sof_intel_dsp_desc *chip = hda->desc; 112 113 /* enable IPC DONE and BUSY interrupts */ 114 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, chip->ipc_ctl, 115 MTL_DSP_REG_HFIPCXCTL_BUSY | MTL_DSP_REG_HFIPCXCTL_DONE, 116 MTL_DSP_REG_HFIPCXCTL_BUSY | MTL_DSP_REG_HFIPCXCTL_DONE); 117 } 118 119 static void mtl_disable_ipc_interrupts(struct snd_sof_dev *sdev) 120 { 121 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 122 const struct sof_intel_dsp_desc *chip = hda->desc; 123 124 /* disable IPC DONE and BUSY interrupts */ 125 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, chip->ipc_ctl, 126 MTL_DSP_REG_HFIPCXCTL_BUSY | MTL_DSP_REG_HFIPCXCTL_DONE, 0); 127 } 128 129 static int mtl_enable_interrupts(struct snd_sof_dev *sdev) 130 { 131 u32 hfintipptr; 132 u32 irqinten; 133 u32 host_ipc; 134 u32 hipcie; 135 int ret; 136 137 /* read Interrupt IP Pointer */ 138 hfintipptr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_HFINTIPPTR) & MTL_HFINTIPPTR_PTR_MASK; 139 140 /* Enable Host IPC and SOUNDWIRE */ 141 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, hfintipptr, 142 MTL_IRQ_INTEN_L_HOST_IPC_MASK | MTL_IRQ_INTEN_L_SOUNDWIRE_MASK, 143 MTL_IRQ_INTEN_L_HOST_IPC_MASK | MTL_IRQ_INTEN_L_SOUNDWIRE_MASK); 144 145 /* check if operation was successful */ 146 host_ipc = MTL_IRQ_INTEN_L_HOST_IPC_MASK | MTL_IRQ_INTEN_L_SOUNDWIRE_MASK; 147 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, hfintipptr, irqinten, 148 (irqinten & host_ipc) == host_ipc, 149 HDA_DSP_REG_POLL_INTERVAL_US, HDA_DSP_RESET_TIMEOUT_US); 150 if (ret < 0) { 151 dev_err(sdev->dev, "failed to enable Host IPC and/or SOUNDWIRE\n"); 152 return ret; 153 } 154 155 /* Set Host IPC interrupt enable */ 156 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfHIPCIE, 157 MTL_DSP_REG_HfHIPCIE_IE_MASK, MTL_DSP_REG_HfHIPCIE_IE_MASK); 158 159 /* check if operation was successful */ 160 host_ipc = MTL_DSP_REG_HfHIPCIE_IE_MASK; 161 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfHIPCIE, hipcie, 162 (hipcie & host_ipc) == host_ipc, 163 HDA_DSP_REG_POLL_INTERVAL_US, HDA_DSP_RESET_TIMEOUT_US); 164 if (ret < 0) { 165 dev_err(sdev->dev, "failed to set Host IPC interrupt enable\n"); 166 return ret; 167 } 168 169 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfSNDWIE, 170 MTL_DSP_REG_HfSNDWIE_IE_MASK, MTL_DSP_REG_HfSNDWIE_IE_MASK); 171 host_ipc = MTL_DSP_REG_HfSNDWIE_IE_MASK; 172 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfSNDWIE, hipcie, 173 (hipcie & host_ipc) == host_ipc, 174 HDA_DSP_REG_POLL_INTERVAL_US, HDA_DSP_RESET_TIMEOUT_US); 175 if (ret < 0) 176 dev_err(sdev->dev, "failed to set SoundWire IPC interrupt enable\n"); 177 178 return ret; 179 } 180 181 static int mtl_disable_interrupts(struct snd_sof_dev *sdev) 182 { 183 u32 hfintipptr; 184 u32 irqinten; 185 u32 host_ipc; 186 u32 hipcie; 187 int ret1; 188 int ret; 189 190 /* read Interrupt IP Pointer */ 191 hfintipptr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_HFINTIPPTR) & MTL_HFINTIPPTR_PTR_MASK; 192 193 /* Disable Host IPC and SOUNDWIRE */ 194 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, hfintipptr, 195 MTL_IRQ_INTEN_L_HOST_IPC_MASK | MTL_IRQ_INTEN_L_SOUNDWIRE_MASK, 0); 196 197 /* check if operation was successful */ 198 host_ipc = MTL_IRQ_INTEN_L_HOST_IPC_MASK | MTL_IRQ_INTEN_L_SOUNDWIRE_MASK; 199 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, hfintipptr, irqinten, 200 (irqinten & host_ipc) == 0, 201 HDA_DSP_REG_POLL_INTERVAL_US, HDA_DSP_RESET_TIMEOUT_US); 202 /* Continue to disable other interrupts when error happens */ 203 if (ret < 0) 204 dev_err(sdev->dev, "failed to disable Host IPC and SoundWire\n"); 205 206 /* Set Host IPC interrupt disable */ 207 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfHIPCIE, 208 MTL_DSP_REG_HfHIPCIE_IE_MASK, 0); 209 210 /* check if operation was successful */ 211 host_ipc = MTL_DSP_REG_HfHIPCIE_IE_MASK; 212 ret1 = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfHIPCIE, hipcie, 213 (hipcie & host_ipc) == 0, 214 HDA_DSP_REG_POLL_INTERVAL_US, 215 HDA_DSP_RESET_TIMEOUT_US); 216 if (ret1 < 0) { 217 dev_err(sdev->dev, "failed to set Host IPC interrupt disable\n"); 218 if (!ret) 219 ret = ret1; 220 } 221 222 /* Set SoundWire IPC interrupt disable */ 223 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfSNDWIE, 224 MTL_DSP_REG_HfSNDWIE_IE_MASK, 0); 225 host_ipc = MTL_DSP_REG_HfSNDWIE_IE_MASK; 226 ret1 = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfSNDWIE, hipcie, 227 (hipcie & host_ipc) == 0, 228 HDA_DSP_REG_POLL_INTERVAL_US, 229 HDA_DSP_RESET_TIMEOUT_US); 230 if (ret1 < 0) { 231 dev_err(sdev->dev, "failed to set SoundWire IPC interrupt disable\n"); 232 if (!ret) 233 ret = ret1; 234 } 235 236 return ret; 237 } 238 239 /* pre fw run operations */ 240 static int mtl_dsp_pre_fw_run(struct snd_sof_dev *sdev) 241 { 242 u32 dsphfpwrsts; 243 u32 dsphfdsscs; 244 u32 cpa; 245 u32 pgs; 246 int ret; 247 248 /* Set the DSP subsystem power on */ 249 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_HFDSSCS, 250 MTL_HFDSSCS_SPA_MASK, MTL_HFDSSCS_SPA_MASK); 251 252 /* Wait for unstable CPA read (1 then 0 then 1) just after setting SPA bit */ 253 usleep_range(1000, 1010); 254 255 /* poll with timeout to check if operation successful */ 256 cpa = MTL_HFDSSCS_CPA_MASK; 257 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_HFDSSCS, dsphfdsscs, 258 (dsphfdsscs & cpa) == cpa, HDA_DSP_REG_POLL_INTERVAL_US, 259 HDA_DSP_RESET_TIMEOUT_US); 260 if (ret < 0) { 261 dev_err(sdev->dev, "failed to enable DSP subsystem\n"); 262 return ret; 263 } 264 265 /* Power up gated-DSP-0 domain in order to access the DSP shim register block. */ 266 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_HFPWRCTL, 267 MTL_HFPWRCTL_WPDSPHPXPG, MTL_HFPWRCTL_WPDSPHPXPG); 268 269 usleep_range(1000, 1010); 270 271 /* poll with timeout to check if operation successful */ 272 pgs = MTL_HFPWRSTS_DSPHPXPGS_MASK; 273 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_HFPWRSTS, dsphfpwrsts, 274 (dsphfpwrsts & pgs) == pgs, 275 HDA_DSP_REG_POLL_INTERVAL_US, 276 HDA_DSP_RESET_TIMEOUT_US); 277 if (ret < 0) 278 dev_err(sdev->dev, "failed to power up gated DSP domain\n"); 279 280 /* make sure SoundWire is not power-gated */ 281 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, MTL_HFPWRCTL, 282 MTL_HfPWRCTL_WPIOXPG(1), MTL_HfPWRCTL_WPIOXPG(1)); 283 return ret; 284 } 285 286 static int mtl_dsp_post_fw_run(struct snd_sof_dev *sdev) 287 { 288 int ret; 289 290 if (sdev->first_boot) { 291 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata; 292 293 ret = hda_sdw_startup(sdev); 294 if (ret < 0) { 295 dev_err(sdev->dev, "could not startup SoundWire links\n"); 296 return ret; 297 } 298 299 /* Check if IMR boot is usable */ 300 if (!sof_debug_check_flag(SOF_DBG_IGNORE_D3_PERSISTENT)) 301 hdev->imrboot_supported = true; 302 } 303 304 hda_sdw_int_enable(sdev, true); 305 return 0; 306 } 307 308 static void mtl_dsp_dump(struct snd_sof_dev *sdev, u32 flags) 309 { 310 char *level = (flags & SOF_DBG_DUMP_OPTIONAL) ? KERN_DEBUG : KERN_ERR; 311 u32 romdbgsts; 312 u32 romdbgerr; 313 u32 fwsts; 314 u32 fwlec; 315 316 fwsts = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_ROM_STS); 317 fwlec = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_ROM_ERROR); 318 romdbgsts = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFFLGPXQWY); 319 romdbgerr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFFLGPXQWY_ERROR); 320 321 dev_err(sdev->dev, "ROM status: %#x, ROM error: %#x\n", fwsts, fwlec); 322 dev_err(sdev->dev, "ROM debug status: %#x, ROM debug error: %#x\n", romdbgsts, 323 romdbgerr); 324 romdbgsts = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFFLGPXQWY + 0x8 * 3); 325 dev_printk(level, sdev->dev, "ROM feature bit%s enabled\n", 326 romdbgsts & BIT(24) ? "" : " not"); 327 } 328 329 static bool mtl_dsp_primary_core_is_enabled(struct snd_sof_dev *sdev) 330 { 331 int val; 332 333 val = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP2CXCTL_PRIMARY_CORE); 334 if (val != U32_MAX && val & MTL_DSP2CXCTL_PRIMARY_CORE_CPA_MASK) 335 return true; 336 337 return false; 338 } 339 340 static int mtl_dsp_core_power_up(struct snd_sof_dev *sdev, int core) 341 { 342 unsigned int cpa; 343 u32 dspcxctl; 344 int ret; 345 346 /* Only the primary core can be powered up by the host */ 347 if (core != SOF_DSP_PRIMARY_CORE || mtl_dsp_primary_core_is_enabled(sdev)) 348 return 0; 349 350 /* Program the owner of the IP & shim registers (10: Host CPU) */ 351 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP2CXCTL_PRIMARY_CORE, 352 MTL_DSP2CXCTL_PRIMARY_CORE_OSEL, 353 0x2 << MTL_DSP2CXCTL_PRIMARY_CORE_OSEL_SHIFT); 354 355 /* enable SPA bit */ 356 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP2CXCTL_PRIMARY_CORE, 357 MTL_DSP2CXCTL_PRIMARY_CORE_SPA_MASK, 358 MTL_DSP2CXCTL_PRIMARY_CORE_SPA_MASK); 359 360 /* Wait for unstable CPA read (1 then 0 then 1) just after setting SPA bit */ 361 usleep_range(1000, 1010); 362 363 /* poll with timeout to check if operation successful */ 364 cpa = MTL_DSP2CXCTL_PRIMARY_CORE_CPA_MASK; 365 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_DSP2CXCTL_PRIMARY_CORE, dspcxctl, 366 (dspcxctl & cpa) == cpa, HDA_DSP_REG_POLL_INTERVAL_US, 367 HDA_DSP_RESET_TIMEOUT_US); 368 if (ret < 0) 369 dev_err(sdev->dev, "%s: timeout on MTL_DSP2CXCTL_PRIMARY_CORE read\n", 370 __func__); 371 372 return ret; 373 } 374 375 static int mtl_dsp_core_power_down(struct snd_sof_dev *sdev, int core) 376 { 377 u32 dspcxctl; 378 int ret; 379 380 /* Only the primary core can be powered down by the host */ 381 if (core != SOF_DSP_PRIMARY_CORE || !mtl_dsp_primary_core_is_enabled(sdev)) 382 return 0; 383 384 /* disable SPA bit */ 385 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP2CXCTL_PRIMARY_CORE, 386 MTL_DSP2CXCTL_PRIMARY_CORE_SPA_MASK, 0); 387 388 /* Wait for unstable CPA read (1 then 0 then 1) just after setting SPA bit */ 389 usleep_range(1000, 1010); 390 391 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_DSP2CXCTL_PRIMARY_CORE, dspcxctl, 392 !(dspcxctl & MTL_DSP2CXCTL_PRIMARY_CORE_CPA_MASK), 393 HDA_DSP_REG_POLL_INTERVAL_US, 394 HDA_DSP_PD_TIMEOUT * USEC_PER_MSEC); 395 if (ret < 0) 396 dev_err(sdev->dev, "failed to power down primary core\n"); 397 398 return ret; 399 } 400 401 static int mtl_power_down_dsp(struct snd_sof_dev *sdev) 402 { 403 u32 dsphfdsscs, cpa; 404 int ret; 405 406 /* first power down core */ 407 ret = mtl_dsp_core_power_down(sdev, SOF_DSP_PRIMARY_CORE); 408 if (ret) { 409 dev_err(sdev->dev, "mtl dsp power down error, %d\n", ret); 410 return ret; 411 } 412 413 /* Set the DSP subsystem power down */ 414 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_HFDSSCS, 415 MTL_HFDSSCS_SPA_MASK, 0); 416 417 /* Wait for unstable CPA read (1 then 0 then 1) just after setting SPA bit */ 418 usleep_range(1000, 1010); 419 420 /* poll with timeout to check if operation successful */ 421 cpa = MTL_HFDSSCS_CPA_MASK; 422 dsphfdsscs = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_HFDSSCS); 423 return snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_HFDSSCS, dsphfdsscs, 424 (dsphfdsscs & cpa) == 0, HDA_DSP_REG_POLL_INTERVAL_US, 425 HDA_DSP_RESET_TIMEOUT_US); 426 } 427 428 static int mtl_dsp_cl_init(struct snd_sof_dev *sdev, int stream_tag, bool imr_boot) 429 { 430 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 431 const struct sof_intel_dsp_desc *chip = hda->desc; 432 unsigned int status; 433 u32 ipc_hdr; 434 int ret; 435 436 /* step 1: purge FW request */ 437 ipc_hdr = chip->ipc_req_mask | HDA_DSP_ROM_IPC_CONTROL; 438 if (!imr_boot) 439 ipc_hdr |= HDA_DSP_ROM_IPC_PURGE_FW | ((stream_tag - 1) << 9); 440 441 snd_sof_dsp_write(sdev, HDA_DSP_BAR, chip->ipc_req, ipc_hdr); 442 443 /* step 2: power up primary core */ 444 ret = mtl_dsp_core_power_up(sdev, SOF_DSP_PRIMARY_CORE); 445 if (ret < 0) { 446 if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS) 447 dev_err(sdev->dev, "dsp core 0/1 power up failed\n"); 448 goto err; 449 } 450 451 dev_dbg(sdev->dev, "Primary core power up successful\n"); 452 453 /* step 3: wait for IPC DONE bit from ROM */ 454 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, chip->ipc_ack, status, 455 ((status & chip->ipc_ack_mask) == chip->ipc_ack_mask), 456 HDA_DSP_REG_POLL_INTERVAL_US, MTL_DSP_PURGE_TIMEOUT_US); 457 if (ret < 0) { 458 if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS) 459 dev_err(sdev->dev, "timeout waiting for purge IPC done\n"); 460 goto err; 461 } 462 463 /* set DONE bit to clear the reply IPC message */ 464 snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR, chip->ipc_ack, chip->ipc_ack_mask, 465 chip->ipc_ack_mask); 466 467 /* step 4: enable interrupts */ 468 ret = mtl_enable_interrupts(sdev); 469 if (ret < 0) { 470 if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS) 471 dev_err(sdev->dev, "%s: failed to enable interrupts\n", __func__); 472 goto err; 473 } 474 475 mtl_enable_ipc_interrupts(sdev); 476 477 /* 478 * ACE workaround: don't wait for ROM INIT. 479 * The platform cannot catch ROM_INIT_DONE because of a very short 480 * timing window. Follow the recommendations and skip this part. 481 */ 482 483 return 0; 484 485 err: 486 snd_sof_dsp_dbg_dump(sdev, "MTL DSP init fail", 0); 487 mtl_dsp_core_power_down(sdev, SOF_DSP_PRIMARY_CORE); 488 return ret; 489 } 490 491 static irqreturn_t mtl_ipc_irq_thread(int irq, void *context) 492 { 493 struct sof_ipc4_msg notification_data = {{ 0 }}; 494 struct snd_sof_dev *sdev = context; 495 bool ipc_irq = false; 496 u32 hipcida; 497 u32 hipctdr; 498 499 hipcida = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDA); 500 501 /* reply message from DSP */ 502 if (hipcida & MTL_DSP_REG_HFIPCXIDA_DONE) { 503 /* DSP received the message */ 504 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXCTL, 505 MTL_DSP_REG_HFIPCXCTL_DONE, 0); 506 507 mtl_ipc_dsp_done(sdev); 508 509 ipc_irq = true; 510 } 511 512 hipctdr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDR); 513 if (hipctdr & MTL_DSP_REG_HFIPCXTDR_BUSY) { 514 /* Message from DSP (reply or notification) */ 515 u32 extension = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDDY); 516 u32 primary = hipctdr & MTL_DSP_REG_HFIPCXTDR_MSG_MASK; 517 518 /* 519 * ACE fw sends a new fw ipc message to host to 520 * notify the status of the last host ipc message 521 */ 522 if (primary & SOF_IPC4_MSG_DIR_MASK) { 523 /* Reply received */ 524 if (likely(sdev->fw_state == SOF_FW_BOOT_COMPLETE)) { 525 struct sof_ipc4_msg *data = sdev->ipc->msg.reply_data; 526 527 data->primary = primary; 528 data->extension = extension; 529 530 spin_lock_irq(&sdev->ipc_lock); 531 532 snd_sof_ipc_get_reply(sdev); 533 snd_sof_ipc_reply(sdev, data->primary); 534 535 spin_unlock_irq(&sdev->ipc_lock); 536 } else { 537 dev_dbg_ratelimited(sdev->dev, 538 "IPC reply before FW_READY: %#x|%#x\n", 539 primary, extension); 540 } 541 } else { 542 /* Notification received */ 543 notification_data.primary = primary; 544 notification_data.extension = extension; 545 546 sdev->ipc->msg.rx_data = ¬ification_data; 547 snd_sof_ipc_msgs_rx(sdev); 548 sdev->ipc->msg.rx_data = NULL; 549 } 550 551 mtl_ipc_host_done(sdev); 552 553 ipc_irq = true; 554 } 555 556 if (!ipc_irq) { 557 /* This interrupt is not shared so no need to return IRQ_NONE. */ 558 dev_dbg_ratelimited(sdev->dev, "nothing to do in IPC IRQ thread\n"); 559 } 560 561 return IRQ_HANDLED; 562 } 563 564 static int mtl_dsp_ipc_get_mailbox_offset(struct snd_sof_dev *sdev) 565 { 566 return MTL_DSP_MBOX_UPLINK_OFFSET; 567 } 568 569 static int mtl_dsp_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id) 570 { 571 return MTL_SRAM_WINDOW_OFFSET(id); 572 } 573 574 static void mtl_ipc_dump(struct snd_sof_dev *sdev) 575 { 576 u32 hipcidr, hipcidd, hipcida, hipctdr, hipctdd, hipctda, hipcctl; 577 578 hipcidr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDR); 579 hipcidd = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDDY); 580 hipcida = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDA); 581 hipctdr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDR); 582 hipctdd = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDDY); 583 hipctda = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDA); 584 hipcctl = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXCTL); 585 586 dev_err(sdev->dev, 587 "Host IPC initiator: %#x|%#x|%#x, target: %#x|%#x|%#x, ctl: %#x\n", 588 hipcidr, hipcidd, hipcida, hipctdr, hipctdd, hipctda, hipcctl); 589 } 590 591 static int mtl_dsp_disable_interrupts(struct snd_sof_dev *sdev) 592 { 593 mtl_disable_ipc_interrupts(sdev); 594 return mtl_disable_interrupts(sdev); 595 } 596 597 /* Meteorlake ops */ 598 struct snd_sof_dsp_ops sof_mtl_ops; 599 EXPORT_SYMBOL_NS(sof_mtl_ops, SND_SOC_SOF_INTEL_HDA_COMMON); 600 601 int sof_mtl_ops_init(struct snd_sof_dev *sdev) 602 { 603 struct sof_ipc4_fw_data *ipc4_data; 604 605 /* common defaults */ 606 memcpy(&sof_mtl_ops, &sof_hda_common_ops, sizeof(struct snd_sof_dsp_ops)); 607 608 /* shutdown */ 609 sof_mtl_ops.shutdown = hda_dsp_shutdown; 610 611 /* doorbell */ 612 sof_mtl_ops.irq_thread = mtl_ipc_irq_thread; 613 614 /* ipc */ 615 sof_mtl_ops.send_msg = mtl_ipc_send_msg; 616 sof_mtl_ops.get_mailbox_offset = mtl_dsp_ipc_get_mailbox_offset; 617 sof_mtl_ops.get_window_offset = mtl_dsp_ipc_get_window_offset; 618 619 /* debug */ 620 sof_mtl_ops.debug_map = mtl_dsp_debugfs; 621 sof_mtl_ops.debug_map_count = ARRAY_SIZE(mtl_dsp_debugfs); 622 sof_mtl_ops.dbg_dump = mtl_dsp_dump; 623 sof_mtl_ops.ipc_dump = mtl_ipc_dump; 624 625 /* pre/post fw run */ 626 sof_mtl_ops.pre_fw_run = mtl_dsp_pre_fw_run; 627 sof_mtl_ops.post_fw_run = mtl_dsp_post_fw_run; 628 629 /* parse platform specific extended manifest */ 630 sof_mtl_ops.parse_platform_ext_manifest = NULL; 631 632 /* dsp core get/put */ 633 /* TODO: add core_get and core_put */ 634 635 sdev->private = devm_kzalloc(sdev->dev, sizeof(struct sof_ipc4_fw_data), GFP_KERNEL); 636 if (!sdev->private) 637 return -ENOMEM; 638 639 ipc4_data = sdev->private; 640 ipc4_data->manifest_fw_hdr_offset = SOF_MAN4_FW_HDR_OFFSET; 641 642 ipc4_data->mtrace_type = SOF_IPC4_MTRACE_INTEL_CAVS_2; 643 644 /* set DAI ops */ 645 hda_set_dai_drv_ops(sdev, &sof_mtl_ops); 646 647 return 0; 648 }; 649 EXPORT_SYMBOL_NS(sof_mtl_ops_init, SND_SOC_SOF_INTEL_HDA_COMMON); 650 651 const struct sof_intel_dsp_desc mtl_chip_info = { 652 .cores_num = 3, 653 .init_core_mask = BIT(0), 654 .host_managed_cores_mask = BIT(0), 655 .ipc_req = MTL_DSP_REG_HFIPCXIDR, 656 .ipc_req_mask = MTL_DSP_REG_HFIPCXIDR_BUSY, 657 .ipc_ack = MTL_DSP_REG_HFIPCXIDA, 658 .ipc_ack_mask = MTL_DSP_REG_HFIPCXIDA_DONE, 659 .ipc_ctl = MTL_DSP_REG_HFIPCXCTL, 660 .rom_status_reg = MTL_DSP_ROM_STS, 661 .rom_init_timeout = 300, 662 .ssp_count = MTL_SSP_COUNT, 663 .ssp_base_offset = CNL_SSP_BASE_OFFSET, 664 .sdw_shim_base = SDW_SHIM_BASE_ACE, 665 .sdw_alh_base = SDW_ALH_BASE_ACE, 666 .check_sdw_irq = mtl_dsp_check_sdw_irq, 667 .check_ipc_irq = mtl_dsp_check_ipc_irq, 668 .cl_init = mtl_dsp_cl_init, 669 .power_down_dsp = mtl_power_down_dsp, 670 .disable_interrupts = mtl_dsp_disable_interrupts, 671 .hw_ip_version = SOF_INTEL_ACE_1_0, 672 }; 673 EXPORT_SYMBOL_NS(mtl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); 674