1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 // 3 // Copyright(c) 2022 Intel Corporation. All rights reserved. 4 // 5 // Authors: Ranjani Sridharan <ranjani.sridharan@linux.intel.com> 6 // 7 8 /* 9 * Hardware interface for audio DSP on Meteorlake. 10 */ 11 12 #include <linux/firmware.h> 13 #include <sound/sof/ipc4/header.h> 14 #include "../ipc4-priv.h" 15 #include "../ops.h" 16 #include "hda.h" 17 #include "hda-ipc.h" 18 #include "../sof-audio.h" 19 #include "mtl.h" 20 21 static const struct snd_sof_debugfs_map mtl_dsp_debugfs[] = { 22 {"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS}, 23 {"pp", HDA_DSP_PP_BAR, 0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS}, 24 {"dsp", HDA_DSP_BAR, 0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS}, 25 }; 26 27 static void mtl_ipc_host_done(struct snd_sof_dev *sdev) 28 { 29 /* 30 * clear busy interrupt to tell dsp controller this interrupt has been accepted, 31 * not trigger it again 32 */ 33 snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDR, 34 MTL_DSP_REG_HFIPCXTDR_BUSY, MTL_DSP_REG_HFIPCXTDR_BUSY); 35 /* 36 * clear busy bit to ack dsp the msg has been processed and send reply msg to dsp 37 */ 38 snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDA, 39 MTL_DSP_REG_HFIPCXTDA_BUSY, 0); 40 } 41 42 static void mtl_ipc_dsp_done(struct snd_sof_dev *sdev) 43 { 44 /* 45 * set DONE bit - tell DSP we have received the reply msg from DSP, and processed it, 46 * don't send more reply to host 47 */ 48 snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDA, 49 MTL_DSP_REG_HFIPCXIDA_DONE, MTL_DSP_REG_HFIPCXIDA_DONE); 50 51 /* unmask Done interrupt */ 52 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXCTL, 53 MTL_DSP_REG_HFIPCXCTL_DONE, MTL_DSP_REG_HFIPCXCTL_DONE); 54 } 55 56 /* Check if an IPC IRQ occurred */ 57 static bool mtl_dsp_check_ipc_irq(struct snd_sof_dev *sdev) 58 { 59 u32 irq_status; 60 u32 hfintipptr; 61 62 /* read Interrupt IP Pointer */ 63 hfintipptr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_HFINTIPPTR) & MTL_HFINTIPPTR_PTR_MASK; 64 irq_status = snd_sof_dsp_read(sdev, HDA_DSP_BAR, hfintipptr + MTL_DSP_IRQSTS); 65 66 dev_vdbg(sdev->dev, "irq handler: irq_status:0x%x\n", irq_status); 67 68 if (irq_status != U32_MAX && (irq_status & MTL_DSP_IRQSTS_IPC)) 69 return true; 70 71 return false; 72 } 73 74 /* Check if an SDW IRQ occurred */ 75 static bool mtl_dsp_check_sdw_irq(struct snd_sof_dev *sdev) 76 { 77 u32 irq_status; 78 u32 hfintipptr; 79 80 /* read Interrupt IP Pointer */ 81 hfintipptr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_HFINTIPPTR) & MTL_HFINTIPPTR_PTR_MASK; 82 irq_status = snd_sof_dsp_read(sdev, HDA_DSP_BAR, hfintipptr + MTL_DSP_IRQSTS); 83 84 if (irq_status != U32_MAX && (irq_status & MTL_DSP_IRQSTS_SDW)) 85 return true; 86 87 return false; 88 } 89 90 static int mtl_ipc_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg) 91 { 92 struct sof_ipc4_msg *msg_data = msg->msg_data; 93 94 /* send the message via mailbox */ 95 if (msg_data->data_size) 96 sof_mailbox_write(sdev, sdev->host_box.offset, msg_data->data_ptr, 97 msg_data->data_size); 98 99 snd_sof_dsp_write(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDDY, 100 msg_data->extension); 101 snd_sof_dsp_write(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDR, 102 msg_data->primary | MTL_DSP_REG_HFIPCXIDR_BUSY); 103 104 return 0; 105 } 106 107 static void mtl_enable_ipc_interrupts(struct snd_sof_dev *sdev) 108 { 109 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 110 const struct sof_intel_dsp_desc *chip = hda->desc; 111 112 /* enable IPC DONE and BUSY interrupts */ 113 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, chip->ipc_ctl, 114 MTL_DSP_REG_HFIPCXCTL_BUSY | MTL_DSP_REG_HFIPCXCTL_DONE, 115 MTL_DSP_REG_HFIPCXCTL_BUSY | MTL_DSP_REG_HFIPCXCTL_DONE); 116 } 117 118 static void mtl_disable_ipc_interrupts(struct snd_sof_dev *sdev) 119 { 120 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 121 const struct sof_intel_dsp_desc *chip = hda->desc; 122 123 /* disable IPC DONE and BUSY interrupts */ 124 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, chip->ipc_ctl, 125 MTL_DSP_REG_HFIPCXCTL_BUSY | MTL_DSP_REG_HFIPCXCTL_DONE, 0); 126 } 127 128 static int mtl_enable_interrupts(struct snd_sof_dev *sdev) 129 { 130 u32 hfintipptr; 131 u32 irqinten; 132 u32 host_ipc; 133 u32 hipcie; 134 int ret; 135 136 /* read Interrupt IP Pointer */ 137 hfintipptr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_HFINTIPPTR) & MTL_HFINTIPPTR_PTR_MASK; 138 139 /* Enable Host IPC and SOUNDWIRE */ 140 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, hfintipptr, 141 MTL_IRQ_INTEN_L_HOST_IPC_MASK | MTL_IRQ_INTEN_L_SOUNDWIRE_MASK, 142 MTL_IRQ_INTEN_L_HOST_IPC_MASK | MTL_IRQ_INTEN_L_SOUNDWIRE_MASK); 143 144 /* check if operation was successful */ 145 host_ipc = MTL_IRQ_INTEN_L_HOST_IPC_MASK | MTL_IRQ_INTEN_L_SOUNDWIRE_MASK; 146 irqinten = snd_sof_dsp_read(sdev, HDA_DSP_BAR, hfintipptr); 147 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, hfintipptr, irqinten, 148 (irqinten & host_ipc) == host_ipc, 149 HDA_DSP_REG_POLL_INTERVAL_US, HDA_DSP_RESET_TIMEOUT_US); 150 if (ret < 0) { 151 dev_err(sdev->dev, "failed to enable Host IPC and/or SOUNDWIRE\n"); 152 return ret; 153 } 154 155 /* Set Host IPC interrupt enable */ 156 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfHIPCIE, 157 MTL_DSP_REG_HfHIPCIE_IE_MASK, MTL_DSP_REG_HfHIPCIE_IE_MASK); 158 159 /* check if operation was successful */ 160 host_ipc = MTL_DSP_REG_HfHIPCIE_IE_MASK; 161 hipcie = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfHIPCIE); 162 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfHIPCIE, hipcie, 163 (hipcie & host_ipc) == host_ipc, 164 HDA_DSP_REG_POLL_INTERVAL_US, HDA_DSP_RESET_TIMEOUT_US); 165 if (ret < 0) { 166 dev_err(sdev->dev, "failed to set Host IPC interrupt enable\n"); 167 return ret; 168 } 169 170 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfSNDWIE, 171 MTL_DSP_REG_HfSNDWIE_IE_MASK, MTL_DSP_REG_HfSNDWIE_IE_MASK); 172 host_ipc = MTL_DSP_REG_HfSNDWIE_IE_MASK; 173 hipcie = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfSNDWIE); 174 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfSNDWIE, hipcie, 175 (hipcie & host_ipc) == host_ipc, 176 HDA_DSP_REG_POLL_INTERVAL_US, HDA_DSP_RESET_TIMEOUT_US); 177 if (ret < 0) 178 dev_err(sdev->dev, "failed to set SoundWire IPC interrupt enable\n"); 179 180 return ret; 181 } 182 183 static int mtl_disable_interrupts(struct snd_sof_dev *sdev) 184 { 185 u32 hfintipptr; 186 u32 irqinten; 187 u32 host_ipc; 188 u32 hipcie; 189 int ret1; 190 int ret; 191 192 /* read Interrupt IP Pointer */ 193 hfintipptr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_HFINTIPPTR) & MTL_HFINTIPPTR_PTR_MASK; 194 195 /* Disable Host IPC and SOUNDWIRE */ 196 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, hfintipptr, 197 MTL_IRQ_INTEN_L_HOST_IPC_MASK | MTL_IRQ_INTEN_L_SOUNDWIRE_MASK, 0); 198 199 /* check if operation was successful */ 200 host_ipc = MTL_IRQ_INTEN_L_HOST_IPC_MASK | MTL_IRQ_INTEN_L_SOUNDWIRE_MASK; 201 irqinten = snd_sof_dsp_read(sdev, HDA_DSP_BAR, hfintipptr); 202 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, hfintipptr, irqinten, 203 (irqinten & host_ipc) == 0, 204 HDA_DSP_REG_POLL_INTERVAL_US, HDA_DSP_RESET_TIMEOUT_US); 205 /* Continue to disable other interrupts when error happens */ 206 if (ret < 0) 207 dev_err(sdev->dev, "failed to disable Host IPC and SoundWire\n"); 208 209 /* Set Host IPC interrupt disable */ 210 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfHIPCIE, 211 MTL_DSP_REG_HfHIPCIE_IE_MASK, 0); 212 213 /* check if operation was successful */ 214 host_ipc = MTL_DSP_REG_HfHIPCIE_IE_MASK; 215 hipcie = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfHIPCIE); 216 ret1 = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfHIPCIE, hipcie, 217 (hipcie & host_ipc) == 0, 218 HDA_DSP_REG_POLL_INTERVAL_US, 219 HDA_DSP_RESET_TIMEOUT_US); 220 if (ret1 < 0) { 221 dev_err(sdev->dev, "failed to set Host IPC interrupt disable\n"); 222 if (!ret) 223 ret = ret1; 224 } 225 226 /* Set SoundWire IPC interrupt disable */ 227 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfSNDWIE, 228 MTL_DSP_REG_HfSNDWIE_IE_MASK, 0); 229 host_ipc = MTL_DSP_REG_HfSNDWIE_IE_MASK; 230 hipcie = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfSNDWIE); 231 ret1 = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfSNDWIE, hipcie, 232 (hipcie & host_ipc) == 0, 233 HDA_DSP_REG_POLL_INTERVAL_US, 234 HDA_DSP_RESET_TIMEOUT_US); 235 if (ret1 < 0) { 236 dev_err(sdev->dev, "failed to set SoundWire IPC interrupt disable\n"); 237 if (!ret) 238 ret = ret1; 239 } 240 241 return ret; 242 } 243 244 /* pre fw run operations */ 245 static int mtl_dsp_pre_fw_run(struct snd_sof_dev *sdev) 246 { 247 u32 dsphfpwrsts; 248 u32 dsphfdsscs; 249 u32 cpa; 250 u32 pgs; 251 int ret; 252 253 /* Set the DSP subsystem power on */ 254 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_HFDSSCS, 255 MTL_HFDSSCS_SPA_MASK, MTL_HFDSSCS_SPA_MASK); 256 257 /* Wait for unstable CPA read (1 then 0 then 1) just after setting SPA bit */ 258 usleep_range(1000, 1010); 259 260 /* poll with timeout to check if operation successful */ 261 cpa = MTL_HFDSSCS_CPA_MASK; 262 dsphfdsscs = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_HFDSSCS); 263 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_HFDSSCS, dsphfdsscs, 264 (dsphfdsscs & cpa) == cpa, HDA_DSP_REG_POLL_INTERVAL_US, 265 HDA_DSP_RESET_TIMEOUT_US); 266 if (ret < 0) { 267 dev_err(sdev->dev, "failed to enable DSP subsystem\n"); 268 return ret; 269 } 270 271 /* Power up gated-DSP-0 domain in order to access the DSP shim register block. */ 272 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_HFPWRCTL, 273 MTL_HFPWRCTL_WPDSPHPXPG, MTL_HFPWRCTL_WPDSPHPXPG); 274 275 usleep_range(1000, 1010); 276 277 /* poll with timeout to check if operation successful */ 278 pgs = MTL_HFPWRSTS_DSPHPXPGS_MASK; 279 dsphfpwrsts = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_HFPWRSTS); 280 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_HFPWRSTS, dsphfpwrsts, 281 (dsphfpwrsts & pgs) == pgs, 282 HDA_DSP_REG_POLL_INTERVAL_US, 283 HDA_DSP_RESET_TIMEOUT_US); 284 if (ret < 0) 285 dev_err(sdev->dev, "failed to power up gated DSP domain\n"); 286 287 /* make sure SoundWire is not power-gated */ 288 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, MTL_HFPWRCTL, 289 MTL_HfPWRCTL_WPIOXPG(1), MTL_HfPWRCTL_WPIOXPG(1)); 290 return ret; 291 } 292 293 static int mtl_dsp_post_fw_run(struct snd_sof_dev *sdev) 294 { 295 int ret; 296 297 if (sdev->first_boot) { 298 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata; 299 300 ret = hda_sdw_startup(sdev); 301 if (ret < 0) { 302 dev_err(sdev->dev, "could not startup SoundWire links\n"); 303 return ret; 304 } 305 306 /* Check if IMR boot is usable */ 307 if (!sof_debug_check_flag(SOF_DBG_IGNORE_D3_PERSISTENT)) 308 hdev->imrboot_supported = true; 309 } 310 311 hda_sdw_int_enable(sdev, true); 312 return 0; 313 } 314 315 static void mtl_dsp_dump(struct snd_sof_dev *sdev, u32 flags) 316 { 317 char *level = (flags & SOF_DBG_DUMP_OPTIONAL) ? KERN_DEBUG : KERN_ERR; 318 u32 romdbgsts; 319 u32 romdbgerr; 320 u32 fwsts; 321 u32 fwlec; 322 323 fwsts = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_ROM_STS); 324 fwlec = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_ROM_ERROR); 325 romdbgsts = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFFLGPXQWY); 326 romdbgerr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFFLGPXQWY_ERROR); 327 328 dev_err(sdev->dev, "ROM status: %#x, ROM error: %#x\n", fwsts, fwlec); 329 dev_err(sdev->dev, "ROM debug status: %#x, ROM debug error: %#x\n", romdbgsts, 330 romdbgerr); 331 romdbgsts = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFFLGPXQWY + 0x8 * 3); 332 dev_printk(level, sdev->dev, "ROM feature bit%s enabled\n", 333 romdbgsts & BIT(24) ? "" : " not"); 334 } 335 336 static bool mtl_dsp_primary_core_is_enabled(struct snd_sof_dev *sdev) 337 { 338 int val; 339 340 val = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP2CXCTL_PRIMARY_CORE); 341 if (val != U32_MAX && val & MTL_DSP2CXCTL_PRIMARY_CORE_CPA_MASK) 342 return true; 343 344 return false; 345 } 346 347 static int mtl_dsp_core_power_up(struct snd_sof_dev *sdev, int core) 348 { 349 unsigned int cpa; 350 u32 dspcxctl; 351 int ret; 352 353 /* Only the primary core can be powered up by the host */ 354 if (core != SOF_DSP_PRIMARY_CORE || mtl_dsp_primary_core_is_enabled(sdev)) 355 return 0; 356 357 /* Program the owner of the IP & shim registers (10: Host CPU) */ 358 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP2CXCTL_PRIMARY_CORE, 359 MTL_DSP2CXCTL_PRIMARY_CORE_OSEL, 360 0x2 << MTL_DSP2CXCTL_PRIMARY_CORE_OSEL_SHIFT); 361 362 /* enable SPA bit */ 363 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP2CXCTL_PRIMARY_CORE, 364 MTL_DSP2CXCTL_PRIMARY_CORE_SPA_MASK, 365 MTL_DSP2CXCTL_PRIMARY_CORE_SPA_MASK); 366 367 /* Wait for unstable CPA read (1 then 0 then 1) just after setting SPA bit */ 368 usleep_range(1000, 1010); 369 370 /* poll with timeout to check if operation successful */ 371 cpa = MTL_DSP2CXCTL_PRIMARY_CORE_CPA_MASK; 372 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_DSP2CXCTL_PRIMARY_CORE, dspcxctl, 373 (dspcxctl & cpa) == cpa, HDA_DSP_REG_POLL_INTERVAL_US, 374 HDA_DSP_RESET_TIMEOUT_US); 375 if (ret < 0) 376 dev_err(sdev->dev, "%s: timeout on MTL_DSP2CXCTL_PRIMARY_CORE read\n", 377 __func__); 378 379 return ret; 380 } 381 382 static int mtl_dsp_core_power_down(struct snd_sof_dev *sdev, int core) 383 { 384 u32 dspcxctl; 385 int ret; 386 387 /* Only the primary core can be powered down by the host */ 388 if (core != SOF_DSP_PRIMARY_CORE || !mtl_dsp_primary_core_is_enabled(sdev)) 389 return 0; 390 391 /* disable SPA bit */ 392 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP2CXCTL_PRIMARY_CORE, 393 MTL_DSP2CXCTL_PRIMARY_CORE_SPA_MASK, 0); 394 395 /* Wait for unstable CPA read (1 then 0 then 1) just after setting SPA bit */ 396 usleep_range(1000, 1010); 397 398 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_DSP2CXCTL_PRIMARY_CORE, dspcxctl, 399 !(dspcxctl & MTL_DSP2CXCTL_PRIMARY_CORE_CPA_MASK), 400 HDA_DSP_REG_POLL_INTERVAL_US, 401 HDA_DSP_PD_TIMEOUT * USEC_PER_MSEC); 402 if (ret < 0) 403 dev_err(sdev->dev, "failed to power down primary core\n"); 404 405 return ret; 406 } 407 408 static int mtl_dsp_cl_init(struct snd_sof_dev *sdev, int stream_tag, bool imr_boot) 409 { 410 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 411 const struct sof_intel_dsp_desc *chip = hda->desc; 412 unsigned int status; 413 u32 ipc_hdr; 414 int ret; 415 416 /* step 1: purge FW request */ 417 ipc_hdr = chip->ipc_req_mask | HDA_DSP_ROM_IPC_CONTROL; 418 if (!imr_boot) 419 ipc_hdr |= HDA_DSP_ROM_IPC_PURGE_FW | ((stream_tag - 1) << 9); 420 421 snd_sof_dsp_write(sdev, HDA_DSP_BAR, chip->ipc_req, ipc_hdr); 422 423 /* step 2: power up primary core */ 424 ret = mtl_dsp_core_power_up(sdev, SOF_DSP_PRIMARY_CORE); 425 if (ret < 0) { 426 if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS) 427 dev_err(sdev->dev, "dsp core 0/1 power up failed\n"); 428 goto err; 429 } 430 431 dev_dbg(sdev->dev, "Primary core power up successful\n"); 432 433 /* step 3: wait for IPC DONE bit from ROM */ 434 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, chip->ipc_ack, status, 435 ((status & chip->ipc_ack_mask) == chip->ipc_ack_mask), 436 HDA_DSP_REG_POLL_INTERVAL_US, MTL_DSP_PURGE_TIMEOUT_US); 437 if (ret < 0) { 438 if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS) 439 dev_err(sdev->dev, "timeout waiting for purge IPC done\n"); 440 goto err; 441 } 442 443 /* set DONE bit to clear the reply IPC message */ 444 snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR, chip->ipc_ack, chip->ipc_ack_mask, 445 chip->ipc_ack_mask); 446 447 /* step 4: enable interrupts */ 448 ret = mtl_enable_interrupts(sdev); 449 if (ret < 0) { 450 if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS) 451 dev_err(sdev->dev, "%s: failed to enable interrupts\n", __func__); 452 goto err; 453 } 454 455 mtl_enable_ipc_interrupts(sdev); 456 457 /* 458 * ACE workaround: don't wait for ROM INIT. 459 * The platform cannot catch ROM_INIT_DONE because of a very short 460 * timing window. Follow the recommendations and skip this part. 461 */ 462 463 return 0; 464 465 err: 466 snd_sof_dsp_dbg_dump(sdev, "MTL DSP init fail", 0); 467 mtl_dsp_core_power_down(sdev, SOF_DSP_PRIMARY_CORE); 468 return ret; 469 } 470 471 static irqreturn_t mtl_ipc_irq_thread(int irq, void *context) 472 { 473 struct sof_ipc4_msg notification_data = {{ 0 }}; 474 struct snd_sof_dev *sdev = context; 475 bool ipc_irq = false; 476 u32 hipcida; 477 u32 hipctdr; 478 479 hipcida = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDA); 480 481 /* reply message from DSP */ 482 if (hipcida & MTL_DSP_REG_HFIPCXIDA_DONE) { 483 /* DSP received the message */ 484 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXCTL, 485 MTL_DSP_REG_HFIPCXCTL_DONE, 0); 486 487 mtl_ipc_dsp_done(sdev); 488 489 ipc_irq = true; 490 } 491 492 hipctdr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDR); 493 if (hipctdr & MTL_DSP_REG_HFIPCXTDR_BUSY) { 494 /* Message from DSP (reply or notification) */ 495 u32 extension = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDDY); 496 u32 primary = hipctdr & MTL_DSP_REG_HFIPCXTDR_MSG_MASK; 497 498 /* 499 * ACE fw sends a new fw ipc message to host to 500 * notify the status of the last host ipc message 501 */ 502 if (primary & SOF_IPC4_MSG_DIR_MASK) { 503 /* Reply received */ 504 if (likely(sdev->fw_state == SOF_FW_BOOT_COMPLETE)) { 505 struct sof_ipc4_msg *data = sdev->ipc->msg.reply_data; 506 507 data->primary = primary; 508 data->extension = extension; 509 510 spin_lock_irq(&sdev->ipc_lock); 511 512 snd_sof_ipc_get_reply(sdev); 513 snd_sof_ipc_reply(sdev, data->primary); 514 515 spin_unlock_irq(&sdev->ipc_lock); 516 } else { 517 dev_dbg_ratelimited(sdev->dev, 518 "IPC reply before FW_READY: %#x|%#x\n", 519 primary, extension); 520 } 521 } else { 522 /* Notification received */ 523 notification_data.primary = primary; 524 notification_data.extension = extension; 525 526 sdev->ipc->msg.rx_data = ¬ification_data; 527 snd_sof_ipc_msgs_rx(sdev); 528 sdev->ipc->msg.rx_data = NULL; 529 } 530 531 mtl_ipc_host_done(sdev); 532 533 ipc_irq = true; 534 } 535 536 if (!ipc_irq) { 537 /* This interrupt is not shared so no need to return IRQ_NONE. */ 538 dev_dbg_ratelimited(sdev->dev, "nothing to do in IPC IRQ thread\n"); 539 } 540 541 return IRQ_HANDLED; 542 } 543 544 static int mtl_dsp_ipc_get_mailbox_offset(struct snd_sof_dev *sdev) 545 { 546 return MTL_DSP_MBOX_UPLINK_OFFSET; 547 } 548 549 static int mtl_dsp_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id) 550 { 551 return MTL_SRAM_WINDOW_OFFSET(id); 552 } 553 554 static int mtl_suspend(struct snd_sof_dev *sdev, bool runtime_suspend) 555 { 556 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 557 const struct sof_intel_dsp_desc *chip = hda->desc; 558 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) 559 struct hdac_bus *bus = sof_to_bus(sdev); 560 #endif 561 u32 dsphfdsscs; 562 u32 cpa; 563 int ret; 564 int i; 565 566 mtl_disable_ipc_interrupts(sdev); 567 ret = mtl_disable_interrupts(sdev); 568 if (ret) 569 return ret; 570 571 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) 572 hda_codec_jack_wake_enable(sdev, runtime_suspend); 573 /* power down all hda link */ 574 snd_hdac_ext_bus_link_power_down_all(bus); 575 #endif 576 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_HFPWRCTL, 577 MTL_HFPWRCTL_WPDSPHPXPG, 0); 578 579 /* Set the DSP subsystem power down */ 580 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_HFDSSCS, 581 MTL_HFDSSCS_SPA_MASK, 0); 582 583 /* Wait for unstable CPA read (1 then 0 then 1) just after setting SPA bit */ 584 usleep_range(1000, 1010); 585 586 /* poll with timeout to check if operation successful */ 587 cpa = MTL_HFDSSCS_CPA_MASK; 588 dsphfdsscs = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_HFDSSCS); 589 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_HFDSSCS, dsphfdsscs, 590 (dsphfdsscs & cpa) == 0, HDA_DSP_REG_POLL_INTERVAL_US, 591 HDA_DSP_RESET_TIMEOUT_US); 592 if (ret < 0) 593 dev_err(sdev->dev, "failed to disable DSP subsystem\n"); 594 595 /* reset ref counts for all cores */ 596 for (i = 0; i < chip->cores_num; i++) 597 sdev->dsp_core_ref_count[i] = 0; 598 599 /* TODO: need to reset controller? */ 600 601 /* display codec can be powered off after link reset */ 602 hda_codec_i915_display_power(sdev, false); 603 604 return 0; 605 } 606 607 static int mtl_dsp_suspend(struct snd_sof_dev *sdev, u32 target_state) 608 { 609 const struct sof_dsp_power_state target_dsp_state = { 610 .state = target_state, 611 .substate = target_state == SOF_DSP_PM_D0 ? 612 SOF_HDA_DSP_PM_D0I3 : 0, 613 }; 614 int ret; 615 616 ret = mtl_suspend(sdev, false); 617 if (ret < 0) 618 return ret; 619 620 return snd_sof_dsp_set_power_state(sdev, &target_dsp_state); 621 } 622 623 static int mtl_dsp_runtime_suspend(struct snd_sof_dev *sdev) 624 { 625 const struct sof_dsp_power_state target_state = { 626 .state = SOF_DSP_PM_D3, 627 }; 628 int ret; 629 630 ret = mtl_suspend(sdev, true); 631 if (ret < 0) 632 return ret; 633 634 return snd_sof_dsp_set_power_state(sdev, &target_state); 635 } 636 637 static int mtl_resume(struct snd_sof_dev *sdev, bool runtime_resume) 638 { 639 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) 640 struct hdac_bus *bus = sof_to_bus(sdev); 641 struct hdac_ext_link *hlink = NULL; 642 #endif 643 644 /* display codec must be powered before link reset */ 645 hda_codec_i915_display_power(sdev, true); 646 647 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) 648 /* check jack status */ 649 if (runtime_resume) { 650 hda_codec_jack_wake_enable(sdev, false); 651 if (sdev->system_suspend_target == SOF_SUSPEND_NONE) 652 hda_codec_jack_check(sdev); 653 } 654 655 /* turn off the links that were off before suspend */ 656 list_for_each_entry(hlink, &bus->hlink_list, list) { 657 if (!hlink->ref_count) 658 snd_hdac_ext_bus_link_power_down(hlink); 659 } 660 661 /* check dma status and clean up CORB/RIRB buffers */ 662 if (!bus->cmd_dma_state) 663 snd_hdac_bus_stop_cmd_io(bus); 664 #endif 665 666 return 0; 667 } 668 669 static int mtl_dsp_resume(struct snd_sof_dev *sdev) 670 { 671 const struct sof_dsp_power_state target_state = { 672 .state = SOF_DSP_PM_D0, 673 .substate = SOF_HDA_DSP_PM_D0I0, 674 }; 675 int ret; 676 677 ret = mtl_resume(sdev, false); 678 if (ret < 0) 679 return ret; 680 681 return snd_sof_dsp_set_power_state(sdev, &target_state); 682 } 683 684 static int mtl_dsp_runtime_resume(struct snd_sof_dev *sdev) 685 { 686 const struct sof_dsp_power_state target_state = { 687 .state = SOF_DSP_PM_D0, 688 }; 689 int ret; 690 691 ret = mtl_resume(sdev, true); 692 if (ret < 0) 693 return ret; 694 695 return snd_sof_dsp_set_power_state(sdev, &target_state); 696 } 697 698 static void mtl_ipc_dump(struct snd_sof_dev *sdev) 699 { 700 u32 hipcctl; 701 u32 hipcida; 702 u32 hipctdr; 703 704 /* read IPC status */ 705 hipcida = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDA); 706 hipcctl = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXCTL); 707 hipctdr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDR); 708 709 /* dump the IPC regs */ 710 /* TODO: parse the raw msg */ 711 dev_err(sdev->dev, 712 "error: host status 0x%8.8x dsp status 0x%8.8x mask 0x%8.8x\n", 713 hipcida, hipctdr, hipcctl); 714 } 715 716 /* Meteorlake ops */ 717 struct snd_sof_dsp_ops sof_mtl_ops; 718 EXPORT_SYMBOL_NS(sof_mtl_ops, SND_SOC_SOF_INTEL_HDA_COMMON); 719 720 int sof_mtl_ops_init(struct snd_sof_dev *sdev) 721 { 722 struct sof_ipc4_fw_data *ipc4_data; 723 724 /* common defaults */ 725 memcpy(&sof_mtl_ops, &sof_hda_common_ops, sizeof(struct snd_sof_dsp_ops)); 726 727 /* shutdown */ 728 sof_mtl_ops.shutdown = hda_dsp_shutdown; 729 730 /* doorbell */ 731 sof_mtl_ops.irq_thread = mtl_ipc_irq_thread; 732 733 /* ipc */ 734 sof_mtl_ops.send_msg = mtl_ipc_send_msg; 735 sof_mtl_ops.get_mailbox_offset = mtl_dsp_ipc_get_mailbox_offset; 736 sof_mtl_ops.get_window_offset = mtl_dsp_ipc_get_window_offset; 737 738 /* debug */ 739 sof_mtl_ops.debug_map = mtl_dsp_debugfs; 740 sof_mtl_ops.debug_map_count = ARRAY_SIZE(mtl_dsp_debugfs); 741 sof_mtl_ops.dbg_dump = mtl_dsp_dump; 742 sof_mtl_ops.ipc_dump = mtl_ipc_dump; 743 744 /* pre/post fw run */ 745 sof_mtl_ops.pre_fw_run = mtl_dsp_pre_fw_run; 746 sof_mtl_ops.post_fw_run = mtl_dsp_post_fw_run; 747 748 /* parse platform specific extended manifest */ 749 sof_mtl_ops.parse_platform_ext_manifest = NULL; 750 751 /* dsp core get/put */ 752 /* TODO: add core_get and core_put */ 753 754 /* PM */ 755 sof_mtl_ops.suspend = mtl_dsp_suspend; 756 sof_mtl_ops.resume = mtl_dsp_resume; 757 sof_mtl_ops.runtime_suspend = mtl_dsp_runtime_suspend; 758 sof_mtl_ops.runtime_resume = mtl_dsp_runtime_resume; 759 760 sdev->private = devm_kzalloc(sdev->dev, sizeof(struct sof_ipc4_fw_data), GFP_KERNEL); 761 if (!sdev->private) 762 return -ENOMEM; 763 764 ipc4_data = sdev->private; 765 ipc4_data->manifest_fw_hdr_offset = SOF_MAN4_FW_HDR_OFFSET; 766 767 /* set DAI ops */ 768 hda_set_dai_drv_ops(sdev, &sof_mtl_ops); 769 770 return 0; 771 }; 772 EXPORT_SYMBOL_NS(sof_mtl_ops_init, SND_SOC_SOF_INTEL_HDA_COMMON); 773 774 const struct sof_intel_dsp_desc mtl_chip_info = { 775 .cores_num = 3, 776 .init_core_mask = BIT(0), 777 .host_managed_cores_mask = BIT(0), 778 .ipc_req = MTL_DSP_REG_HFIPCXIDR, 779 .ipc_req_mask = MTL_DSP_REG_HFIPCXIDR_BUSY, 780 .ipc_ack = MTL_DSP_REG_HFIPCXIDA, 781 .ipc_ack_mask = MTL_DSP_REG_HFIPCXIDA_DONE, 782 .ipc_ctl = MTL_DSP_REG_HFIPCXCTL, 783 .rom_status_reg = MTL_DSP_ROM_STS, 784 .rom_init_timeout = 300, 785 .ssp_count = ICL_SSP_COUNT, 786 .ssp_base_offset = CNL_SSP_BASE_OFFSET, 787 .sdw_shim_base = SDW_SHIM_BASE_ACE, 788 .sdw_alh_base = SDW_ALH_BASE_ACE, 789 .check_sdw_irq = mtl_dsp_check_sdw_irq, 790 .check_ipc_irq = mtl_dsp_check_ipc_irq, 791 .cl_init = mtl_dsp_cl_init, 792 .hw_ip_version = SOF_INTEL_ACE_1_0, 793 }; 794 EXPORT_SYMBOL_NS(mtl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); 795