1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 // 3 // Copyright(c) 2020 Intel Corporation. All rights reserved. 4 // 5 // Author: Fred Oh <fred.oh@linux.intel.com> 6 // 7 8 /* 9 * Hardware interface for audio DSP on IceLake. 10 */ 11 12 #include <linux/kernel.h> 13 #include <linux/kconfig.h> 14 #include <linux/export.h> 15 #include <linux/bits.h> 16 #include "../ops.h" 17 #include "hda.h" 18 #include "hda-ipc.h" 19 #include "../sof-audio.h" 20 21 static const struct snd_sof_debugfs_map icl_dsp_debugfs[] = { 22 {"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS}, 23 {"pp", HDA_DSP_PP_BAR, 0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS}, 24 {"dsp", HDA_DSP_BAR, 0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS}, 25 }; 26 27 /* Icelake ops */ 28 const struct snd_sof_dsp_ops sof_icl_ops = { 29 /* probe and remove */ 30 .probe = hda_dsp_probe, 31 .remove = hda_dsp_remove, 32 33 /* Register IO */ 34 .write = sof_io_write, 35 .read = sof_io_read, 36 .write64 = sof_io_write64, 37 .read64 = sof_io_read64, 38 39 /* Block IO */ 40 .block_read = sof_block_read, 41 .block_write = sof_block_write, 42 43 /* doorbell */ 44 .irq_thread = cnl_ipc_irq_thread, 45 46 /* ipc */ 47 .send_msg = cnl_ipc_send_msg, 48 .fw_ready = sof_fw_ready, 49 .get_mailbox_offset = hda_dsp_ipc_get_mailbox_offset, 50 .get_window_offset = hda_dsp_ipc_get_window_offset, 51 52 .ipc_msg_data = hda_ipc_msg_data, 53 .ipc_pcm_params = hda_ipc_pcm_params, 54 55 /* machine driver */ 56 .machine_select = hda_machine_select, 57 .machine_register = sof_machine_register, 58 .machine_unregister = sof_machine_unregister, 59 .set_mach_params = hda_set_mach_params, 60 61 /* debug */ 62 .debug_map = icl_dsp_debugfs, 63 .debug_map_count = ARRAY_SIZE(icl_dsp_debugfs), 64 .dbg_dump = hda_dsp_dump, 65 .ipc_dump = cnl_ipc_dump, 66 67 /* stream callbacks */ 68 .pcm_open = hda_dsp_pcm_open, 69 .pcm_close = hda_dsp_pcm_close, 70 .pcm_hw_params = hda_dsp_pcm_hw_params, 71 .pcm_hw_free = hda_dsp_stream_hw_free, 72 .pcm_trigger = hda_dsp_pcm_trigger, 73 .pcm_pointer = hda_dsp_pcm_pointer, 74 75 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_PROBES) 76 /* probe callbacks */ 77 .probe_assign = hda_probe_compr_assign, 78 .probe_free = hda_probe_compr_free, 79 .probe_set_params = hda_probe_compr_set_params, 80 .probe_trigger = hda_probe_compr_trigger, 81 .probe_pointer = hda_probe_compr_pointer, 82 #endif 83 84 /* firmware loading */ 85 .load_firmware = snd_sof_load_firmware_raw, 86 87 /* pre/post fw run */ 88 .pre_fw_run = hda_dsp_pre_fw_run, 89 .post_fw_run = hda_dsp_post_fw_run_icl, 90 91 /* parse platform specific extended manifest */ 92 .parse_platform_ext_manifest = hda_dsp_ext_man_get_cavs_config_data, 93 94 /* dsp core power up/down */ 95 .core_power_up = hda_dsp_enable_core, 96 .core_power_down = hda_dsp_core_reset_power_down, 97 98 /* firmware run */ 99 .run = hda_dsp_cl_boot_firmware_iccmax, 100 .stall = hda_dsp_core_stall_icl, 101 102 /* trace callback */ 103 .trace_init = hda_dsp_trace_init, 104 .trace_release = hda_dsp_trace_release, 105 .trace_trigger = hda_dsp_trace_trigger, 106 107 /* DAI drivers */ 108 .drv = skl_dai, 109 .num_drv = SOF_SKL_NUM_DAIS, 110 111 /* PM */ 112 .suspend = hda_dsp_suspend, 113 .resume = hda_dsp_resume, 114 .runtime_suspend = hda_dsp_runtime_suspend, 115 .runtime_resume = hda_dsp_runtime_resume, 116 .runtime_idle = hda_dsp_runtime_idle, 117 .set_hw_params_upon_resume = hda_dsp_set_hw_params_upon_resume, 118 .set_power_state = hda_dsp_set_power_state, 119 120 /* ALSA HW info flags */ 121 .hw_info = SNDRV_PCM_INFO_MMAP | 122 SNDRV_PCM_INFO_MMAP_VALID | 123 SNDRV_PCM_INFO_INTERLEAVED | 124 SNDRV_PCM_INFO_PAUSE | 125 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP, 126 127 .arch_ops = &sof_xtensa_arch_ops, 128 }; 129 EXPORT_SYMBOL_NS(sof_icl_ops, SND_SOC_SOF_INTEL_HDA_COMMON); 130 131 const struct sof_intel_dsp_desc icl_chip_info = { 132 /* Icelake */ 133 .cores_num = 4, 134 .init_core_mask = 1, 135 .host_managed_cores_mask = GENMASK(3, 0), 136 .ipc_req = CNL_DSP_REG_HIPCIDR, 137 .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY, 138 .ipc_ack = CNL_DSP_REG_HIPCIDA, 139 .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE, 140 .ipc_ctl = CNL_DSP_REG_HIPCCTL, 141 .rom_init_timeout = 300, 142 .ssp_count = ICL_SSP_COUNT, 143 .ssp_base_offset = CNL_SSP_BASE_OFFSET, 144 }; 145 EXPORT_SYMBOL_NS(icl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); 146