1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ 2 /* 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * Copyright(c) 2017 Intel Corporation. All rights reserved. 7 * 8 * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com> 9 */ 10 11 #ifndef __SOF_INTEL_HDA_H 12 #define __SOF_INTEL_HDA_H 13 14 #include <linux/soundwire/sdw.h> 15 #include <linux/soundwire/sdw_intel.h> 16 #include <sound/compress_driver.h> 17 #include <sound/hda_codec.h> 18 #include <sound/hdaudio_ext.h> 19 #include "../sof-client-probes.h" 20 #include "../sof-audio.h" 21 #include "shim.h" 22 23 /* PCI registers */ 24 #define PCI_TCSEL 0x44 25 #define PCI_PGCTL PCI_TCSEL 26 #define PCI_CGCTL 0x48 27 28 /* PCI_PGCTL bits */ 29 #define PCI_PGCTL_ADSPPGD BIT(2) 30 #define PCI_PGCTL_LSRMD_MASK BIT(4) 31 32 /* PCI_CGCTL bits */ 33 #define PCI_CGCTL_MISCBDCGE_MASK BIT(6) 34 #define PCI_CGCTL_ADSPDCGE BIT(1) 35 36 /* Legacy HDA registers and bits used - widths are variable */ 37 #define SOF_HDA_GCAP 0x0 38 #define SOF_HDA_GCTL 0x8 39 /* accept unsol. response enable */ 40 #define SOF_HDA_GCTL_UNSOL BIT(8) 41 #define SOF_HDA_LLCH 0x14 42 #define SOF_HDA_INTCTL 0x20 43 #define SOF_HDA_INTSTS 0x24 44 #define SOF_HDA_WAKESTS 0x0E 45 #define SOF_HDA_WAKESTS_INT_MASK ((1 << 8) - 1) 46 #define SOF_HDA_RIRBSTS 0x5d 47 48 /* SOF_HDA_GCTL register bist */ 49 #define SOF_HDA_GCTL_RESET BIT(0) 50 51 /* SOF_HDA_INCTL regs */ 52 #define SOF_HDA_INT_GLOBAL_EN BIT(31) 53 #define SOF_HDA_INT_CTRL_EN BIT(30) 54 #define SOF_HDA_INT_ALL_STREAM 0xff 55 56 /* SOF_HDA_INTSTS regs */ 57 #define SOF_HDA_INTSTS_GIS BIT(31) 58 59 #define SOF_HDA_MAX_CAPS 10 60 #define SOF_HDA_CAP_ID_OFF 16 61 #define SOF_HDA_CAP_ID_MASK GENMASK(SOF_HDA_CAP_ID_OFF + 11,\ 62 SOF_HDA_CAP_ID_OFF) 63 #define SOF_HDA_CAP_NEXT_MASK 0xFFFF 64 65 #define SOF_HDA_GTS_CAP_ID 0x1 66 #define SOF_HDA_ML_CAP_ID 0x2 67 68 #define SOF_HDA_PP_CAP_ID 0x3 69 #define SOF_HDA_REG_PP_PPCH 0x10 70 #define SOF_HDA_REG_PP_PPCTL 0x04 71 #define SOF_HDA_REG_PP_PPSTS 0x08 72 #define SOF_HDA_PPCTL_PIE BIT(31) 73 #define SOF_HDA_PPCTL_GPROCEN BIT(30) 74 75 /*Vendor Specific Registers*/ 76 #define SOF_HDA_VS_D0I3C 0x104A 77 78 /* D0I3C Register fields */ 79 #define SOF_HDA_VS_D0I3C_CIP BIT(0) /* Command-In-Progress */ 80 #define SOF_HDA_VS_D0I3C_I3 BIT(2) /* D0i3 enable bit */ 81 82 /* DPIB entry size: 8 Bytes = 2 DWords */ 83 #define SOF_HDA_DPIB_ENTRY_SIZE 0x8 84 85 #define SOF_HDA_SPIB_CAP_ID 0x4 86 #define SOF_HDA_DRSM_CAP_ID 0x5 87 88 #define SOF_HDA_SPIB_BASE 0x08 89 #define SOF_HDA_SPIB_INTERVAL 0x08 90 #define SOF_HDA_SPIB_SPIB 0x00 91 #define SOF_HDA_SPIB_MAXFIFO 0x04 92 93 #define SOF_HDA_PPHC_BASE 0x10 94 #define SOF_HDA_PPHC_INTERVAL 0x10 95 96 #define SOF_HDA_PPLC_BASE 0x10 97 #define SOF_HDA_PPLC_MULTI 0x10 98 #define SOF_HDA_PPLC_INTERVAL 0x10 99 100 #define SOF_HDA_DRSM_BASE 0x08 101 #define SOF_HDA_DRSM_INTERVAL 0x08 102 103 /* Descriptor error interrupt */ 104 #define SOF_HDA_CL_DMA_SD_INT_DESC_ERR 0x10 105 106 /* FIFO error interrupt */ 107 #define SOF_HDA_CL_DMA_SD_INT_FIFO_ERR 0x08 108 109 /* Buffer completion interrupt */ 110 #define SOF_HDA_CL_DMA_SD_INT_COMPLETE 0x04 111 112 #define SOF_HDA_CL_DMA_SD_INT_MASK \ 113 (SOF_HDA_CL_DMA_SD_INT_DESC_ERR | \ 114 SOF_HDA_CL_DMA_SD_INT_FIFO_ERR | \ 115 SOF_HDA_CL_DMA_SD_INT_COMPLETE) 116 #define SOF_HDA_SD_CTL_DMA_START 0x02 /* Stream DMA start bit */ 117 118 /* Intel HD Audio Code Loader DMA Registers */ 119 #define SOF_HDA_ADSP_LOADER_BASE 0x80 120 #define SOF_HDA_ADSP_DPLBASE 0x70 121 #define SOF_HDA_ADSP_DPUBASE 0x74 122 #define SOF_HDA_ADSP_DPLBASE_ENABLE 0x01 123 124 /* Stream Registers */ 125 #define SOF_HDA_ADSP_REG_CL_SD_CTL 0x00 126 #define SOF_HDA_ADSP_REG_CL_SD_STS 0x03 127 #define SOF_HDA_ADSP_REG_CL_SD_LPIB 0x04 128 #define SOF_HDA_ADSP_REG_CL_SD_CBL 0x08 129 #define SOF_HDA_ADSP_REG_CL_SD_LVI 0x0C 130 #define SOF_HDA_ADSP_REG_CL_SD_FIFOW 0x0E 131 #define SOF_HDA_ADSP_REG_CL_SD_FIFOSIZE 0x10 132 #define SOF_HDA_ADSP_REG_CL_SD_FORMAT 0x12 133 #define SOF_HDA_ADSP_REG_CL_SD_FIFOL 0x14 134 #define SOF_HDA_ADSP_REG_CL_SD_BDLPL 0x18 135 #define SOF_HDA_ADSP_REG_CL_SD_BDLPU 0x1C 136 #define SOF_HDA_ADSP_SD_ENTRY_SIZE 0x20 137 138 /* CL: Software Position Based FIFO Capability Registers */ 139 #define SOF_DSP_REG_CL_SPBFIFO \ 140 (SOF_HDA_ADSP_LOADER_BASE + 0x20) 141 #define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCH 0x0 142 #define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCCTL 0x4 143 #define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPIB 0x8 144 #define SOF_HDA_ADSP_REG_CL_SPBFIFO_MAXFIFOS 0xc 145 146 /* Stream Number */ 147 #define SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT 20 148 #define SOF_HDA_CL_SD_CTL_STREAM_TAG_MASK \ 149 GENMASK(SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT + 3,\ 150 SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT) 151 152 #define HDA_DSP_HDA_BAR 0 153 #define HDA_DSP_PP_BAR 1 154 #define HDA_DSP_SPIB_BAR 2 155 #define HDA_DSP_DRSM_BAR 3 156 #define HDA_DSP_BAR 4 157 158 #define SRAM_WINDOW_OFFSET(x) (0x80000 + (x) * 0x20000) 159 160 #define HDA_DSP_MBOX_OFFSET SRAM_WINDOW_OFFSET(0) 161 162 #define HDA_DSP_PANIC_OFFSET(x) \ 163 (((x) & 0xFFFFFF) + HDA_DSP_MBOX_OFFSET) 164 165 /* SRAM window 0 FW "registers" */ 166 #define HDA_DSP_SRAM_REG_ROM_STATUS (HDA_DSP_MBOX_OFFSET + 0x0) 167 #define HDA_DSP_SRAM_REG_ROM_ERROR (HDA_DSP_MBOX_OFFSET + 0x4) 168 /* FW and ROM share offset 4 */ 169 #define HDA_DSP_SRAM_REG_FW_STATUS (HDA_DSP_MBOX_OFFSET + 0x4) 170 #define HDA_DSP_SRAM_REG_FW_TRACEP (HDA_DSP_MBOX_OFFSET + 0x8) 171 #define HDA_DSP_SRAM_REG_FW_END (HDA_DSP_MBOX_OFFSET + 0xc) 172 173 #define HDA_DSP_MBOX_UPLINK_OFFSET 0x81000 174 175 #define HDA_DSP_STREAM_RESET_TIMEOUT 300 176 /* 177 * Timeout in us, for setting the stream RUN bit, during 178 * start/stop the stream. The timeout expires if new RUN bit 179 * value cannot be read back within the specified time. 180 */ 181 #define HDA_DSP_STREAM_RUN_TIMEOUT 300 182 183 #define HDA_DSP_SPIB_ENABLE 1 184 #define HDA_DSP_SPIB_DISABLE 0 185 186 #define SOF_HDA_MAX_BUFFER_SIZE (32 * PAGE_SIZE) 187 188 #define HDA_DSP_STACK_DUMP_SIZE 32 189 190 /* ROM/FW status register */ 191 #define FSR_STATE_MASK GENMASK(23, 0) 192 #define FSR_WAIT_STATE_MASK GENMASK(27, 24) 193 #define FSR_MODULE_MASK GENMASK(30, 28) 194 #define FSR_HALTED BIT(31) 195 #define FSR_TO_STATE_CODE(x) ((x) & FSR_STATE_MASK) 196 #define FSR_TO_WAIT_STATE_CODE(x) (((x) & FSR_WAIT_STATE_MASK) >> 24) 197 #define FSR_TO_MODULE_CODE(x) (((x) & FSR_MODULE_MASK) >> 28) 198 199 /* Wait states */ 200 #define FSR_WAIT_FOR_IPC_BUSY 0x1 201 #define FSR_WAIT_FOR_IPC_DONE 0x2 202 #define FSR_WAIT_FOR_CACHE_INVALIDATION 0x3 203 #define FSR_WAIT_FOR_LP_SRAM_OFF 0x4 204 #define FSR_WAIT_FOR_DMA_BUFFER_FULL 0x5 205 #define FSR_WAIT_FOR_CSE_CSR 0x6 206 207 /* Module codes */ 208 #define FSR_MOD_ROM 0x0 209 #define FSR_MOD_ROM_BYP 0x1 210 #define FSR_MOD_BASE_FW 0x2 211 #define FSR_MOD_LP_BOOT 0x3 212 #define FSR_MOD_BRNGUP 0x4 213 #define FSR_MOD_ROM_EXT 0x5 214 215 /* State codes (module dependent) */ 216 /* Module independent states */ 217 #define FSR_STATE_INIT 0x0 218 #define FSR_STATE_INIT_DONE 0x1 219 #define FSR_STATE_FW_ENTERED 0x5 220 221 /* ROM states */ 222 #define FSR_STATE_ROM_INIT FSR_STATE_INIT 223 #define FSR_STATE_ROM_INIT_DONE FSR_STATE_INIT_DONE 224 #define FSR_STATE_ROM_CSE_MANIFEST_LOADED 0x2 225 #define FSR_STATE_ROM_FW_MANIFEST_LOADED 0x3 226 #define FSR_STATE_ROM_FW_FW_LOADED 0x4 227 #define FSR_STATE_ROM_FW_ENTERED FSR_STATE_FW_ENTERED 228 #define FSR_STATE_ROM_VERIFY_FEATURE_MASK 0x6 229 #define FSR_STATE_ROM_GET_LOAD_OFFSET 0x7 230 #define FSR_STATE_ROM_FETCH_ROM_EXT 0x8 231 #define FSR_STATE_ROM_FETCH_ROM_EXT_DONE 0x9 232 233 /* (ROM) CSE states */ 234 #define FSR_STATE_ROM_CSE_IMR_REQUEST 0x10 235 #define FSR_STATE_ROM_CSE_IMR_GRANTED 0x11 236 #define FSR_STATE_ROM_CSE_VALIDATE_IMAGE_REQUEST 0x12 237 #define FSR_STATE_ROM_CSE_IMAGE_VALIDATED 0x13 238 239 #define FSR_STATE_ROM_CSE_IPC_IFACE_INIT 0x20 240 #define FSR_STATE_ROM_CSE_IPC_RESET_PHASE_1 0x21 241 #define FSR_STATE_ROM_CSE_IPC_OPERATIONAL_ENTRY 0x22 242 #define FSR_STATE_ROM_CSE_IPC_OPERATIONAL 0x23 243 #define FSR_STATE_ROM_CSE_IPC_DOWN 0x24 244 245 /* BRINGUP (or BRNGUP) states */ 246 #define FSR_STATE_BRINGUP_INIT FSR_STATE_INIT 247 #define FSR_STATE_BRINGUP_INIT_DONE FSR_STATE_INIT_DONE 248 #define FSR_STATE_BRINGUP_HPSRAM_LOAD 0x2 249 #define FSR_STATE_BRINGUP_UNPACK_START 0X3 250 #define FSR_STATE_BRINGUP_IMR_RESTORE 0x4 251 #define FSR_STATE_BRINGUP_FW_ENTERED FSR_STATE_FW_ENTERED 252 253 /* ROM status/error values */ 254 #define HDA_DSP_ROM_STS_MASK GENMASK(23, 0) 255 #define HDA_DSP_ROM_INIT 0x1 256 #define HDA_DSP_ROM_FW_MANIFEST_LOADED 0x3 257 #define HDA_DSP_ROM_FW_FW_LOADED 0x4 258 #define HDA_DSP_ROM_FW_ENTERED 0x5 259 #define HDA_DSP_ROM_RFW_START 0xf 260 #define HDA_DSP_ROM_CSE_ERROR 40 261 #define HDA_DSP_ROM_CSE_WRONG_RESPONSE 41 262 #define HDA_DSP_ROM_IMR_TO_SMALL 42 263 #define HDA_DSP_ROM_BASE_FW_NOT_FOUND 43 264 #define HDA_DSP_ROM_CSE_VALIDATION_FAILED 44 265 #define HDA_DSP_ROM_IPC_FATAL_ERROR 45 266 #define HDA_DSP_ROM_L2_CACHE_ERROR 46 267 #define HDA_DSP_ROM_LOAD_OFFSET_TO_SMALL 47 268 #define HDA_DSP_ROM_API_PTR_INVALID 50 269 #define HDA_DSP_ROM_BASEFW_INCOMPAT 51 270 #define HDA_DSP_ROM_UNHANDLED_INTERRUPT 0xBEE00000 271 #define HDA_DSP_ROM_MEMORY_HOLE_ECC 0xECC00000 272 #define HDA_DSP_ROM_KERNEL_EXCEPTION 0xCAFE0000 273 #define HDA_DSP_ROM_USER_EXCEPTION 0xBEEF0000 274 #define HDA_DSP_ROM_UNEXPECTED_RESET 0xDECAF000 275 #define HDA_DSP_ROM_NULL_FW_ENTRY 0x4c4c4e55 276 277 #define HDA_DSP_ROM_IPC_CONTROL 0x01000000 278 #define HDA_DSP_ROM_IPC_PURGE_FW 0x00004000 279 280 /* various timeout values */ 281 #define HDA_DSP_PU_TIMEOUT 50 282 #define HDA_DSP_PD_TIMEOUT 50 283 #define HDA_DSP_RESET_TIMEOUT_US 50000 284 #define HDA_DSP_BASEFW_TIMEOUT_US 3000000 285 #define HDA_DSP_INIT_TIMEOUT_US 500000 286 #define HDA_DSP_CTRL_RESET_TIMEOUT 100 287 #define HDA_DSP_WAIT_TIMEOUT 500 /* 500 msec */ 288 #define HDA_DSP_REG_POLL_INTERVAL_US 500 /* 0.5 msec */ 289 #define HDA_DSP_REG_POLL_RETRY_COUNT 50 290 291 #define HDA_DSP_ADSPIC_IPC BIT(0) 292 #define HDA_DSP_ADSPIS_IPC BIT(0) 293 294 /* Intel HD Audio General DSP Registers */ 295 #define HDA_DSP_GEN_BASE 0x0 296 #define HDA_DSP_REG_ADSPCS (HDA_DSP_GEN_BASE + 0x04) 297 #define HDA_DSP_REG_ADSPIC (HDA_DSP_GEN_BASE + 0x08) 298 #define HDA_DSP_REG_ADSPIS (HDA_DSP_GEN_BASE + 0x0C) 299 #define HDA_DSP_REG_ADSPIC2 (HDA_DSP_GEN_BASE + 0x10) 300 #define HDA_DSP_REG_ADSPIS2 (HDA_DSP_GEN_BASE + 0x14) 301 302 #define HDA_DSP_REG_ADSPIS2_SNDW BIT(5) 303 304 /* Intel HD Audio Inter-Processor Communication Registers */ 305 #define HDA_DSP_IPC_BASE 0x40 306 #define HDA_DSP_REG_HIPCT (HDA_DSP_IPC_BASE + 0x00) 307 #define HDA_DSP_REG_HIPCTE (HDA_DSP_IPC_BASE + 0x04) 308 #define HDA_DSP_REG_HIPCI (HDA_DSP_IPC_BASE + 0x08) 309 #define HDA_DSP_REG_HIPCIE (HDA_DSP_IPC_BASE + 0x0C) 310 #define HDA_DSP_REG_HIPCCTL (HDA_DSP_IPC_BASE + 0x10) 311 312 /* Intel Vendor Specific Registers */ 313 #define HDA_VS_INTEL_EM2 0x1030 314 #define HDA_VS_INTEL_EM2_L1SEN BIT(13) 315 #define HDA_VS_INTEL_LTRP_GB_MASK 0x3F 316 317 /* HIPCI */ 318 #define HDA_DSP_REG_HIPCI_BUSY BIT(31) 319 #define HDA_DSP_REG_HIPCI_MSG_MASK 0x7FFFFFFF 320 321 /* HIPCIE */ 322 #define HDA_DSP_REG_HIPCIE_DONE BIT(30) 323 #define HDA_DSP_REG_HIPCIE_MSG_MASK 0x3FFFFFFF 324 325 /* HIPCCTL */ 326 #define HDA_DSP_REG_HIPCCTL_DONE BIT(1) 327 #define HDA_DSP_REG_HIPCCTL_BUSY BIT(0) 328 329 /* HIPCT */ 330 #define HDA_DSP_REG_HIPCT_BUSY BIT(31) 331 #define HDA_DSP_REG_HIPCT_MSG_MASK 0x7FFFFFFF 332 333 /* HIPCTE */ 334 #define HDA_DSP_REG_HIPCTE_MSG_MASK 0x3FFFFFFF 335 336 #define HDA_DSP_ADSPIC_CL_DMA BIT(1) 337 #define HDA_DSP_ADSPIS_CL_DMA BIT(1) 338 339 /* Delay before scheduling D0i3 entry */ 340 #define BXT_D0I3_DELAY 5000 341 342 #define FW_CL_STREAM_NUMBER 0x1 343 #define HDA_FW_BOOT_ATTEMPTS 3 344 345 /* ADSPCS - Audio DSP Control & Status */ 346 347 /* 348 * Core Reset - asserted high 349 * CRST Mask for a given core mask pattern, cm 350 */ 351 #define HDA_DSP_ADSPCS_CRST_SHIFT 0 352 #define HDA_DSP_ADSPCS_CRST_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CRST_SHIFT) 353 354 /* 355 * Core run/stall - when set to '1' core is stalled 356 * CSTALL Mask for a given core mask pattern, cm 357 */ 358 #define HDA_DSP_ADSPCS_CSTALL_SHIFT 8 359 #define HDA_DSP_ADSPCS_CSTALL_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CSTALL_SHIFT) 360 361 /* 362 * Set Power Active - when set to '1' turn cores on 363 * SPA Mask for a given core mask pattern, cm 364 */ 365 #define HDA_DSP_ADSPCS_SPA_SHIFT 16 366 #define HDA_DSP_ADSPCS_SPA_MASK(cm) ((cm) << HDA_DSP_ADSPCS_SPA_SHIFT) 367 368 /* 369 * Current Power Active - power status of cores, set by hardware 370 * CPA Mask for a given core mask pattern, cm 371 */ 372 #define HDA_DSP_ADSPCS_CPA_SHIFT 24 373 #define HDA_DSP_ADSPCS_CPA_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CPA_SHIFT) 374 375 /* 376 * Mask for a given number of cores 377 * nc = number of supported cores 378 */ 379 #define SOF_DSP_CORES_MASK(nc) GENMASK(((nc) - 1), 0) 380 381 /* Intel HD Audio Inter-Processor Communication Registers for Cannonlake*/ 382 #define CNL_DSP_IPC_BASE 0xc0 383 #define CNL_DSP_REG_HIPCTDR (CNL_DSP_IPC_BASE + 0x00) 384 #define CNL_DSP_REG_HIPCTDA (CNL_DSP_IPC_BASE + 0x04) 385 #define CNL_DSP_REG_HIPCTDD (CNL_DSP_IPC_BASE + 0x08) 386 #define CNL_DSP_REG_HIPCIDR (CNL_DSP_IPC_BASE + 0x10) 387 #define CNL_DSP_REG_HIPCIDA (CNL_DSP_IPC_BASE + 0x14) 388 #define CNL_DSP_REG_HIPCIDD (CNL_DSP_IPC_BASE + 0x18) 389 #define CNL_DSP_REG_HIPCCTL (CNL_DSP_IPC_BASE + 0x28) 390 391 /* HIPCI */ 392 #define CNL_DSP_REG_HIPCIDR_BUSY BIT(31) 393 #define CNL_DSP_REG_HIPCIDR_MSG_MASK 0x7FFFFFFF 394 395 /* HIPCIE */ 396 #define CNL_DSP_REG_HIPCIDA_DONE BIT(31) 397 #define CNL_DSP_REG_HIPCIDA_MSG_MASK 0x7FFFFFFF 398 399 /* HIPCCTL */ 400 #define CNL_DSP_REG_HIPCCTL_DONE BIT(1) 401 #define CNL_DSP_REG_HIPCCTL_BUSY BIT(0) 402 403 /* HIPCT */ 404 #define CNL_DSP_REG_HIPCTDR_BUSY BIT(31) 405 #define CNL_DSP_REG_HIPCTDR_MSG_MASK 0x7FFFFFFF 406 407 /* HIPCTDA */ 408 #define CNL_DSP_REG_HIPCTDA_DONE BIT(31) 409 #define CNL_DSP_REG_HIPCTDA_MSG_MASK 0x7FFFFFFF 410 411 /* HIPCTDD */ 412 #define CNL_DSP_REG_HIPCTDD_MSG_MASK 0x7FFFFFFF 413 414 /* BDL */ 415 #define HDA_DSP_BDL_SIZE 4096 416 #define HDA_DSP_MAX_BDL_ENTRIES \ 417 (HDA_DSP_BDL_SIZE / sizeof(struct sof_intel_dsp_bdl)) 418 419 /* Number of DAIs */ 420 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) 421 #define SOF_SKL_NUM_DAIS 15 422 #else 423 #define SOF_SKL_NUM_DAIS 8 424 #endif 425 426 /* Intel HD Audio SRAM Window 0*/ 427 #define HDA_ADSP_SRAM0_BASE_SKL 0x8000 428 429 /* Firmware status window */ 430 #define HDA_ADSP_FW_STATUS_SKL HDA_ADSP_SRAM0_BASE_SKL 431 #define HDA_ADSP_ERROR_CODE_SKL (HDA_ADSP_FW_STATUS_SKL + 0x4) 432 433 /* Host Device Memory Space */ 434 #define APL_SSP_BASE_OFFSET 0x2000 435 #define CNL_SSP_BASE_OFFSET 0x10000 436 437 /* Host Device Memory Size of a Single SSP */ 438 #define SSP_DEV_MEM_SIZE 0x1000 439 440 /* SSP Count of the Platform */ 441 #define APL_SSP_COUNT 6 442 #define CNL_SSP_COUNT 3 443 #define ICL_SSP_COUNT 6 444 445 /* SSP Registers */ 446 #define SSP_SSC1_OFFSET 0x4 447 #define SSP_SET_SCLK_CONSUMER BIT(25) 448 #define SSP_SET_SFRM_CONSUMER BIT(24) 449 #define SSP_SET_CBP_CFP (SSP_SET_SCLK_CONSUMER | SSP_SET_SFRM_CONSUMER) 450 451 #define HDA_IDISP_ADDR 2 452 #define HDA_IDISP_CODEC(x) ((x) & BIT(HDA_IDISP_ADDR)) 453 454 struct sof_intel_dsp_bdl { 455 __le32 addr_l; 456 __le32 addr_h; 457 __le32 size; 458 __le32 ioc; 459 } __attribute((packed)); 460 461 #define SOF_HDA_PLAYBACK_STREAMS 16 462 #define SOF_HDA_CAPTURE_STREAMS 16 463 #define SOF_HDA_PLAYBACK 0 464 #define SOF_HDA_CAPTURE 1 465 466 /* stream flags */ 467 #define SOF_HDA_STREAM_DMI_L1_COMPATIBLE 1 468 469 /* 470 * Time in ms for opportunistic D0I3 entry delay. 471 * This has been deliberately chosen to be long to avoid race conditions. 472 * Could be optimized in future. 473 */ 474 #define SOF_HDA_D0I3_WORK_DELAY_MS 5000 475 476 /* HDA DSP D0 substate */ 477 enum sof_hda_D0_substate { 478 SOF_HDA_DSP_PM_D0I0, /* default D0 substate */ 479 SOF_HDA_DSP_PM_D0I3, /* low power D0 substate */ 480 }; 481 482 /* represents DSP HDA controller frontend - i.e. host facing control */ 483 struct sof_intel_hda_dev { 484 bool imrboot_supported; 485 bool skip_imr_boot; 486 487 int boot_iteration; 488 489 struct hda_bus hbus; 490 491 /* hw config */ 492 const struct sof_intel_dsp_desc *desc; 493 494 /* trace */ 495 struct hdac_ext_stream *dtrace_stream; 496 497 /* if position update IPC needed */ 498 u32 no_ipc_position; 499 500 /* the maximum number of streams (playback + capture) supported */ 501 u32 stream_max; 502 503 /* PM related */ 504 bool l1_support_changed;/* during suspend, is L1SEN changed or not */ 505 506 /* DMIC device */ 507 struct platform_device *dmic_dev; 508 509 /* delayed work to enter D0I3 opportunistically */ 510 struct delayed_work d0i3_work; 511 512 /* ACPI information stored between scan and probe steps */ 513 struct sdw_intel_acpi_info info; 514 515 /* sdw context allocated by SoundWire driver */ 516 struct sdw_intel_ctx *sdw; 517 518 /* FW clock config, 0:HPRO, 1:LPRO */ 519 bool clk_config_lpro; 520 521 /* Intel NHLT information */ 522 struct nhlt_acpi_table *nhlt; 523 }; 524 525 static inline struct hdac_bus *sof_to_bus(struct snd_sof_dev *s) 526 { 527 struct sof_intel_hda_dev *hda = s->pdata->hw_pdata; 528 529 return &hda->hbus.core; 530 } 531 532 static inline struct hda_bus *sof_to_hbus(struct snd_sof_dev *s) 533 { 534 struct sof_intel_hda_dev *hda = s->pdata->hw_pdata; 535 536 return &hda->hbus; 537 } 538 539 struct sof_intel_hda_stream { 540 struct snd_sof_dev *sdev; 541 struct hdac_ext_stream hext_stream; 542 struct sof_intel_stream sof_intel_stream; 543 int host_reserved; /* reserve host DMA channel */ 544 u32 flags; 545 }; 546 547 #define hstream_to_sof_hda_stream(hstream) \ 548 container_of(hstream, struct sof_intel_hda_stream, hext_stream) 549 550 #define bus_to_sof_hda(bus) \ 551 container_of(bus, struct sof_intel_hda_dev, hbus.core) 552 553 #define SOF_STREAM_SD_OFFSET(s) \ 554 (SOF_HDA_ADSP_SD_ENTRY_SIZE * ((s)->index) \ 555 + SOF_HDA_ADSP_LOADER_BASE) 556 557 #define SOF_STREAM_SD_OFFSET_CRST 0x1 558 559 /* 560 * DSP Core services. 561 */ 562 int hda_dsp_probe(struct snd_sof_dev *sdev); 563 int hda_dsp_remove(struct snd_sof_dev *sdev); 564 int hda_dsp_core_power_up(struct snd_sof_dev *sdev, unsigned int core_mask); 565 int hda_dsp_core_run(struct snd_sof_dev *sdev, unsigned int core_mask); 566 int hda_dsp_enable_core(struct snd_sof_dev *sdev, unsigned int core_mask); 567 int hda_dsp_core_reset_power_down(struct snd_sof_dev *sdev, 568 unsigned int core_mask); 569 int hda_dsp_core_get(struct snd_sof_dev *sdev, int core); 570 void hda_dsp_ipc_int_enable(struct snd_sof_dev *sdev); 571 void hda_dsp_ipc_int_disable(struct snd_sof_dev *sdev); 572 573 int hda_dsp_set_power_state(struct snd_sof_dev *sdev, 574 const struct sof_dsp_power_state *target_state); 575 576 int hda_dsp_suspend(struct snd_sof_dev *sdev, u32 target_state); 577 int hda_dsp_resume(struct snd_sof_dev *sdev); 578 int hda_dsp_runtime_suspend(struct snd_sof_dev *sdev); 579 int hda_dsp_runtime_resume(struct snd_sof_dev *sdev); 580 int hda_dsp_runtime_idle(struct snd_sof_dev *sdev); 581 int hda_dsp_shutdown(struct snd_sof_dev *sdev); 582 int hda_dsp_set_hw_params_upon_resume(struct snd_sof_dev *sdev); 583 void hda_dsp_dump(struct snd_sof_dev *sdev, u32 flags); 584 void hda_ipc_dump(struct snd_sof_dev *sdev); 585 void hda_ipc_irq_dump(struct snd_sof_dev *sdev); 586 void hda_dsp_d0i3_work(struct work_struct *work); 587 588 /* 589 * DSP PCM Operations. 590 */ 591 u32 hda_dsp_get_mult_div(struct snd_sof_dev *sdev, int rate); 592 u32 hda_dsp_get_bits(struct snd_sof_dev *sdev, int sample_bits); 593 int hda_dsp_pcm_open(struct snd_sof_dev *sdev, 594 struct snd_pcm_substream *substream); 595 int hda_dsp_pcm_close(struct snd_sof_dev *sdev, 596 struct snd_pcm_substream *substream); 597 int hda_dsp_pcm_hw_params(struct snd_sof_dev *sdev, 598 struct snd_pcm_substream *substream, 599 struct snd_pcm_hw_params *params, 600 struct snd_sof_platform_stream_params *platform_params); 601 int hda_dsp_stream_hw_free(struct snd_sof_dev *sdev, 602 struct snd_pcm_substream *substream); 603 int hda_dsp_pcm_trigger(struct snd_sof_dev *sdev, 604 struct snd_pcm_substream *substream, int cmd); 605 snd_pcm_uframes_t hda_dsp_pcm_pointer(struct snd_sof_dev *sdev, 606 struct snd_pcm_substream *substream); 607 int hda_dsp_pcm_ack(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream); 608 609 /* 610 * DSP Stream Operations. 611 */ 612 613 int hda_dsp_stream_init(struct snd_sof_dev *sdev); 614 void hda_dsp_stream_free(struct snd_sof_dev *sdev); 615 int hda_dsp_stream_hw_params(struct snd_sof_dev *sdev, 616 struct hdac_ext_stream *hext_stream, 617 struct snd_dma_buffer *dmab, 618 struct snd_pcm_hw_params *params); 619 int hda_dsp_iccmax_stream_hw_params(struct snd_sof_dev *sdev, 620 struct hdac_ext_stream *hext_stream, 621 struct snd_dma_buffer *dmab, 622 struct snd_pcm_hw_params *params); 623 int hda_dsp_stream_trigger(struct snd_sof_dev *sdev, 624 struct hdac_ext_stream *hext_stream, int cmd); 625 irqreturn_t hda_dsp_stream_threaded_handler(int irq, void *context); 626 int hda_dsp_stream_setup_bdl(struct snd_sof_dev *sdev, 627 struct snd_dma_buffer *dmab, 628 struct hdac_stream *hstream); 629 bool hda_dsp_check_ipc_irq(struct snd_sof_dev *sdev); 630 bool hda_dsp_check_stream_irq(struct snd_sof_dev *sdev); 631 632 snd_pcm_uframes_t hda_dsp_stream_get_position(struct hdac_stream *hstream, 633 int direction, bool can_sleep); 634 635 struct hdac_ext_stream * 636 hda_dsp_stream_get(struct snd_sof_dev *sdev, int direction, u32 flags); 637 int hda_dsp_stream_put(struct snd_sof_dev *sdev, int direction, int stream_tag); 638 int hda_dsp_stream_spib_config(struct snd_sof_dev *sdev, 639 struct hdac_ext_stream *hext_stream, 640 int enable, u32 size); 641 642 int hda_ipc_msg_data(struct snd_sof_dev *sdev, 643 struct snd_pcm_substream *substream, 644 void *p, size_t sz); 645 int hda_set_stream_data_offset(struct snd_sof_dev *sdev, 646 struct snd_pcm_substream *substream, 647 size_t posn_offset); 648 649 /* 650 * DSP IPC Operations. 651 */ 652 int hda_dsp_ipc_send_msg(struct snd_sof_dev *sdev, 653 struct snd_sof_ipc_msg *msg); 654 void hda_dsp_ipc_get_reply(struct snd_sof_dev *sdev); 655 int hda_dsp_ipc_get_mailbox_offset(struct snd_sof_dev *sdev); 656 int hda_dsp_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id); 657 658 irqreturn_t hda_dsp_ipc_irq_thread(int irq, void *context); 659 int hda_dsp_ipc_cmd_done(struct snd_sof_dev *sdev, int dir); 660 661 /* 662 * DSP Code loader. 663 */ 664 int hda_dsp_cl_boot_firmware(struct snd_sof_dev *sdev); 665 int hda_dsp_cl_boot_firmware_iccmax(struct snd_sof_dev *sdev); 666 int hda_cl_copy_fw(struct snd_sof_dev *sdev, struct hdac_ext_stream *hext_stream); 667 struct hdac_ext_stream *hda_cl_stream_prepare(struct snd_sof_dev *sdev, unsigned int format, 668 unsigned int size, struct snd_dma_buffer *dmab, 669 int direction); 670 int hda_cl_cleanup(struct snd_sof_dev *sdev, struct snd_dma_buffer *dmab, 671 struct hdac_ext_stream *hext_stream); 672 int cl_dsp_init(struct snd_sof_dev *sdev, int stream_tag, bool imr_boot); 673 #define HDA_CL_STREAM_FORMAT 0x40 674 675 /* pre and post fw run ops */ 676 int hda_dsp_pre_fw_run(struct snd_sof_dev *sdev); 677 int hda_dsp_post_fw_run(struct snd_sof_dev *sdev); 678 679 /* parse platform specific ext manifest ops */ 680 int hda_dsp_ext_man_get_cavs_config_data(struct snd_sof_dev *sdev, 681 const struct sof_ext_man_elem_header *hdr); 682 683 /* 684 * HDA Controller Operations. 685 */ 686 int hda_dsp_ctrl_get_caps(struct snd_sof_dev *sdev); 687 void hda_dsp_ctrl_ppcap_enable(struct snd_sof_dev *sdev, bool enable); 688 void hda_dsp_ctrl_ppcap_int_enable(struct snd_sof_dev *sdev, bool enable); 689 int hda_dsp_ctrl_link_reset(struct snd_sof_dev *sdev, bool reset); 690 void hda_dsp_ctrl_misc_clock_gating(struct snd_sof_dev *sdev, bool enable); 691 int hda_dsp_ctrl_clock_power_gating(struct snd_sof_dev *sdev, bool enable); 692 int hda_dsp_ctrl_init_chip(struct snd_sof_dev *sdev, bool full_reset); 693 void hda_dsp_ctrl_stop_chip(struct snd_sof_dev *sdev); 694 /* 695 * HDA bus operations. 696 */ 697 void sof_hda_bus_init(struct hdac_bus *bus, struct device *dev); 698 699 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) 700 /* 701 * HDA Codec operations. 702 */ 703 void hda_codec_probe_bus(struct snd_sof_dev *sdev, 704 bool hda_codec_use_common_hdmi); 705 void hda_codec_jack_wake_enable(struct snd_sof_dev *sdev, bool enable); 706 void hda_codec_jack_check(struct snd_sof_dev *sdev); 707 708 #endif /* CONFIG_SND_SOC_SOF_HDA */ 709 710 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) && \ 711 (IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI) || \ 712 IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) 713 714 void hda_codec_i915_display_power(struct snd_sof_dev *sdev, bool enable); 715 int hda_codec_i915_init(struct snd_sof_dev *sdev); 716 int hda_codec_i915_exit(struct snd_sof_dev *sdev); 717 718 #else 719 720 static inline void hda_codec_i915_display_power(struct snd_sof_dev *sdev, 721 bool enable) { } 722 static inline int hda_codec_i915_init(struct snd_sof_dev *sdev) { return 0; } 723 static inline int hda_codec_i915_exit(struct snd_sof_dev *sdev) { return 0; } 724 725 #endif 726 727 /* 728 * Trace Control. 729 */ 730 int hda_dsp_trace_init(struct snd_sof_dev *sdev, struct snd_dma_buffer *dmab, 731 struct sof_ipc_dma_trace_params_ext *dtrace_params); 732 int hda_dsp_trace_release(struct snd_sof_dev *sdev); 733 int hda_dsp_trace_trigger(struct snd_sof_dev *sdev, int cmd); 734 735 /* 736 * SoundWire support 737 */ 738 #if IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE) 739 740 int hda_sdw_startup(struct snd_sof_dev *sdev); 741 void hda_sdw_int_enable(struct snd_sof_dev *sdev, bool enable); 742 void hda_sdw_process_wakeen(struct snd_sof_dev *sdev); 743 bool hda_common_check_sdw_irq(struct snd_sof_dev *sdev); 744 745 #else 746 747 static inline int hda_sdw_startup(struct snd_sof_dev *sdev) 748 { 749 return 0; 750 } 751 752 static inline void hda_sdw_int_enable(struct snd_sof_dev *sdev, bool enable) 753 { 754 } 755 756 static inline void hda_sdw_process_wakeen(struct snd_sof_dev *sdev) 757 { 758 } 759 760 static inline bool hda_common_check_sdw_irq(struct snd_sof_dev *sdev) 761 { 762 return false; 763 } 764 765 #endif 766 767 /* common dai driver */ 768 extern struct snd_soc_dai_driver skl_dai[]; 769 int hda_dsp_dais_suspend(struct snd_sof_dev *sdev); 770 771 /* 772 * Platform Specific HW abstraction Ops. 773 */ 774 extern struct snd_sof_dsp_ops sof_hda_common_ops; 775 776 extern struct snd_sof_dsp_ops sof_apl_ops; 777 int sof_apl_ops_init(struct snd_sof_dev *sdev); 778 extern struct snd_sof_dsp_ops sof_cnl_ops; 779 int sof_cnl_ops_init(struct snd_sof_dev *sdev); 780 extern struct snd_sof_dsp_ops sof_tgl_ops; 781 int sof_tgl_ops_init(struct snd_sof_dev *sdev); 782 extern struct snd_sof_dsp_ops sof_icl_ops; 783 int sof_icl_ops_init(struct snd_sof_dev *sdev); 784 extern struct snd_sof_dsp_ops sof_mtl_ops; 785 int sof_mtl_ops_init(struct snd_sof_dev *sdev); 786 787 extern const struct sof_intel_dsp_desc apl_chip_info; 788 extern const struct sof_intel_dsp_desc cnl_chip_info; 789 extern const struct sof_intel_dsp_desc icl_chip_info; 790 extern const struct sof_intel_dsp_desc tgl_chip_info; 791 extern const struct sof_intel_dsp_desc tglh_chip_info; 792 extern const struct sof_intel_dsp_desc ehl_chip_info; 793 extern const struct sof_intel_dsp_desc jsl_chip_info; 794 extern const struct sof_intel_dsp_desc adls_chip_info; 795 extern const struct sof_intel_dsp_desc mtl_chip_info; 796 797 /* Probes support */ 798 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_PROBES) 799 int hda_probes_register(struct snd_sof_dev *sdev); 800 void hda_probes_unregister(struct snd_sof_dev *sdev); 801 #else 802 static inline int hda_probes_register(struct snd_sof_dev *sdev) 803 { 804 return 0; 805 } 806 807 static inline void hda_probes_unregister(struct snd_sof_dev *sdev) 808 { 809 } 810 #endif /* CONFIG_SND_SOC_SOF_HDA_PROBES */ 811 812 /* SOF client registration for HDA platforms */ 813 int hda_register_clients(struct snd_sof_dev *sdev); 814 void hda_unregister_clients(struct snd_sof_dev *sdev); 815 816 /* machine driver select */ 817 struct snd_soc_acpi_mach *hda_machine_select(struct snd_sof_dev *sdev); 818 void hda_set_mach_params(struct snd_soc_acpi_mach *mach, 819 struct snd_sof_dev *sdev); 820 821 /* PCI driver selection and probe */ 822 int hda_pci_intel_probe(struct pci_dev *pci, const struct pci_device_id *pci_id); 823 824 struct snd_sof_dai; 825 struct sof_ipc_dai_config; 826 int hda_ctrl_dai_widget_setup(struct snd_soc_dapm_widget *w, unsigned int quirk_flags, 827 struct snd_sof_dai_config_data *data); 828 int hda_ctrl_dai_widget_free(struct snd_soc_dapm_widget *w, unsigned int quirk_flags, 829 struct snd_sof_dai_config_data *data); 830 831 #define SOF_HDA_POSITION_QUIRK_USE_SKYLAKE_LEGACY (0) /* previous implementation */ 832 #define SOF_HDA_POSITION_QUIRK_USE_DPIB_REGISTERS (1) /* recommended if VC0 only */ 833 #define SOF_HDA_POSITION_QUIRK_USE_DPIB_DDR_UPDATE (2) /* recommended with VC0 or VC1 */ 834 835 extern int sof_hda_position_quirk; 836 837 void hda_set_dai_drv_ops(struct snd_sof_dev *sdev, struct snd_sof_dsp_ops *ops); 838 void hda_ops_free(struct snd_sof_dev *sdev); 839 840 /* IPC4 */ 841 irqreturn_t cnl_ipc4_irq_thread(int irq, void *context); 842 int cnl_ipc4_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg); 843 irqreturn_t hda_dsp_ipc4_irq_thread(int irq, void *context); 844 int hda_dsp_ipc4_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg); 845 extern struct sdw_intel_ops sdw_callback; 846 847 #endif 848