1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ 2 /* 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * Copyright(c) 2017 Intel Corporation. All rights reserved. 7 * 8 * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com> 9 */ 10 11 #ifndef __SOF_INTEL_HDA_H 12 #define __SOF_INTEL_HDA_H 13 14 #include <linux/soundwire/sdw.h> 15 #include <linux/soundwire/sdw_intel.h> 16 #include <sound/compress_driver.h> 17 #include <sound/hda_codec.h> 18 #include <sound/hdaudio_ext.h> 19 #include "../sof-client-probes.h" 20 #include "../sof-audio.h" 21 #include "shim.h" 22 23 /* PCI registers */ 24 #define PCI_TCSEL 0x44 25 #define PCI_PGCTL PCI_TCSEL 26 #define PCI_CGCTL 0x48 27 28 /* PCI_PGCTL bits */ 29 #define PCI_PGCTL_ADSPPGD BIT(2) 30 #define PCI_PGCTL_LSRMD_MASK BIT(4) 31 32 /* PCI_CGCTL bits */ 33 #define PCI_CGCTL_MISCBDCGE_MASK BIT(6) 34 #define PCI_CGCTL_ADSPDCGE BIT(1) 35 36 /* Legacy HDA registers and bits used - widths are variable */ 37 #define SOF_HDA_GCAP 0x0 38 #define SOF_HDA_GCTL 0x8 39 /* accept unsol. response enable */ 40 #define SOF_HDA_GCTL_UNSOL BIT(8) 41 #define SOF_HDA_LLCH 0x14 42 #define SOF_HDA_INTCTL 0x20 43 #define SOF_HDA_INTSTS 0x24 44 #define SOF_HDA_WAKESTS 0x0E 45 #define SOF_HDA_WAKESTS_INT_MASK ((1 << 8) - 1) 46 #define SOF_HDA_RIRBSTS 0x5d 47 48 /* SOF_HDA_GCTL register bist */ 49 #define SOF_HDA_GCTL_RESET BIT(0) 50 51 /* SOF_HDA_INCTL regs */ 52 #define SOF_HDA_INT_GLOBAL_EN BIT(31) 53 #define SOF_HDA_INT_CTRL_EN BIT(30) 54 #define SOF_HDA_INT_ALL_STREAM 0xff 55 56 /* SOF_HDA_INTSTS regs */ 57 #define SOF_HDA_INTSTS_GIS BIT(31) 58 59 #define SOF_HDA_MAX_CAPS 10 60 #define SOF_HDA_CAP_ID_OFF 16 61 #define SOF_HDA_CAP_ID_MASK GENMASK(SOF_HDA_CAP_ID_OFF + 11,\ 62 SOF_HDA_CAP_ID_OFF) 63 #define SOF_HDA_CAP_NEXT_MASK 0xFFFF 64 65 #define SOF_HDA_GTS_CAP_ID 0x1 66 #define SOF_HDA_ML_CAP_ID 0x2 67 68 #define SOF_HDA_PP_CAP_ID 0x3 69 #define SOF_HDA_REG_PP_PPCH 0x10 70 #define SOF_HDA_REG_PP_PPCTL 0x04 71 #define SOF_HDA_REG_PP_PPSTS 0x08 72 #define SOF_HDA_PPCTL_PIE BIT(31) 73 #define SOF_HDA_PPCTL_GPROCEN BIT(30) 74 75 /*Vendor Specific Registers*/ 76 #define SOF_HDA_VS_D0I3C 0x104A 77 78 /* D0I3C Register fields */ 79 #define SOF_HDA_VS_D0I3C_CIP BIT(0) /* Command-In-Progress */ 80 #define SOF_HDA_VS_D0I3C_I3 BIT(2) /* D0i3 enable bit */ 81 82 /* DPIB entry size: 8 Bytes = 2 DWords */ 83 #define SOF_HDA_DPIB_ENTRY_SIZE 0x8 84 85 #define SOF_HDA_SPIB_CAP_ID 0x4 86 #define SOF_HDA_DRSM_CAP_ID 0x5 87 88 #define SOF_HDA_SPIB_BASE 0x08 89 #define SOF_HDA_SPIB_INTERVAL 0x08 90 #define SOF_HDA_SPIB_SPIB 0x00 91 #define SOF_HDA_SPIB_MAXFIFO 0x04 92 93 #define SOF_HDA_PPHC_BASE 0x10 94 #define SOF_HDA_PPHC_INTERVAL 0x10 95 96 #define SOF_HDA_PPLC_BASE 0x10 97 #define SOF_HDA_PPLC_MULTI 0x10 98 #define SOF_HDA_PPLC_INTERVAL 0x10 99 100 #define SOF_HDA_DRSM_BASE 0x08 101 #define SOF_HDA_DRSM_INTERVAL 0x08 102 103 /* Descriptor error interrupt */ 104 #define SOF_HDA_CL_DMA_SD_INT_DESC_ERR 0x10 105 106 /* FIFO error interrupt */ 107 #define SOF_HDA_CL_DMA_SD_INT_FIFO_ERR 0x08 108 109 /* Buffer completion interrupt */ 110 #define SOF_HDA_CL_DMA_SD_INT_COMPLETE 0x04 111 112 #define SOF_HDA_CL_DMA_SD_INT_MASK \ 113 (SOF_HDA_CL_DMA_SD_INT_DESC_ERR | \ 114 SOF_HDA_CL_DMA_SD_INT_FIFO_ERR | \ 115 SOF_HDA_CL_DMA_SD_INT_COMPLETE) 116 #define SOF_HDA_SD_CTL_DMA_START 0x02 /* Stream DMA start bit */ 117 118 /* Intel HD Audio Code Loader DMA Registers */ 119 #define SOF_HDA_ADSP_LOADER_BASE 0x80 120 #define SOF_HDA_ADSP_DPLBASE 0x70 121 #define SOF_HDA_ADSP_DPUBASE 0x74 122 #define SOF_HDA_ADSP_DPLBASE_ENABLE 0x01 123 124 /* Stream Registers */ 125 #define SOF_HDA_ADSP_REG_CL_SD_CTL 0x00 126 #define SOF_HDA_ADSP_REG_CL_SD_STS 0x03 127 #define SOF_HDA_ADSP_REG_CL_SD_LPIB 0x04 128 #define SOF_HDA_ADSP_REG_CL_SD_CBL 0x08 129 #define SOF_HDA_ADSP_REG_CL_SD_LVI 0x0C 130 #define SOF_HDA_ADSP_REG_CL_SD_FIFOW 0x0E 131 #define SOF_HDA_ADSP_REG_CL_SD_FIFOSIZE 0x10 132 #define SOF_HDA_ADSP_REG_CL_SD_FORMAT 0x12 133 #define SOF_HDA_ADSP_REG_CL_SD_FIFOL 0x14 134 #define SOF_HDA_ADSP_REG_CL_SD_BDLPL 0x18 135 #define SOF_HDA_ADSP_REG_CL_SD_BDLPU 0x1C 136 #define SOF_HDA_ADSP_SD_ENTRY_SIZE 0x20 137 138 /* CL: Software Position Based FIFO Capability Registers */ 139 #define SOF_DSP_REG_CL_SPBFIFO \ 140 (SOF_HDA_ADSP_LOADER_BASE + 0x20) 141 #define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCH 0x0 142 #define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCCTL 0x4 143 #define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPIB 0x8 144 #define SOF_HDA_ADSP_REG_CL_SPBFIFO_MAXFIFOS 0xc 145 146 /* Stream Number */ 147 #define SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT 20 148 #define SOF_HDA_CL_SD_CTL_STREAM_TAG_MASK \ 149 GENMASK(SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT + 3,\ 150 SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT) 151 152 #define HDA_DSP_HDA_BAR 0 153 #define HDA_DSP_PP_BAR 1 154 #define HDA_DSP_SPIB_BAR 2 155 #define HDA_DSP_DRSM_BAR 3 156 #define HDA_DSP_BAR 4 157 158 #define SRAM_WINDOW_OFFSET(x) (0x80000 + (x) * 0x20000) 159 160 #define HDA_DSP_MBOX_OFFSET SRAM_WINDOW_OFFSET(0) 161 162 #define HDA_DSP_PANIC_OFFSET(x) \ 163 (((x) & 0xFFFFFF) + HDA_DSP_MBOX_OFFSET) 164 165 /* SRAM window 0 FW "registers" */ 166 #define HDA_DSP_SRAM_REG_ROM_STATUS (HDA_DSP_MBOX_OFFSET + 0x0) 167 #define HDA_DSP_SRAM_REG_ROM_ERROR (HDA_DSP_MBOX_OFFSET + 0x4) 168 /* FW and ROM share offset 4 */ 169 #define HDA_DSP_SRAM_REG_FW_STATUS (HDA_DSP_MBOX_OFFSET + 0x4) 170 #define HDA_DSP_SRAM_REG_FW_TRACEP (HDA_DSP_MBOX_OFFSET + 0x8) 171 #define HDA_DSP_SRAM_REG_FW_END (HDA_DSP_MBOX_OFFSET + 0xc) 172 173 #define HDA_DSP_MBOX_UPLINK_OFFSET 0x81000 174 175 #define HDA_DSP_STREAM_RESET_TIMEOUT 300 176 /* 177 * Timeout in us, for setting the stream RUN bit, during 178 * start/stop the stream. The timeout expires if new RUN bit 179 * value cannot be read back within the specified time. 180 */ 181 #define HDA_DSP_STREAM_RUN_TIMEOUT 300 182 183 #define HDA_DSP_SPIB_ENABLE 1 184 #define HDA_DSP_SPIB_DISABLE 0 185 186 #define SOF_HDA_MAX_BUFFER_SIZE (32 * PAGE_SIZE) 187 188 #define HDA_DSP_STACK_DUMP_SIZE 32 189 190 /* ROM status/error values */ 191 #define HDA_DSP_ROM_STS_MASK GENMASK(23, 0) 192 #define HDA_DSP_ROM_INIT 0x1 193 #define HDA_DSP_ROM_FW_MANIFEST_LOADED 0x3 194 #define HDA_DSP_ROM_FW_FW_LOADED 0x4 195 #define HDA_DSP_ROM_FW_ENTERED 0x5 196 #define HDA_DSP_ROM_RFW_START 0xf 197 #define HDA_DSP_ROM_CSE_ERROR 40 198 #define HDA_DSP_ROM_CSE_WRONG_RESPONSE 41 199 #define HDA_DSP_ROM_IMR_TO_SMALL 42 200 #define HDA_DSP_ROM_BASE_FW_NOT_FOUND 43 201 #define HDA_DSP_ROM_CSE_VALIDATION_FAILED 44 202 #define HDA_DSP_ROM_IPC_FATAL_ERROR 45 203 #define HDA_DSP_ROM_L2_CACHE_ERROR 46 204 #define HDA_DSP_ROM_LOAD_OFFSET_TO_SMALL 47 205 #define HDA_DSP_ROM_API_PTR_INVALID 50 206 #define HDA_DSP_ROM_BASEFW_INCOMPAT 51 207 #define HDA_DSP_ROM_UNHANDLED_INTERRUPT 0xBEE00000 208 #define HDA_DSP_ROM_MEMORY_HOLE_ECC 0xECC00000 209 #define HDA_DSP_ROM_KERNEL_EXCEPTION 0xCAFE0000 210 #define HDA_DSP_ROM_USER_EXCEPTION 0xBEEF0000 211 #define HDA_DSP_ROM_UNEXPECTED_RESET 0xDECAF000 212 #define HDA_DSP_ROM_NULL_FW_ENTRY 0x4c4c4e55 213 #define HDA_DSP_IPC_PURGE_FW 0x01004000 214 215 /* various timeout values */ 216 #define HDA_DSP_PU_TIMEOUT 50 217 #define HDA_DSP_PD_TIMEOUT 50 218 #define HDA_DSP_RESET_TIMEOUT_US 50000 219 #define HDA_DSP_BASEFW_TIMEOUT_US 3000000 220 #define HDA_DSP_INIT_TIMEOUT_US 500000 221 #define HDA_DSP_CTRL_RESET_TIMEOUT 100 222 #define HDA_DSP_WAIT_TIMEOUT 500 /* 500 msec */ 223 #define HDA_DSP_REG_POLL_INTERVAL_US 500 /* 0.5 msec */ 224 #define HDA_DSP_REG_POLL_RETRY_COUNT 50 225 226 #define HDA_DSP_ADSPIC_IPC 1 227 #define HDA_DSP_ADSPIS_IPC 1 228 229 /* Intel HD Audio General DSP Registers */ 230 #define HDA_DSP_GEN_BASE 0x0 231 #define HDA_DSP_REG_ADSPCS (HDA_DSP_GEN_BASE + 0x04) 232 #define HDA_DSP_REG_ADSPIC (HDA_DSP_GEN_BASE + 0x08) 233 #define HDA_DSP_REG_ADSPIS (HDA_DSP_GEN_BASE + 0x0C) 234 #define HDA_DSP_REG_ADSPIC2 (HDA_DSP_GEN_BASE + 0x10) 235 #define HDA_DSP_REG_ADSPIS2 (HDA_DSP_GEN_BASE + 0x14) 236 237 #define HDA_DSP_REG_ADSPIS2_SNDW BIT(5) 238 239 /* Intel HD Audio Inter-Processor Communication Registers */ 240 #define HDA_DSP_IPC_BASE 0x40 241 #define HDA_DSP_REG_HIPCT (HDA_DSP_IPC_BASE + 0x00) 242 #define HDA_DSP_REG_HIPCTE (HDA_DSP_IPC_BASE + 0x04) 243 #define HDA_DSP_REG_HIPCI (HDA_DSP_IPC_BASE + 0x08) 244 #define HDA_DSP_REG_HIPCIE (HDA_DSP_IPC_BASE + 0x0C) 245 #define HDA_DSP_REG_HIPCCTL (HDA_DSP_IPC_BASE + 0x10) 246 247 /* Intel Vendor Specific Registers */ 248 #define HDA_VS_INTEL_EM2 0x1030 249 #define HDA_VS_INTEL_EM2_L1SEN BIT(13) 250 #define HDA_VS_INTEL_LTRP_GB_MASK 0x3F 251 252 /* HIPCI */ 253 #define HDA_DSP_REG_HIPCI_BUSY BIT(31) 254 #define HDA_DSP_REG_HIPCI_MSG_MASK 0x7FFFFFFF 255 256 /* HIPCIE */ 257 #define HDA_DSP_REG_HIPCIE_DONE BIT(30) 258 #define HDA_DSP_REG_HIPCIE_MSG_MASK 0x3FFFFFFF 259 260 /* HIPCCTL */ 261 #define HDA_DSP_REG_HIPCCTL_DONE BIT(1) 262 #define HDA_DSP_REG_HIPCCTL_BUSY BIT(0) 263 264 /* HIPCT */ 265 #define HDA_DSP_REG_HIPCT_BUSY BIT(31) 266 #define HDA_DSP_REG_HIPCT_MSG_MASK 0x7FFFFFFF 267 268 /* HIPCTE */ 269 #define HDA_DSP_REG_HIPCTE_MSG_MASK 0x3FFFFFFF 270 271 #define HDA_DSP_ADSPIC_CL_DMA 0x2 272 #define HDA_DSP_ADSPIS_CL_DMA 0x2 273 274 /* Delay before scheduling D0i3 entry */ 275 #define BXT_D0I3_DELAY 5000 276 277 #define FW_CL_STREAM_NUMBER 0x1 278 #define HDA_FW_BOOT_ATTEMPTS 3 279 280 /* ADSPCS - Audio DSP Control & Status */ 281 282 /* 283 * Core Reset - asserted high 284 * CRST Mask for a given core mask pattern, cm 285 */ 286 #define HDA_DSP_ADSPCS_CRST_SHIFT 0 287 #define HDA_DSP_ADSPCS_CRST_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CRST_SHIFT) 288 289 /* 290 * Core run/stall - when set to '1' core is stalled 291 * CSTALL Mask for a given core mask pattern, cm 292 */ 293 #define HDA_DSP_ADSPCS_CSTALL_SHIFT 8 294 #define HDA_DSP_ADSPCS_CSTALL_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CSTALL_SHIFT) 295 296 /* 297 * Set Power Active - when set to '1' turn cores on 298 * SPA Mask for a given core mask pattern, cm 299 */ 300 #define HDA_DSP_ADSPCS_SPA_SHIFT 16 301 #define HDA_DSP_ADSPCS_SPA_MASK(cm) ((cm) << HDA_DSP_ADSPCS_SPA_SHIFT) 302 303 /* 304 * Current Power Active - power status of cores, set by hardware 305 * CPA Mask for a given core mask pattern, cm 306 */ 307 #define HDA_DSP_ADSPCS_CPA_SHIFT 24 308 #define HDA_DSP_ADSPCS_CPA_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CPA_SHIFT) 309 310 /* 311 * Mask for a given number of cores 312 * nc = number of supported cores 313 */ 314 #define SOF_DSP_CORES_MASK(nc) GENMASK(((nc) - 1), 0) 315 316 /* Intel HD Audio Inter-Processor Communication Registers for Cannonlake*/ 317 #define CNL_DSP_IPC_BASE 0xc0 318 #define CNL_DSP_REG_HIPCTDR (CNL_DSP_IPC_BASE + 0x00) 319 #define CNL_DSP_REG_HIPCTDA (CNL_DSP_IPC_BASE + 0x04) 320 #define CNL_DSP_REG_HIPCTDD (CNL_DSP_IPC_BASE + 0x08) 321 #define CNL_DSP_REG_HIPCIDR (CNL_DSP_IPC_BASE + 0x10) 322 #define CNL_DSP_REG_HIPCIDA (CNL_DSP_IPC_BASE + 0x14) 323 #define CNL_DSP_REG_HIPCIDD (CNL_DSP_IPC_BASE + 0x18) 324 #define CNL_DSP_REG_HIPCCTL (CNL_DSP_IPC_BASE + 0x28) 325 326 /* HIPCI */ 327 #define CNL_DSP_REG_HIPCIDR_BUSY BIT(31) 328 #define CNL_DSP_REG_HIPCIDR_MSG_MASK 0x7FFFFFFF 329 330 /* HIPCIE */ 331 #define CNL_DSP_REG_HIPCIDA_DONE BIT(31) 332 #define CNL_DSP_REG_HIPCIDA_MSG_MASK 0x7FFFFFFF 333 334 /* HIPCCTL */ 335 #define CNL_DSP_REG_HIPCCTL_DONE BIT(1) 336 #define CNL_DSP_REG_HIPCCTL_BUSY BIT(0) 337 338 /* HIPCT */ 339 #define CNL_DSP_REG_HIPCTDR_BUSY BIT(31) 340 #define CNL_DSP_REG_HIPCTDR_MSG_MASK 0x7FFFFFFF 341 342 /* HIPCTDA */ 343 #define CNL_DSP_REG_HIPCTDA_DONE BIT(31) 344 #define CNL_DSP_REG_HIPCTDA_MSG_MASK 0x7FFFFFFF 345 346 /* HIPCTDD */ 347 #define CNL_DSP_REG_HIPCTDD_MSG_MASK 0x7FFFFFFF 348 349 /* BDL */ 350 #define HDA_DSP_BDL_SIZE 4096 351 #define HDA_DSP_MAX_BDL_ENTRIES \ 352 (HDA_DSP_BDL_SIZE / sizeof(struct sof_intel_dsp_bdl)) 353 354 /* Number of DAIs */ 355 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) 356 #define SOF_SKL_NUM_DAIS 15 357 #else 358 #define SOF_SKL_NUM_DAIS 8 359 #endif 360 361 /* Intel HD Audio SRAM Window 0*/ 362 #define HDA_ADSP_SRAM0_BASE_SKL 0x8000 363 364 /* Firmware status window */ 365 #define HDA_ADSP_FW_STATUS_SKL HDA_ADSP_SRAM0_BASE_SKL 366 #define HDA_ADSP_ERROR_CODE_SKL (HDA_ADSP_FW_STATUS_SKL + 0x4) 367 368 /* Host Device Memory Space */ 369 #define APL_SSP_BASE_OFFSET 0x2000 370 #define CNL_SSP_BASE_OFFSET 0x10000 371 372 /* Host Device Memory Size of a Single SSP */ 373 #define SSP_DEV_MEM_SIZE 0x1000 374 375 /* SSP Count of the Platform */ 376 #define APL_SSP_COUNT 6 377 #define CNL_SSP_COUNT 3 378 #define ICL_SSP_COUNT 6 379 380 /* SSP Registers */ 381 #define SSP_SSC1_OFFSET 0x4 382 #define SSP_SET_SCLK_CONSUMER BIT(25) 383 #define SSP_SET_SFRM_CONSUMER BIT(24) 384 #define SSP_SET_CBP_CFP (SSP_SET_SCLK_CONSUMER | SSP_SET_SFRM_CONSUMER) 385 386 #define HDA_IDISP_ADDR 2 387 #define HDA_IDISP_CODEC(x) ((x) & BIT(HDA_IDISP_ADDR)) 388 389 struct sof_intel_dsp_bdl { 390 __le32 addr_l; 391 __le32 addr_h; 392 __le32 size; 393 __le32 ioc; 394 } __attribute((packed)); 395 396 #define SOF_HDA_PLAYBACK_STREAMS 16 397 #define SOF_HDA_CAPTURE_STREAMS 16 398 #define SOF_HDA_PLAYBACK 0 399 #define SOF_HDA_CAPTURE 1 400 401 /* stream flags */ 402 #define SOF_HDA_STREAM_DMI_L1_COMPATIBLE 1 403 404 /* 405 * Time in ms for opportunistic D0I3 entry delay. 406 * This has been deliberately chosen to be long to avoid race conditions. 407 * Could be optimized in future. 408 */ 409 #define SOF_HDA_D0I3_WORK_DELAY_MS 5000 410 411 /* HDA DSP D0 substate */ 412 enum sof_hda_D0_substate { 413 SOF_HDA_DSP_PM_D0I0, /* default D0 substate */ 414 SOF_HDA_DSP_PM_D0I3, /* low power D0 substate */ 415 }; 416 417 /* represents DSP HDA controller frontend - i.e. host facing control */ 418 struct sof_intel_hda_dev { 419 int boot_iteration; 420 421 struct hda_bus hbus; 422 423 /* hw config */ 424 const struct sof_intel_dsp_desc *desc; 425 426 /* trace */ 427 struct hdac_ext_stream *dtrace_stream; 428 429 /* if position update IPC needed */ 430 u32 no_ipc_position; 431 432 /* the maximum number of streams (playback + capture) supported */ 433 u32 stream_max; 434 435 /* PM related */ 436 bool l1_support_changed;/* during suspend, is L1SEN changed or not */ 437 438 /* DMIC device */ 439 struct platform_device *dmic_dev; 440 441 /* delayed work to enter D0I3 opportunistically */ 442 struct delayed_work d0i3_work; 443 444 /* ACPI information stored between scan and probe steps */ 445 struct sdw_intel_acpi_info info; 446 447 /* sdw context allocated by SoundWire driver */ 448 struct sdw_intel_ctx *sdw; 449 450 /* FW clock config, 0:HPRO, 1:LPRO */ 451 bool clk_config_lpro; 452 }; 453 454 static inline struct hdac_bus *sof_to_bus(struct snd_sof_dev *s) 455 { 456 struct sof_intel_hda_dev *hda = s->pdata->hw_pdata; 457 458 return &hda->hbus.core; 459 } 460 461 static inline struct hda_bus *sof_to_hbus(struct snd_sof_dev *s) 462 { 463 struct sof_intel_hda_dev *hda = s->pdata->hw_pdata; 464 465 return &hda->hbus; 466 } 467 468 struct sof_intel_hda_stream { 469 struct snd_sof_dev *sdev; 470 struct hdac_ext_stream hext_stream; 471 struct sof_intel_stream sof_intel_stream; 472 int host_reserved; /* reserve host DMA channel */ 473 u32 flags; 474 }; 475 476 #define hstream_to_sof_hda_stream(hstream) \ 477 container_of(hstream, struct sof_intel_hda_stream, hext_stream) 478 479 #define bus_to_sof_hda(bus) \ 480 container_of(bus, struct sof_intel_hda_dev, hbus.core) 481 482 #define SOF_STREAM_SD_OFFSET(s) \ 483 (SOF_HDA_ADSP_SD_ENTRY_SIZE * ((s)->index) \ 484 + SOF_HDA_ADSP_LOADER_BASE) 485 486 #define SOF_STREAM_SD_OFFSET_CRST 0x1 487 488 /* 489 * DSP Core services. 490 */ 491 int hda_dsp_probe(struct snd_sof_dev *sdev); 492 int hda_dsp_remove(struct snd_sof_dev *sdev); 493 int hda_dsp_core_run(struct snd_sof_dev *sdev, unsigned int core_mask); 494 int hda_dsp_enable_core(struct snd_sof_dev *sdev, unsigned int core_mask); 495 int hda_dsp_core_reset_power_down(struct snd_sof_dev *sdev, 496 unsigned int core_mask); 497 int hda_dsp_core_get(struct snd_sof_dev *sdev, int core); 498 void hda_dsp_ipc_int_enable(struct snd_sof_dev *sdev); 499 void hda_dsp_ipc_int_disable(struct snd_sof_dev *sdev); 500 501 int hda_dsp_set_power_state(struct snd_sof_dev *sdev, 502 const struct sof_dsp_power_state *target_state); 503 504 int hda_dsp_suspend(struct snd_sof_dev *sdev, u32 target_state); 505 int hda_dsp_resume(struct snd_sof_dev *sdev); 506 int hda_dsp_runtime_suspend(struct snd_sof_dev *sdev); 507 int hda_dsp_runtime_resume(struct snd_sof_dev *sdev); 508 int hda_dsp_runtime_idle(struct snd_sof_dev *sdev); 509 int hda_dsp_shutdown(struct snd_sof_dev *sdev); 510 int hda_dsp_set_hw_params_upon_resume(struct snd_sof_dev *sdev); 511 void hda_dsp_dump(struct snd_sof_dev *sdev, u32 flags); 512 void hda_ipc_dump(struct snd_sof_dev *sdev); 513 void hda_ipc_irq_dump(struct snd_sof_dev *sdev); 514 void hda_dsp_d0i3_work(struct work_struct *work); 515 516 /* 517 * DSP PCM Operations. 518 */ 519 u32 hda_dsp_get_mult_div(struct snd_sof_dev *sdev, int rate); 520 u32 hda_dsp_get_bits(struct snd_sof_dev *sdev, int sample_bits); 521 int hda_dsp_pcm_open(struct snd_sof_dev *sdev, 522 struct snd_pcm_substream *substream); 523 int hda_dsp_pcm_close(struct snd_sof_dev *sdev, 524 struct snd_pcm_substream *substream); 525 int hda_dsp_pcm_hw_params(struct snd_sof_dev *sdev, 526 struct snd_pcm_substream *substream, 527 struct snd_pcm_hw_params *params, 528 struct snd_sof_platform_stream_params *platform_params); 529 int hda_dsp_stream_hw_free(struct snd_sof_dev *sdev, 530 struct snd_pcm_substream *substream); 531 int hda_dsp_pcm_trigger(struct snd_sof_dev *sdev, 532 struct snd_pcm_substream *substream, int cmd); 533 snd_pcm_uframes_t hda_dsp_pcm_pointer(struct snd_sof_dev *sdev, 534 struct snd_pcm_substream *substream); 535 int hda_dsp_pcm_ack(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream); 536 537 /* 538 * DSP Stream Operations. 539 */ 540 541 int hda_dsp_stream_init(struct snd_sof_dev *sdev); 542 void hda_dsp_stream_free(struct snd_sof_dev *sdev); 543 int hda_dsp_stream_hw_params(struct snd_sof_dev *sdev, 544 struct hdac_ext_stream *hext_stream, 545 struct snd_dma_buffer *dmab, 546 struct snd_pcm_hw_params *params); 547 int hda_dsp_iccmax_stream_hw_params(struct snd_sof_dev *sdev, 548 struct hdac_ext_stream *hext_stream, 549 struct snd_dma_buffer *dmab, 550 struct snd_pcm_hw_params *params); 551 int hda_dsp_stream_trigger(struct snd_sof_dev *sdev, 552 struct hdac_ext_stream *hext_stream, int cmd); 553 irqreturn_t hda_dsp_stream_threaded_handler(int irq, void *context); 554 int hda_dsp_stream_setup_bdl(struct snd_sof_dev *sdev, 555 struct snd_dma_buffer *dmab, 556 struct hdac_stream *hstream); 557 bool hda_dsp_check_ipc_irq(struct snd_sof_dev *sdev); 558 bool hda_dsp_check_stream_irq(struct snd_sof_dev *sdev); 559 560 struct hdac_ext_stream * 561 hda_dsp_stream_get(struct snd_sof_dev *sdev, int direction, u32 flags); 562 int hda_dsp_stream_put(struct snd_sof_dev *sdev, int direction, int stream_tag); 563 int hda_dsp_stream_spib_config(struct snd_sof_dev *sdev, 564 struct hdac_ext_stream *hext_stream, 565 int enable, u32 size); 566 567 int hda_ipc_msg_data(struct snd_sof_dev *sdev, 568 struct snd_pcm_substream *substream, 569 void *p, size_t sz); 570 int hda_set_stream_data_offset(struct snd_sof_dev *sdev, 571 struct snd_pcm_substream *substream, 572 size_t posn_offset); 573 574 /* 575 * DSP IPC Operations. 576 */ 577 int hda_dsp_ipc_send_msg(struct snd_sof_dev *sdev, 578 struct snd_sof_ipc_msg *msg); 579 void hda_dsp_ipc_get_reply(struct snd_sof_dev *sdev); 580 int hda_dsp_ipc_get_mailbox_offset(struct snd_sof_dev *sdev); 581 int hda_dsp_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id); 582 583 irqreturn_t hda_dsp_ipc_irq_thread(int irq, void *context); 584 int hda_dsp_ipc_cmd_done(struct snd_sof_dev *sdev, int dir); 585 586 /* 587 * DSP Code loader. 588 */ 589 int hda_dsp_cl_boot_firmware(struct snd_sof_dev *sdev); 590 int hda_dsp_cl_boot_firmware_iccmax(struct snd_sof_dev *sdev); 591 592 /* pre and post fw run ops */ 593 int hda_dsp_pre_fw_run(struct snd_sof_dev *sdev); 594 int hda_dsp_post_fw_run(struct snd_sof_dev *sdev); 595 596 /* parse platform specific ext manifest ops */ 597 int hda_dsp_ext_man_get_cavs_config_data(struct snd_sof_dev *sdev, 598 const struct sof_ext_man_elem_header *hdr); 599 600 /* 601 * HDA Controller Operations. 602 */ 603 int hda_dsp_ctrl_get_caps(struct snd_sof_dev *sdev); 604 void hda_dsp_ctrl_ppcap_enable(struct snd_sof_dev *sdev, bool enable); 605 void hda_dsp_ctrl_ppcap_int_enable(struct snd_sof_dev *sdev, bool enable); 606 int hda_dsp_ctrl_link_reset(struct snd_sof_dev *sdev, bool reset); 607 void hda_dsp_ctrl_misc_clock_gating(struct snd_sof_dev *sdev, bool enable); 608 int hda_dsp_ctrl_clock_power_gating(struct snd_sof_dev *sdev, bool enable); 609 int hda_dsp_ctrl_init_chip(struct snd_sof_dev *sdev, bool full_reset); 610 void hda_dsp_ctrl_stop_chip(struct snd_sof_dev *sdev); 611 /* 612 * HDA bus operations. 613 */ 614 void sof_hda_bus_init(struct hdac_bus *bus, struct device *dev); 615 616 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) 617 /* 618 * HDA Codec operations. 619 */ 620 void hda_codec_probe_bus(struct snd_sof_dev *sdev, 621 bool hda_codec_use_common_hdmi); 622 void hda_codec_jack_wake_enable(struct snd_sof_dev *sdev, bool enable); 623 void hda_codec_jack_check(struct snd_sof_dev *sdev); 624 625 #endif /* CONFIG_SND_SOC_SOF_HDA */ 626 627 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) && \ 628 (IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI) || \ 629 IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) 630 631 void hda_codec_i915_display_power(struct snd_sof_dev *sdev, bool enable); 632 int hda_codec_i915_init(struct snd_sof_dev *sdev); 633 int hda_codec_i915_exit(struct snd_sof_dev *sdev); 634 635 #else 636 637 static inline void hda_codec_i915_display_power(struct snd_sof_dev *sdev, 638 bool enable) { } 639 static inline int hda_codec_i915_init(struct snd_sof_dev *sdev) { return 0; } 640 static inline int hda_codec_i915_exit(struct snd_sof_dev *sdev) { return 0; } 641 642 #endif 643 644 /* 645 * Trace Control. 646 */ 647 int hda_dsp_trace_init(struct snd_sof_dev *sdev, 648 struct sof_ipc_dma_trace_params_ext *dtrace_params); 649 int hda_dsp_trace_release(struct snd_sof_dev *sdev); 650 int hda_dsp_trace_trigger(struct snd_sof_dev *sdev, int cmd); 651 652 /* 653 * SoundWire support 654 */ 655 #if IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE) 656 657 int hda_sdw_startup(struct snd_sof_dev *sdev); 658 void hda_sdw_int_enable(struct snd_sof_dev *sdev, bool enable); 659 void hda_sdw_process_wakeen(struct snd_sof_dev *sdev); 660 bool hda_common_check_sdw_irq(struct snd_sof_dev *sdev); 661 662 #else 663 664 static inline int hda_sdw_startup(struct snd_sof_dev *sdev) 665 { 666 return 0; 667 } 668 669 static inline void hda_sdw_int_enable(struct snd_sof_dev *sdev, bool enable) 670 { 671 } 672 673 static inline void hda_sdw_process_wakeen(struct snd_sof_dev *sdev) 674 { 675 } 676 677 static inline bool hda_common_check_sdw_irq(struct snd_sof_dev *sdev) 678 { 679 return false; 680 } 681 682 #endif 683 684 /* common dai driver */ 685 extern struct snd_soc_dai_driver skl_dai[]; 686 687 /* 688 * Platform Specific HW abstraction Ops. 689 */ 690 extern const struct snd_sof_dsp_ops sof_apl_ops; 691 extern const struct snd_sof_dsp_ops sof_cnl_ops; 692 extern const struct snd_sof_dsp_ops sof_tgl_ops; 693 extern const struct snd_sof_dsp_ops sof_icl_ops; 694 695 extern const struct sof_intel_dsp_desc apl_chip_info; 696 extern const struct sof_intel_dsp_desc cnl_chip_info; 697 extern const struct sof_intel_dsp_desc skl_chip_info; 698 extern const struct sof_intel_dsp_desc icl_chip_info; 699 extern const struct sof_intel_dsp_desc tgl_chip_info; 700 extern const struct sof_intel_dsp_desc tglh_chip_info; 701 extern const struct sof_intel_dsp_desc ehl_chip_info; 702 extern const struct sof_intel_dsp_desc jsl_chip_info; 703 extern const struct sof_intel_dsp_desc adls_chip_info; 704 705 /* Probes support */ 706 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_PROBES) 707 int hda_probes_register(struct snd_sof_dev *sdev); 708 void hda_probes_unregister(struct snd_sof_dev *sdev); 709 #else 710 static inline int hda_probes_register(struct snd_sof_dev *sdev) 711 { 712 return 0; 713 } 714 715 static inline void hda_probes_unregister(struct snd_sof_dev *sdev) 716 { 717 } 718 #endif /* CONFIG_SND_SOC_SOF_HDA_PROBES */ 719 720 /* SOF client registration for HDA platforms */ 721 int hda_register_clients(struct snd_sof_dev *sdev); 722 void hda_unregister_clients(struct snd_sof_dev *sdev); 723 724 /* machine driver select */ 725 struct snd_soc_acpi_mach *hda_machine_select(struct snd_sof_dev *sdev); 726 void hda_set_mach_params(struct snd_soc_acpi_mach *mach, 727 struct snd_sof_dev *sdev); 728 729 /* PCI driver selection and probe */ 730 int hda_pci_intel_probe(struct pci_dev *pci, const struct pci_device_id *pci_id); 731 732 struct snd_sof_dai; 733 struct sof_ipc_dai_config; 734 int hda_ctrl_dai_widget_setup(struct snd_soc_dapm_widget *w, unsigned int quirk_flags, 735 struct snd_sof_dai_config_data *data); 736 int hda_ctrl_dai_widget_free(struct snd_soc_dapm_widget *w, unsigned int quirk_flags, 737 struct snd_sof_dai_config_data *data); 738 739 #define SOF_HDA_POSITION_QUIRK_USE_SKYLAKE_LEGACY (0) /* previous implementation */ 740 #define SOF_HDA_POSITION_QUIRK_USE_DPIB_REGISTERS (1) /* recommended if VC0 only */ 741 #define SOF_HDA_POSITION_QUIRK_USE_DPIB_DDR_UPDATE (2) /* recommended with VC0 or VC1 */ 742 743 extern int sof_hda_position_quirk; 744 745 #endif 746