1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */ 2 /* 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * Copyright(c) 2017 Intel Corporation. All rights reserved. 7 * 8 * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com> 9 */ 10 11 #ifndef __SOF_INTEL_HDA_H 12 #define __SOF_INTEL_HDA_H 13 14 #include <sound/compress_driver.h> 15 #include <sound/hda_codec.h> 16 #include <sound/hdaudio_ext.h> 17 #include "shim.h" 18 19 /* PCI registers */ 20 #define PCI_TCSEL 0x44 21 #define PCI_PGCTL PCI_TCSEL 22 #define PCI_CGCTL 0x48 23 24 /* PCI_PGCTL bits */ 25 #define PCI_PGCTL_ADSPPGD BIT(2) 26 #define PCI_PGCTL_LSRMD_MASK BIT(4) 27 28 /* PCI_CGCTL bits */ 29 #define PCI_CGCTL_MISCBDCGE_MASK BIT(6) 30 #define PCI_CGCTL_ADSPDCGE BIT(1) 31 32 /* Legacy HDA registers and bits used - widths are variable */ 33 #define SOF_HDA_GCAP 0x0 34 #define SOF_HDA_GCTL 0x8 35 /* accept unsol. response enable */ 36 #define SOF_HDA_GCTL_UNSOL BIT(8) 37 #define SOF_HDA_LLCH 0x14 38 #define SOF_HDA_INTCTL 0x20 39 #define SOF_HDA_INTSTS 0x24 40 #define SOF_HDA_WAKESTS 0x0E 41 #define SOF_HDA_WAKESTS_INT_MASK ((1 << 8) - 1) 42 #define SOF_HDA_RIRBSTS 0x5d 43 44 /* SOF_HDA_GCTL register bist */ 45 #define SOF_HDA_GCTL_RESET BIT(0) 46 47 /* SOF_HDA_INCTL regs */ 48 #define SOF_HDA_INT_GLOBAL_EN BIT(31) 49 #define SOF_HDA_INT_CTRL_EN BIT(30) 50 #define SOF_HDA_INT_ALL_STREAM 0xff 51 52 /* SOF_HDA_INTSTS regs */ 53 #define SOF_HDA_INTSTS_GIS BIT(31) 54 55 #define SOF_HDA_MAX_CAPS 10 56 #define SOF_HDA_CAP_ID_OFF 16 57 #define SOF_HDA_CAP_ID_MASK GENMASK(SOF_HDA_CAP_ID_OFF + 11,\ 58 SOF_HDA_CAP_ID_OFF) 59 #define SOF_HDA_CAP_NEXT_MASK 0xFFFF 60 61 #define SOF_HDA_GTS_CAP_ID 0x1 62 #define SOF_HDA_ML_CAP_ID 0x2 63 64 #define SOF_HDA_PP_CAP_ID 0x3 65 #define SOF_HDA_REG_PP_PPCH 0x10 66 #define SOF_HDA_REG_PP_PPCTL 0x04 67 #define SOF_HDA_REG_PP_PPSTS 0x08 68 #define SOF_HDA_PPCTL_PIE BIT(31) 69 #define SOF_HDA_PPCTL_GPROCEN BIT(30) 70 71 /*Vendor Specific Registers*/ 72 #define SOF_HDA_VS_D0I3C 0x104A 73 74 /* D0I3C Register fields */ 75 #define SOF_HDA_VS_D0I3C_CIP BIT(0) /* Command-In-Progress */ 76 #define SOF_HDA_VS_D0I3C_I3 BIT(2) /* D0i3 enable bit */ 77 78 /* DPIB entry size: 8 Bytes = 2 DWords */ 79 #define SOF_HDA_DPIB_ENTRY_SIZE 0x8 80 81 #define SOF_HDA_SPIB_CAP_ID 0x4 82 #define SOF_HDA_DRSM_CAP_ID 0x5 83 84 #define SOF_HDA_SPIB_BASE 0x08 85 #define SOF_HDA_SPIB_INTERVAL 0x08 86 #define SOF_HDA_SPIB_SPIB 0x00 87 #define SOF_HDA_SPIB_MAXFIFO 0x04 88 89 #define SOF_HDA_PPHC_BASE 0x10 90 #define SOF_HDA_PPHC_INTERVAL 0x10 91 92 #define SOF_HDA_PPLC_BASE 0x10 93 #define SOF_HDA_PPLC_MULTI 0x10 94 #define SOF_HDA_PPLC_INTERVAL 0x10 95 96 #define SOF_HDA_DRSM_BASE 0x08 97 #define SOF_HDA_DRSM_INTERVAL 0x08 98 99 /* Descriptor error interrupt */ 100 #define SOF_HDA_CL_DMA_SD_INT_DESC_ERR 0x10 101 102 /* FIFO error interrupt */ 103 #define SOF_HDA_CL_DMA_SD_INT_FIFO_ERR 0x08 104 105 /* Buffer completion interrupt */ 106 #define SOF_HDA_CL_DMA_SD_INT_COMPLETE 0x04 107 108 #define SOF_HDA_CL_DMA_SD_INT_MASK \ 109 (SOF_HDA_CL_DMA_SD_INT_DESC_ERR | \ 110 SOF_HDA_CL_DMA_SD_INT_FIFO_ERR | \ 111 SOF_HDA_CL_DMA_SD_INT_COMPLETE) 112 #define SOF_HDA_SD_CTL_DMA_START 0x02 /* Stream DMA start bit */ 113 114 /* Intel HD Audio Code Loader DMA Registers */ 115 #define SOF_HDA_ADSP_LOADER_BASE 0x80 116 #define SOF_HDA_ADSP_DPLBASE 0x70 117 #define SOF_HDA_ADSP_DPUBASE 0x74 118 #define SOF_HDA_ADSP_DPLBASE_ENABLE 0x01 119 120 /* Stream Registers */ 121 #define SOF_HDA_ADSP_REG_CL_SD_CTL 0x00 122 #define SOF_HDA_ADSP_REG_CL_SD_STS 0x03 123 #define SOF_HDA_ADSP_REG_CL_SD_LPIB 0x04 124 #define SOF_HDA_ADSP_REG_CL_SD_CBL 0x08 125 #define SOF_HDA_ADSP_REG_CL_SD_LVI 0x0C 126 #define SOF_HDA_ADSP_REG_CL_SD_FIFOW 0x0E 127 #define SOF_HDA_ADSP_REG_CL_SD_FIFOSIZE 0x10 128 #define SOF_HDA_ADSP_REG_CL_SD_FORMAT 0x12 129 #define SOF_HDA_ADSP_REG_CL_SD_FIFOL 0x14 130 #define SOF_HDA_ADSP_REG_CL_SD_BDLPL 0x18 131 #define SOF_HDA_ADSP_REG_CL_SD_BDLPU 0x1C 132 #define SOF_HDA_ADSP_SD_ENTRY_SIZE 0x20 133 134 /* CL: Software Position Based FIFO Capability Registers */ 135 #define SOF_DSP_REG_CL_SPBFIFO \ 136 (SOF_HDA_ADSP_LOADER_BASE + 0x20) 137 #define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCH 0x0 138 #define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCCTL 0x4 139 #define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPIB 0x8 140 #define SOF_HDA_ADSP_REG_CL_SPBFIFO_MAXFIFOS 0xc 141 142 /* Stream Number */ 143 #define SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT 20 144 #define SOF_HDA_CL_SD_CTL_STREAM_TAG_MASK \ 145 GENMASK(SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT + 3,\ 146 SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT) 147 148 #define HDA_DSP_HDA_BAR 0 149 #define HDA_DSP_PP_BAR 1 150 #define HDA_DSP_SPIB_BAR 2 151 #define HDA_DSP_DRSM_BAR 3 152 #define HDA_DSP_BAR 4 153 154 #define SRAM_WINDOW_OFFSET(x) (0x80000 + (x) * 0x20000) 155 156 #define HDA_DSP_MBOX_OFFSET SRAM_WINDOW_OFFSET(0) 157 158 #define HDA_DSP_PANIC_OFFSET(x) \ 159 (((x) & 0xFFFFFF) + HDA_DSP_MBOX_OFFSET) 160 161 /* SRAM window 0 FW "registers" */ 162 #define HDA_DSP_SRAM_REG_ROM_STATUS (HDA_DSP_MBOX_OFFSET + 0x0) 163 #define HDA_DSP_SRAM_REG_ROM_ERROR (HDA_DSP_MBOX_OFFSET + 0x4) 164 /* FW and ROM share offset 4 */ 165 #define HDA_DSP_SRAM_REG_FW_STATUS (HDA_DSP_MBOX_OFFSET + 0x4) 166 #define HDA_DSP_SRAM_REG_FW_TRACEP (HDA_DSP_MBOX_OFFSET + 0x8) 167 #define HDA_DSP_SRAM_REG_FW_END (HDA_DSP_MBOX_OFFSET + 0xc) 168 169 #define HDA_DSP_MBOX_UPLINK_OFFSET 0x81000 170 171 #define HDA_DSP_STREAM_RESET_TIMEOUT 300 172 /* 173 * Timeout in us, for setting the stream RUN bit, during 174 * start/stop the stream. The timeout expires if new RUN bit 175 * value cannot be read back within the specified time. 176 */ 177 #define HDA_DSP_STREAM_RUN_TIMEOUT 300 178 179 #define HDA_DSP_SPIB_ENABLE 1 180 #define HDA_DSP_SPIB_DISABLE 0 181 182 #define SOF_HDA_MAX_BUFFER_SIZE (32 * PAGE_SIZE) 183 184 #define HDA_DSP_STACK_DUMP_SIZE 32 185 186 /* ROM status/error values */ 187 #define HDA_DSP_ROM_STS_MASK GENMASK(23, 0) 188 #define HDA_DSP_ROM_INIT 0x1 189 #define HDA_DSP_ROM_FW_MANIFEST_LOADED 0x3 190 #define HDA_DSP_ROM_FW_FW_LOADED 0x4 191 #define HDA_DSP_ROM_FW_ENTERED 0x5 192 #define HDA_DSP_ROM_RFW_START 0xf 193 #define HDA_DSP_ROM_CSE_ERROR 40 194 #define HDA_DSP_ROM_CSE_WRONG_RESPONSE 41 195 #define HDA_DSP_ROM_IMR_TO_SMALL 42 196 #define HDA_DSP_ROM_BASE_FW_NOT_FOUND 43 197 #define HDA_DSP_ROM_CSE_VALIDATION_FAILED 44 198 #define HDA_DSP_ROM_IPC_FATAL_ERROR 45 199 #define HDA_DSP_ROM_L2_CACHE_ERROR 46 200 #define HDA_DSP_ROM_LOAD_OFFSET_TO_SMALL 47 201 #define HDA_DSP_ROM_API_PTR_INVALID 50 202 #define HDA_DSP_ROM_BASEFW_INCOMPAT 51 203 #define HDA_DSP_ROM_UNHANDLED_INTERRUPT 0xBEE00000 204 #define HDA_DSP_ROM_MEMORY_HOLE_ECC 0xECC00000 205 #define HDA_DSP_ROM_KERNEL_EXCEPTION 0xCAFE0000 206 #define HDA_DSP_ROM_USER_EXCEPTION 0xBEEF0000 207 #define HDA_DSP_ROM_UNEXPECTED_RESET 0xDECAF000 208 #define HDA_DSP_ROM_NULL_FW_ENTRY 0x4c4c4e55 209 #define HDA_DSP_IPC_PURGE_FW 0x01004000 210 211 /* various timeout values */ 212 #define HDA_DSP_PU_TIMEOUT 50 213 #define HDA_DSP_PD_TIMEOUT 50 214 #define HDA_DSP_RESET_TIMEOUT_US 50000 215 #define HDA_DSP_BASEFW_TIMEOUT_US 3000000 216 #define HDA_DSP_INIT_TIMEOUT_US 500000 217 #define HDA_DSP_CTRL_RESET_TIMEOUT 100 218 #define HDA_DSP_WAIT_TIMEOUT 500 /* 500 msec */ 219 #define HDA_DSP_REG_POLL_INTERVAL_US 500 /* 0.5 msec */ 220 #define HDA_DSP_REG_POLL_RETRY_COUNT 50 221 222 #define HDA_DSP_ADSPIC_IPC 1 223 #define HDA_DSP_ADSPIS_IPC 1 224 225 /* Intel HD Audio General DSP Registers */ 226 #define HDA_DSP_GEN_BASE 0x0 227 #define HDA_DSP_REG_ADSPCS (HDA_DSP_GEN_BASE + 0x04) 228 #define HDA_DSP_REG_ADSPIC (HDA_DSP_GEN_BASE + 0x08) 229 #define HDA_DSP_REG_ADSPIS (HDA_DSP_GEN_BASE + 0x0C) 230 #define HDA_DSP_REG_ADSPIC2 (HDA_DSP_GEN_BASE + 0x10) 231 #define HDA_DSP_REG_ADSPIS2 (HDA_DSP_GEN_BASE + 0x14) 232 233 /* Intel HD Audio Inter-Processor Communication Registers */ 234 #define HDA_DSP_IPC_BASE 0x40 235 #define HDA_DSP_REG_HIPCT (HDA_DSP_IPC_BASE + 0x00) 236 #define HDA_DSP_REG_HIPCTE (HDA_DSP_IPC_BASE + 0x04) 237 #define HDA_DSP_REG_HIPCI (HDA_DSP_IPC_BASE + 0x08) 238 #define HDA_DSP_REG_HIPCIE (HDA_DSP_IPC_BASE + 0x0C) 239 #define HDA_DSP_REG_HIPCCTL (HDA_DSP_IPC_BASE + 0x10) 240 241 /* Intel Vendor Specific Registers */ 242 #define HDA_VS_INTEL_EM2 0x1030 243 #define HDA_VS_INTEL_EM2_L1SEN BIT(13) 244 245 /* HIPCI */ 246 #define HDA_DSP_REG_HIPCI_BUSY BIT(31) 247 #define HDA_DSP_REG_HIPCI_MSG_MASK 0x7FFFFFFF 248 249 /* HIPCIE */ 250 #define HDA_DSP_REG_HIPCIE_DONE BIT(30) 251 #define HDA_DSP_REG_HIPCIE_MSG_MASK 0x3FFFFFFF 252 253 /* HIPCCTL */ 254 #define HDA_DSP_REG_HIPCCTL_DONE BIT(1) 255 #define HDA_DSP_REG_HIPCCTL_BUSY BIT(0) 256 257 /* HIPCT */ 258 #define HDA_DSP_REG_HIPCT_BUSY BIT(31) 259 #define HDA_DSP_REG_HIPCT_MSG_MASK 0x7FFFFFFF 260 261 /* HIPCTE */ 262 #define HDA_DSP_REG_HIPCTE_MSG_MASK 0x3FFFFFFF 263 264 #define HDA_DSP_ADSPIC_CL_DMA 0x2 265 #define HDA_DSP_ADSPIS_CL_DMA 0x2 266 267 /* Delay before scheduling D0i3 entry */ 268 #define BXT_D0I3_DELAY 5000 269 270 #define FW_CL_STREAM_NUMBER 0x1 271 272 /* ADSPCS - Audio DSP Control & Status */ 273 274 /* 275 * Core Reset - asserted high 276 * CRST Mask for a given core mask pattern, cm 277 */ 278 #define HDA_DSP_ADSPCS_CRST_SHIFT 0 279 #define HDA_DSP_ADSPCS_CRST_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CRST_SHIFT) 280 281 /* 282 * Core run/stall - when set to '1' core is stalled 283 * CSTALL Mask for a given core mask pattern, cm 284 */ 285 #define HDA_DSP_ADSPCS_CSTALL_SHIFT 8 286 #define HDA_DSP_ADSPCS_CSTALL_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CSTALL_SHIFT) 287 288 /* 289 * Set Power Active - when set to '1' turn cores on 290 * SPA Mask for a given core mask pattern, cm 291 */ 292 #define HDA_DSP_ADSPCS_SPA_SHIFT 16 293 #define HDA_DSP_ADSPCS_SPA_MASK(cm) ((cm) << HDA_DSP_ADSPCS_SPA_SHIFT) 294 295 /* 296 * Current Power Active - power status of cores, set by hardware 297 * CPA Mask for a given core mask pattern, cm 298 */ 299 #define HDA_DSP_ADSPCS_CPA_SHIFT 24 300 #define HDA_DSP_ADSPCS_CPA_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CPA_SHIFT) 301 302 /* Mask for a given core index, c = 0.. number of supported cores - 1 */ 303 #define HDA_DSP_CORE_MASK(c) BIT(c) 304 305 /* 306 * Mask for a given number of cores 307 * nc = number of supported cores 308 */ 309 #define SOF_DSP_CORES_MASK(nc) GENMASK(((nc) - 1), 0) 310 311 /* Intel HD Audio Inter-Processor Communication Registers for Cannonlake*/ 312 #define CNL_DSP_IPC_BASE 0xc0 313 #define CNL_DSP_REG_HIPCTDR (CNL_DSP_IPC_BASE + 0x00) 314 #define CNL_DSP_REG_HIPCTDA (CNL_DSP_IPC_BASE + 0x04) 315 #define CNL_DSP_REG_HIPCTDD (CNL_DSP_IPC_BASE + 0x08) 316 #define CNL_DSP_REG_HIPCIDR (CNL_DSP_IPC_BASE + 0x10) 317 #define CNL_DSP_REG_HIPCIDA (CNL_DSP_IPC_BASE + 0x14) 318 #define CNL_DSP_REG_HIPCIDD (CNL_DSP_IPC_BASE + 0x18) 319 #define CNL_DSP_REG_HIPCCTL (CNL_DSP_IPC_BASE + 0x28) 320 321 /* HIPCI */ 322 #define CNL_DSP_REG_HIPCIDR_BUSY BIT(31) 323 #define CNL_DSP_REG_HIPCIDR_MSG_MASK 0x7FFFFFFF 324 325 /* HIPCIE */ 326 #define CNL_DSP_REG_HIPCIDA_DONE BIT(31) 327 #define CNL_DSP_REG_HIPCIDA_MSG_MASK 0x7FFFFFFF 328 329 /* HIPCCTL */ 330 #define CNL_DSP_REG_HIPCCTL_DONE BIT(1) 331 #define CNL_DSP_REG_HIPCCTL_BUSY BIT(0) 332 333 /* HIPCT */ 334 #define CNL_DSP_REG_HIPCTDR_BUSY BIT(31) 335 #define CNL_DSP_REG_HIPCTDR_MSG_MASK 0x7FFFFFFF 336 337 /* HIPCTDA */ 338 #define CNL_DSP_REG_HIPCTDA_DONE BIT(31) 339 #define CNL_DSP_REG_HIPCTDA_MSG_MASK 0x7FFFFFFF 340 341 /* HIPCTDD */ 342 #define CNL_DSP_REG_HIPCTDD_MSG_MASK 0x7FFFFFFF 343 344 /* BDL */ 345 #define HDA_DSP_BDL_SIZE 4096 346 #define HDA_DSP_MAX_BDL_ENTRIES \ 347 (HDA_DSP_BDL_SIZE / sizeof(struct sof_intel_dsp_bdl)) 348 349 /* Number of DAIs */ 350 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) 351 352 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_PROBES) 353 #define SOF_SKL_NUM_DAIS 16 354 #else 355 #define SOF_SKL_NUM_DAIS 15 356 #endif 357 358 #else 359 #define SOF_SKL_NUM_DAIS 8 360 #endif 361 362 /* Intel HD Audio SRAM Window 0*/ 363 #define HDA_ADSP_SRAM0_BASE_SKL 0x8000 364 365 /* Firmware status window */ 366 #define HDA_ADSP_FW_STATUS_SKL HDA_ADSP_SRAM0_BASE_SKL 367 #define HDA_ADSP_ERROR_CODE_SKL (HDA_ADSP_FW_STATUS_SKL + 0x4) 368 369 /* Host Device Memory Space */ 370 #define APL_SSP_BASE_OFFSET 0x2000 371 #define CNL_SSP_BASE_OFFSET 0x10000 372 373 /* Host Device Memory Size of a Single SSP */ 374 #define SSP_DEV_MEM_SIZE 0x1000 375 376 /* SSP Count of the Platform */ 377 #define APL_SSP_COUNT 6 378 #define CNL_SSP_COUNT 3 379 #define ICL_SSP_COUNT 6 380 381 /* SSP Registers */ 382 #define SSP_SSC1_OFFSET 0x4 383 #define SSP_SET_SCLK_SLAVE BIT(25) 384 #define SSP_SET_SFRM_SLAVE BIT(24) 385 #define SSP_SET_SLAVE (SSP_SET_SCLK_SLAVE | SSP_SET_SFRM_SLAVE) 386 387 #define HDA_IDISP_CODEC(x) ((x) & BIT(2)) 388 389 struct sof_intel_dsp_bdl { 390 __le32 addr_l; 391 __le32 addr_h; 392 __le32 size; 393 __le32 ioc; 394 } __attribute((packed)); 395 396 #define SOF_HDA_PLAYBACK_STREAMS 16 397 #define SOF_HDA_CAPTURE_STREAMS 16 398 #define SOF_HDA_PLAYBACK 0 399 #define SOF_HDA_CAPTURE 1 400 401 /* 402 * Time in ms for opportunistic D0I3 entry delay. 403 * This has been deliberately chosen to be long to avoid race conditions. 404 * Could be optimized in future. 405 */ 406 #define SOF_HDA_D0I3_WORK_DELAY_MS 5000 407 408 /* HDA DSP D0 substate */ 409 enum sof_hda_D0_substate { 410 SOF_HDA_DSP_PM_D0I0, /* default D0 substate */ 411 SOF_HDA_DSP_PM_D0I3, /* low power D0 substate */ 412 }; 413 414 /* represents DSP HDA controller frontend - i.e. host facing control */ 415 struct sof_intel_hda_dev { 416 417 struct hda_bus hbus; 418 419 /* hw config */ 420 const struct sof_intel_dsp_desc *desc; 421 422 /* trace */ 423 struct hdac_ext_stream *dtrace_stream; 424 425 /* if position update IPC needed */ 426 u32 no_ipc_position; 427 428 /* the maximum number of streams (playback + capture) supported */ 429 u32 stream_max; 430 431 /* PM related */ 432 bool l1_support_changed;/* during suspend, is L1SEN changed or not */ 433 434 /* DMIC device */ 435 struct platform_device *dmic_dev; 436 437 /* delayed work to enter D0I3 opportunistically */ 438 struct delayed_work d0i3_work; 439 }; 440 441 static inline struct hdac_bus *sof_to_bus(struct snd_sof_dev *s) 442 { 443 struct sof_intel_hda_dev *hda = s->pdata->hw_pdata; 444 445 return &hda->hbus.core; 446 } 447 448 static inline struct hda_bus *sof_to_hbus(struct snd_sof_dev *s) 449 { 450 struct sof_intel_hda_dev *hda = s->pdata->hw_pdata; 451 452 return &hda->hbus; 453 } 454 455 struct sof_intel_hda_stream { 456 struct snd_sof_dev *sdev; 457 struct hdac_ext_stream hda_stream; 458 struct sof_intel_stream stream; 459 int host_reserved; /* reserve host DMA channel */ 460 }; 461 462 #define hstream_to_sof_hda_stream(hstream) \ 463 container_of(hstream, struct sof_intel_hda_stream, hda_stream) 464 465 #define bus_to_sof_hda(bus) \ 466 container_of(bus, struct sof_intel_hda_dev, hbus.core) 467 468 #define SOF_STREAM_SD_OFFSET(s) \ 469 (SOF_HDA_ADSP_SD_ENTRY_SIZE * ((s)->index) \ 470 + SOF_HDA_ADSP_LOADER_BASE) 471 472 /* 473 * DSP Core services. 474 */ 475 int hda_dsp_probe(struct snd_sof_dev *sdev); 476 int hda_dsp_remove(struct snd_sof_dev *sdev); 477 int hda_dsp_core_reset_enter(struct snd_sof_dev *sdev, 478 unsigned int core_mask); 479 int hda_dsp_core_reset_leave(struct snd_sof_dev *sdev, 480 unsigned int core_mask); 481 int hda_dsp_core_stall_reset(struct snd_sof_dev *sdev, unsigned int core_mask); 482 int hda_dsp_core_run(struct snd_sof_dev *sdev, unsigned int core_mask); 483 int hda_dsp_core_power_up(struct snd_sof_dev *sdev, unsigned int core_mask); 484 int hda_dsp_enable_core(struct snd_sof_dev *sdev, unsigned int core_mask); 485 int hda_dsp_core_power_down(struct snd_sof_dev *sdev, unsigned int core_mask); 486 bool hda_dsp_core_is_enabled(struct snd_sof_dev *sdev, 487 unsigned int core_mask); 488 int hda_dsp_core_reset_power_down(struct snd_sof_dev *sdev, 489 unsigned int core_mask); 490 void hda_dsp_ipc_int_enable(struct snd_sof_dev *sdev); 491 void hda_dsp_ipc_int_disable(struct snd_sof_dev *sdev); 492 493 int hda_dsp_set_power_state(struct snd_sof_dev *sdev, 494 const struct sof_dsp_power_state *target_state); 495 496 int hda_dsp_suspend(struct snd_sof_dev *sdev, u32 target_state); 497 int hda_dsp_resume(struct snd_sof_dev *sdev); 498 int hda_dsp_runtime_suspend(struct snd_sof_dev *sdev); 499 int hda_dsp_runtime_resume(struct snd_sof_dev *sdev); 500 int hda_dsp_runtime_idle(struct snd_sof_dev *sdev); 501 int hda_dsp_set_hw_params_upon_resume(struct snd_sof_dev *sdev); 502 void hda_dsp_dump_skl(struct snd_sof_dev *sdev, u32 flags); 503 void hda_dsp_dump(struct snd_sof_dev *sdev, u32 flags); 504 void hda_ipc_dump(struct snd_sof_dev *sdev); 505 void hda_ipc_irq_dump(struct snd_sof_dev *sdev); 506 void hda_dsp_d0i3_work(struct work_struct *work); 507 508 /* 509 * DSP PCM Operations. 510 */ 511 u32 hda_dsp_get_mult_div(struct snd_sof_dev *sdev, int rate); 512 u32 hda_dsp_get_bits(struct snd_sof_dev *sdev, int sample_bits); 513 int hda_dsp_pcm_open(struct snd_sof_dev *sdev, 514 struct snd_pcm_substream *substream); 515 int hda_dsp_pcm_close(struct snd_sof_dev *sdev, 516 struct snd_pcm_substream *substream); 517 int hda_dsp_pcm_hw_params(struct snd_sof_dev *sdev, 518 struct snd_pcm_substream *substream, 519 struct snd_pcm_hw_params *params, 520 struct sof_ipc_stream_params *ipc_params); 521 int hda_dsp_stream_hw_free(struct snd_sof_dev *sdev, 522 struct snd_pcm_substream *substream); 523 int hda_dsp_pcm_trigger(struct snd_sof_dev *sdev, 524 struct snd_pcm_substream *substream, int cmd); 525 snd_pcm_uframes_t hda_dsp_pcm_pointer(struct snd_sof_dev *sdev, 526 struct snd_pcm_substream *substream); 527 528 /* 529 * DSP Stream Operations. 530 */ 531 532 int hda_dsp_stream_init(struct snd_sof_dev *sdev); 533 void hda_dsp_stream_free(struct snd_sof_dev *sdev); 534 int hda_dsp_stream_hw_params(struct snd_sof_dev *sdev, 535 struct hdac_ext_stream *stream, 536 struct snd_dma_buffer *dmab, 537 struct snd_pcm_hw_params *params); 538 int hda_dsp_stream_trigger(struct snd_sof_dev *sdev, 539 struct hdac_ext_stream *stream, int cmd); 540 irqreturn_t hda_dsp_stream_threaded_handler(int irq, void *context); 541 int hda_dsp_stream_setup_bdl(struct snd_sof_dev *sdev, 542 struct snd_dma_buffer *dmab, 543 struct hdac_stream *stream); 544 bool hda_dsp_check_ipc_irq(struct snd_sof_dev *sdev); 545 bool hda_dsp_check_stream_irq(struct snd_sof_dev *sdev); 546 547 struct hdac_ext_stream * 548 hda_dsp_stream_get(struct snd_sof_dev *sdev, int direction); 549 int hda_dsp_stream_put(struct snd_sof_dev *sdev, int direction, int stream_tag); 550 int hda_dsp_stream_spib_config(struct snd_sof_dev *sdev, 551 struct hdac_ext_stream *stream, 552 int enable, u32 size); 553 554 void hda_ipc_msg_data(struct snd_sof_dev *sdev, 555 struct snd_pcm_substream *substream, 556 void *p, size_t sz); 557 int hda_ipc_pcm_params(struct snd_sof_dev *sdev, 558 struct snd_pcm_substream *substream, 559 const struct sof_ipc_pcm_params_reply *reply); 560 561 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_PROBES) 562 /* 563 * Probe Compress Operations. 564 */ 565 int hda_probe_compr_assign(struct snd_sof_dev *sdev, 566 struct snd_compr_stream *cstream, 567 struct snd_soc_dai *dai); 568 int hda_probe_compr_free(struct snd_sof_dev *sdev, 569 struct snd_compr_stream *cstream, 570 struct snd_soc_dai *dai); 571 int hda_probe_compr_set_params(struct snd_sof_dev *sdev, 572 struct snd_compr_stream *cstream, 573 struct snd_compr_params *params, 574 struct snd_soc_dai *dai); 575 int hda_probe_compr_trigger(struct snd_sof_dev *sdev, 576 struct snd_compr_stream *cstream, int cmd, 577 struct snd_soc_dai *dai); 578 int hda_probe_compr_pointer(struct snd_sof_dev *sdev, 579 struct snd_compr_stream *cstream, 580 struct snd_compr_tstamp *tstamp, 581 struct snd_soc_dai *dai); 582 #endif 583 584 /* 585 * DSP IPC Operations. 586 */ 587 int hda_dsp_ipc_send_msg(struct snd_sof_dev *sdev, 588 struct snd_sof_ipc_msg *msg); 589 void hda_dsp_ipc_get_reply(struct snd_sof_dev *sdev); 590 int hda_dsp_ipc_get_mailbox_offset(struct snd_sof_dev *sdev); 591 int hda_dsp_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id); 592 593 irqreturn_t hda_dsp_ipc_irq_thread(int irq, void *context); 594 int hda_dsp_ipc_cmd_done(struct snd_sof_dev *sdev, int dir); 595 596 /* 597 * DSP Code loader. 598 */ 599 int hda_dsp_cl_boot_firmware(struct snd_sof_dev *sdev); 600 int hda_dsp_cl_boot_firmware_skl(struct snd_sof_dev *sdev); 601 602 /* pre and post fw run ops */ 603 int hda_dsp_pre_fw_run(struct snd_sof_dev *sdev); 604 int hda_dsp_post_fw_run(struct snd_sof_dev *sdev); 605 606 /* 607 * HDA Controller Operations. 608 */ 609 int hda_dsp_ctrl_get_caps(struct snd_sof_dev *sdev); 610 void hda_dsp_ctrl_ppcap_enable(struct snd_sof_dev *sdev, bool enable); 611 void hda_dsp_ctrl_ppcap_int_enable(struct snd_sof_dev *sdev, bool enable); 612 int hda_dsp_ctrl_link_reset(struct snd_sof_dev *sdev, bool reset); 613 void hda_dsp_ctrl_misc_clock_gating(struct snd_sof_dev *sdev, bool enable); 614 int hda_dsp_ctrl_clock_power_gating(struct snd_sof_dev *sdev, bool enable); 615 int hda_dsp_ctrl_init_chip(struct snd_sof_dev *sdev, bool full_reset); 616 void hda_dsp_ctrl_stop_chip(struct snd_sof_dev *sdev); 617 /* 618 * HDA bus operations. 619 */ 620 void sof_hda_bus_init(struct hdac_bus *bus, struct device *dev); 621 622 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) 623 /* 624 * HDA Codec operations. 625 */ 626 void hda_codec_probe_bus(struct snd_sof_dev *sdev, 627 bool hda_codec_use_common_hdmi); 628 void hda_codec_jack_wake_enable(struct snd_sof_dev *sdev); 629 void hda_codec_jack_check(struct snd_sof_dev *sdev); 630 631 #endif /* CONFIG_SND_SOC_SOF_HDA */ 632 633 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) && \ 634 (IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI) || \ 635 IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) 636 637 void hda_codec_i915_display_power(struct snd_sof_dev *sdev, bool enable); 638 int hda_codec_i915_init(struct snd_sof_dev *sdev); 639 int hda_codec_i915_exit(struct snd_sof_dev *sdev); 640 641 #else 642 643 static inline void hda_codec_i915_display_power(struct snd_sof_dev *sdev, 644 bool enable) { } 645 static inline int hda_codec_i915_init(struct snd_sof_dev *sdev) { return 0; } 646 static inline int hda_codec_i915_exit(struct snd_sof_dev *sdev) { return 0; } 647 648 #endif 649 650 /* 651 * Trace Control. 652 */ 653 int hda_dsp_trace_init(struct snd_sof_dev *sdev, u32 *stream_tag); 654 int hda_dsp_trace_release(struct snd_sof_dev *sdev); 655 int hda_dsp_trace_trigger(struct snd_sof_dev *sdev, int cmd); 656 657 /* common dai driver */ 658 extern struct snd_soc_dai_driver skl_dai[]; 659 660 /* 661 * Platform Specific HW abstraction Ops. 662 */ 663 extern const struct snd_sof_dsp_ops sof_apl_ops; 664 extern const struct snd_sof_dsp_ops sof_cnl_ops; 665 666 extern const struct sof_intel_dsp_desc apl_chip_info; 667 extern const struct sof_intel_dsp_desc cnl_chip_info; 668 extern const struct sof_intel_dsp_desc skl_chip_info; 669 extern const struct sof_intel_dsp_desc icl_chip_info; 670 extern const struct sof_intel_dsp_desc tgl_chip_info; 671 extern const struct sof_intel_dsp_desc ehl_chip_info; 672 extern const struct sof_intel_dsp_desc jsl_chip_info; 673 674 /* machine driver select */ 675 void hda_machine_select(struct snd_sof_dev *sdev); 676 void hda_set_mach_params(const struct snd_soc_acpi_mach *mach, 677 struct device *dev); 678 679 #endif 680