xref: /openbmc/linux/sound/soc/sof/intel/hda.h (revision 6c33a6f4)
1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
2 /*
3  * This file is provided under a dual BSD/GPLv2 license.  When using or
4  * redistributing this file, you may do so under either license.
5  *
6  * Copyright(c) 2017 Intel Corporation. All rights reserved.
7  *
8  * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
9  */
10 
11 #ifndef __SOF_INTEL_HDA_H
12 #define __SOF_INTEL_HDA_H
13 
14 #include <sound/hda_codec.h>
15 #include <sound/hdaudio_ext.h>
16 #include "shim.h"
17 
18 /* PCI registers */
19 #define PCI_TCSEL			0x44
20 #define PCI_PGCTL			PCI_TCSEL
21 #define PCI_CGCTL			0x48
22 
23 /* PCI_PGCTL bits */
24 #define PCI_PGCTL_ADSPPGD               BIT(2)
25 #define PCI_PGCTL_LSRMD_MASK		BIT(4)
26 
27 /* PCI_CGCTL bits */
28 #define PCI_CGCTL_MISCBDCGE_MASK	BIT(6)
29 #define PCI_CGCTL_ADSPDCGE              BIT(1)
30 
31 /* Legacy HDA registers and bits used - widths are variable */
32 #define SOF_HDA_GCAP			0x0
33 #define SOF_HDA_GCTL			0x8
34 /* accept unsol. response enable */
35 #define SOF_HDA_GCTL_UNSOL		BIT(8)
36 #define SOF_HDA_LLCH			0x14
37 #define SOF_HDA_INTCTL			0x20
38 #define SOF_HDA_INTSTS			0x24
39 #define SOF_HDA_WAKESTS			0x0E
40 #define SOF_HDA_WAKESTS_INT_MASK	((1 << 8) - 1)
41 #define SOF_HDA_RIRBSTS			0x5d
42 
43 /* SOF_HDA_GCTL register bist */
44 #define SOF_HDA_GCTL_RESET		BIT(0)
45 
46 /* SOF_HDA_INCTL regs */
47 #define SOF_HDA_INT_GLOBAL_EN		BIT(31)
48 #define SOF_HDA_INT_CTRL_EN		BIT(30)
49 #define SOF_HDA_INT_ALL_STREAM		0xff
50 
51 /* SOF_HDA_INTSTS regs */
52 #define SOF_HDA_INTSTS_GIS		BIT(31)
53 
54 #define SOF_HDA_MAX_CAPS		10
55 #define SOF_HDA_CAP_ID_OFF		16
56 #define SOF_HDA_CAP_ID_MASK		GENMASK(SOF_HDA_CAP_ID_OFF + 11,\
57 						SOF_HDA_CAP_ID_OFF)
58 #define SOF_HDA_CAP_NEXT_MASK		0xFFFF
59 
60 #define SOF_HDA_GTS_CAP_ID			0x1
61 #define SOF_HDA_ML_CAP_ID			0x2
62 
63 #define SOF_HDA_PP_CAP_ID		0x3
64 #define SOF_HDA_REG_PP_PPCH		0x10
65 #define SOF_HDA_REG_PP_PPCTL		0x04
66 #define SOF_HDA_REG_PP_PPSTS		0x08
67 #define SOF_HDA_PPCTL_PIE		BIT(31)
68 #define SOF_HDA_PPCTL_GPROCEN		BIT(30)
69 
70 /*Vendor Specific Registers*/
71 #define SOF_HDA_VS_D0I3C		0x104A
72 
73 /* D0I3C Register fields */
74 #define SOF_HDA_VS_D0I3C_CIP		BIT(0) /* Command-In-Progress */
75 #define SOF_HDA_VS_D0I3C_I3		BIT(2) /* D0i3 enable bit */
76 
77 /* DPIB entry size: 8 Bytes = 2 DWords */
78 #define SOF_HDA_DPIB_ENTRY_SIZE	0x8
79 
80 #define SOF_HDA_SPIB_CAP_ID		0x4
81 #define SOF_HDA_DRSM_CAP_ID		0x5
82 
83 #define SOF_HDA_SPIB_BASE		0x08
84 #define SOF_HDA_SPIB_INTERVAL		0x08
85 #define SOF_HDA_SPIB_SPIB		0x00
86 #define SOF_HDA_SPIB_MAXFIFO		0x04
87 
88 #define SOF_HDA_PPHC_BASE		0x10
89 #define SOF_HDA_PPHC_INTERVAL		0x10
90 
91 #define SOF_HDA_PPLC_BASE		0x10
92 #define SOF_HDA_PPLC_MULTI		0x10
93 #define SOF_HDA_PPLC_INTERVAL		0x10
94 
95 #define SOF_HDA_DRSM_BASE		0x08
96 #define SOF_HDA_DRSM_INTERVAL		0x08
97 
98 /* Descriptor error interrupt */
99 #define SOF_HDA_CL_DMA_SD_INT_DESC_ERR		0x10
100 
101 /* FIFO error interrupt */
102 #define SOF_HDA_CL_DMA_SD_INT_FIFO_ERR		0x08
103 
104 /* Buffer completion interrupt */
105 #define SOF_HDA_CL_DMA_SD_INT_COMPLETE		0x04
106 
107 #define SOF_HDA_CL_DMA_SD_INT_MASK \
108 	(SOF_HDA_CL_DMA_SD_INT_DESC_ERR | \
109 	SOF_HDA_CL_DMA_SD_INT_FIFO_ERR | \
110 	SOF_HDA_CL_DMA_SD_INT_COMPLETE)
111 #define SOF_HDA_SD_CTL_DMA_START		0x02 /* Stream DMA start bit */
112 
113 /* Intel HD Audio Code Loader DMA Registers */
114 #define SOF_HDA_ADSP_LOADER_BASE		0x80
115 #define SOF_HDA_ADSP_DPLBASE			0x70
116 #define SOF_HDA_ADSP_DPUBASE			0x74
117 #define SOF_HDA_ADSP_DPLBASE_ENABLE		0x01
118 
119 /* Stream Registers */
120 #define SOF_HDA_ADSP_REG_CL_SD_CTL		0x00
121 #define SOF_HDA_ADSP_REG_CL_SD_STS		0x03
122 #define SOF_HDA_ADSP_REG_CL_SD_LPIB		0x04
123 #define SOF_HDA_ADSP_REG_CL_SD_CBL		0x08
124 #define SOF_HDA_ADSP_REG_CL_SD_LVI		0x0C
125 #define SOF_HDA_ADSP_REG_CL_SD_FIFOW		0x0E
126 #define SOF_HDA_ADSP_REG_CL_SD_FIFOSIZE		0x10
127 #define SOF_HDA_ADSP_REG_CL_SD_FORMAT		0x12
128 #define SOF_HDA_ADSP_REG_CL_SD_FIFOL		0x14
129 #define SOF_HDA_ADSP_REG_CL_SD_BDLPL		0x18
130 #define SOF_HDA_ADSP_REG_CL_SD_BDLPU		0x1C
131 #define SOF_HDA_ADSP_SD_ENTRY_SIZE		0x20
132 
133 /* CL: Software Position Based FIFO Capability Registers */
134 #define SOF_DSP_REG_CL_SPBFIFO \
135 	(SOF_HDA_ADSP_LOADER_BASE + 0x20)
136 #define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCH	0x0
137 #define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCCTL	0x4
138 #define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPIB	0x8
139 #define SOF_HDA_ADSP_REG_CL_SPBFIFO_MAXFIFOS	0xc
140 
141 /* Stream Number */
142 #define SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT	20
143 #define SOF_HDA_CL_SD_CTL_STREAM_TAG_MASK \
144 	GENMASK(SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT + 3,\
145 		SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT)
146 
147 #define HDA_DSP_HDA_BAR				0
148 #define HDA_DSP_PP_BAR				1
149 #define HDA_DSP_SPIB_BAR			2
150 #define HDA_DSP_DRSM_BAR			3
151 #define HDA_DSP_BAR				4
152 
153 #define SRAM_WINDOW_OFFSET(x)			(0x80000 + (x) * 0x20000)
154 
155 #define HDA_DSP_MBOX_OFFSET			SRAM_WINDOW_OFFSET(0)
156 
157 #define HDA_DSP_PANIC_OFFSET(x) \
158 	(((x) & 0xFFFFFF) + HDA_DSP_MBOX_OFFSET)
159 
160 /* SRAM window 0 FW "registers" */
161 #define HDA_DSP_SRAM_REG_ROM_STATUS		(HDA_DSP_MBOX_OFFSET + 0x0)
162 #define HDA_DSP_SRAM_REG_ROM_ERROR		(HDA_DSP_MBOX_OFFSET + 0x4)
163 /* FW and ROM share offset 4 */
164 #define HDA_DSP_SRAM_REG_FW_STATUS		(HDA_DSP_MBOX_OFFSET + 0x4)
165 #define HDA_DSP_SRAM_REG_FW_TRACEP		(HDA_DSP_MBOX_OFFSET + 0x8)
166 #define HDA_DSP_SRAM_REG_FW_END			(HDA_DSP_MBOX_OFFSET + 0xc)
167 
168 #define HDA_DSP_MBOX_UPLINK_OFFSET		0x81000
169 
170 #define HDA_DSP_STREAM_RESET_TIMEOUT		300
171 /*
172  * Timeout in us, for setting the stream RUN bit, during
173  * start/stop the stream. The timeout expires if new RUN bit
174  * value cannot be read back within the specified time.
175  */
176 #define HDA_DSP_STREAM_RUN_TIMEOUT		300
177 #define HDA_DSP_CL_TRIGGER_TIMEOUT		300
178 
179 #define HDA_DSP_SPIB_ENABLE			1
180 #define HDA_DSP_SPIB_DISABLE			0
181 
182 #define SOF_HDA_MAX_BUFFER_SIZE			(32 * PAGE_SIZE)
183 
184 #define HDA_DSP_STACK_DUMP_SIZE			32
185 
186 /* ROM  status/error values */
187 #define HDA_DSP_ROM_STS_MASK			GENMASK(23, 0)
188 #define HDA_DSP_ROM_INIT			0x1
189 #define HDA_DSP_ROM_FW_MANIFEST_LOADED		0x3
190 #define HDA_DSP_ROM_FW_FW_LOADED		0x4
191 #define HDA_DSP_ROM_FW_ENTERED			0x5
192 #define HDA_DSP_ROM_RFW_START			0xf
193 #define HDA_DSP_ROM_CSE_ERROR			40
194 #define HDA_DSP_ROM_CSE_WRONG_RESPONSE		41
195 #define HDA_DSP_ROM_IMR_TO_SMALL		42
196 #define HDA_DSP_ROM_BASE_FW_NOT_FOUND		43
197 #define HDA_DSP_ROM_CSE_VALIDATION_FAILED	44
198 #define HDA_DSP_ROM_IPC_FATAL_ERROR		45
199 #define HDA_DSP_ROM_L2_CACHE_ERROR		46
200 #define HDA_DSP_ROM_LOAD_OFFSET_TO_SMALL	47
201 #define HDA_DSP_ROM_API_PTR_INVALID		50
202 #define HDA_DSP_ROM_BASEFW_INCOMPAT		51
203 #define HDA_DSP_ROM_UNHANDLED_INTERRUPT		0xBEE00000
204 #define HDA_DSP_ROM_MEMORY_HOLE_ECC		0xECC00000
205 #define HDA_DSP_ROM_KERNEL_EXCEPTION		0xCAFE0000
206 #define HDA_DSP_ROM_USER_EXCEPTION		0xBEEF0000
207 #define HDA_DSP_ROM_UNEXPECTED_RESET		0xDECAF000
208 #define HDA_DSP_ROM_NULL_FW_ENTRY		0x4c4c4e55
209 #define HDA_DSP_IPC_PURGE_FW			0x01004000
210 
211 /* various timeout values */
212 #define HDA_DSP_PU_TIMEOUT		50
213 #define HDA_DSP_PD_TIMEOUT		50
214 #define HDA_DSP_RESET_TIMEOUT_US	50000
215 #define HDA_DSP_BASEFW_TIMEOUT_US       3000000
216 #define HDA_DSP_INIT_TIMEOUT_US	500000
217 #define HDA_DSP_CTRL_RESET_TIMEOUT		100
218 #define HDA_DSP_WAIT_TIMEOUT		500	/* 500 msec */
219 #define HDA_DSP_REG_POLL_INTERVAL_US		500	/* 0.5 msec */
220 #define HDA_DSP_REG_POLL_RETRY_COUNT		50
221 
222 #define HDA_DSP_ADSPIC_IPC			1
223 #define HDA_DSP_ADSPIS_IPC			1
224 
225 /* Intel HD Audio General DSP Registers */
226 #define HDA_DSP_GEN_BASE		0x0
227 #define HDA_DSP_REG_ADSPCS		(HDA_DSP_GEN_BASE + 0x04)
228 #define HDA_DSP_REG_ADSPIC		(HDA_DSP_GEN_BASE + 0x08)
229 #define HDA_DSP_REG_ADSPIS		(HDA_DSP_GEN_BASE + 0x0C)
230 #define HDA_DSP_REG_ADSPIC2		(HDA_DSP_GEN_BASE + 0x10)
231 #define HDA_DSP_REG_ADSPIS2		(HDA_DSP_GEN_BASE + 0x14)
232 
233 /* Intel HD Audio Inter-Processor Communication Registers */
234 #define HDA_DSP_IPC_BASE		0x40
235 #define HDA_DSP_REG_HIPCT		(HDA_DSP_IPC_BASE + 0x00)
236 #define HDA_DSP_REG_HIPCTE		(HDA_DSP_IPC_BASE + 0x04)
237 #define HDA_DSP_REG_HIPCI		(HDA_DSP_IPC_BASE + 0x08)
238 #define HDA_DSP_REG_HIPCIE		(HDA_DSP_IPC_BASE + 0x0C)
239 #define HDA_DSP_REG_HIPCCTL		(HDA_DSP_IPC_BASE + 0x10)
240 
241 /* Intel Vendor Specific Registers */
242 #define HDA_VS_INTEL_EM2		0x1030
243 #define HDA_VS_INTEL_EM2_L1SEN		BIT(13)
244 
245 /*  HIPCI */
246 #define HDA_DSP_REG_HIPCI_BUSY		BIT(31)
247 #define HDA_DSP_REG_HIPCI_MSG_MASK	0x7FFFFFFF
248 
249 /* HIPCIE */
250 #define HDA_DSP_REG_HIPCIE_DONE	BIT(30)
251 #define HDA_DSP_REG_HIPCIE_MSG_MASK	0x3FFFFFFF
252 
253 /* HIPCCTL */
254 #define HDA_DSP_REG_HIPCCTL_DONE	BIT(1)
255 #define HDA_DSP_REG_HIPCCTL_BUSY	BIT(0)
256 
257 /* HIPCT */
258 #define HDA_DSP_REG_HIPCT_BUSY		BIT(31)
259 #define HDA_DSP_REG_HIPCT_MSG_MASK	0x7FFFFFFF
260 
261 /* HIPCTE */
262 #define HDA_DSP_REG_HIPCTE_MSG_MASK	0x3FFFFFFF
263 
264 #define HDA_DSP_ADSPIC_CL_DMA		0x2
265 #define HDA_DSP_ADSPIS_CL_DMA		0x2
266 
267 /* Delay before scheduling D0i3 entry */
268 #define BXT_D0I3_DELAY 5000
269 
270 #define FW_CL_STREAM_NUMBER		0x1
271 
272 /* ADSPCS - Audio DSP Control & Status */
273 
274 /*
275  * Core Reset - asserted high
276  * CRST Mask for a given core mask pattern, cm
277  */
278 #define HDA_DSP_ADSPCS_CRST_SHIFT	0
279 #define HDA_DSP_ADSPCS_CRST_MASK(cm)	((cm) << HDA_DSP_ADSPCS_CRST_SHIFT)
280 
281 /*
282  * Core run/stall - when set to '1' core is stalled
283  * CSTALL Mask for a given core mask pattern, cm
284  */
285 #define HDA_DSP_ADSPCS_CSTALL_SHIFT	8
286 #define HDA_DSP_ADSPCS_CSTALL_MASK(cm)	((cm) << HDA_DSP_ADSPCS_CSTALL_SHIFT)
287 
288 /*
289  * Set Power Active - when set to '1' turn cores on
290  * SPA Mask for a given core mask pattern, cm
291  */
292 #define HDA_DSP_ADSPCS_SPA_SHIFT	16
293 #define HDA_DSP_ADSPCS_SPA_MASK(cm)	((cm) << HDA_DSP_ADSPCS_SPA_SHIFT)
294 
295 /*
296  * Current Power Active - power status of cores, set by hardware
297  * CPA Mask for a given core mask pattern, cm
298  */
299 #define HDA_DSP_ADSPCS_CPA_SHIFT	24
300 #define HDA_DSP_ADSPCS_CPA_MASK(cm)	((cm) << HDA_DSP_ADSPCS_CPA_SHIFT)
301 
302 /* Mask for a given core index, c = 0.. number of supported cores - 1 */
303 #define HDA_DSP_CORE_MASK(c)		BIT(c)
304 
305 /*
306  * Mask for a given number of cores
307  * nc = number of supported cores
308  */
309 #define SOF_DSP_CORES_MASK(nc)	GENMASK(((nc) - 1), 0)
310 
311 /* Intel HD Audio Inter-Processor Communication Registers for Cannonlake*/
312 #define CNL_DSP_IPC_BASE		0xc0
313 #define CNL_DSP_REG_HIPCTDR		(CNL_DSP_IPC_BASE + 0x00)
314 #define CNL_DSP_REG_HIPCTDA		(CNL_DSP_IPC_BASE + 0x04)
315 #define CNL_DSP_REG_HIPCTDD		(CNL_DSP_IPC_BASE + 0x08)
316 #define CNL_DSP_REG_HIPCIDR		(CNL_DSP_IPC_BASE + 0x10)
317 #define CNL_DSP_REG_HIPCIDA		(CNL_DSP_IPC_BASE + 0x14)
318 #define CNL_DSP_REG_HIPCIDD		(CNL_DSP_IPC_BASE + 0x18)
319 #define CNL_DSP_REG_HIPCCTL		(CNL_DSP_IPC_BASE + 0x28)
320 
321 /*  HIPCI */
322 #define CNL_DSP_REG_HIPCIDR_BUSY		BIT(31)
323 #define CNL_DSP_REG_HIPCIDR_MSG_MASK	0x7FFFFFFF
324 
325 /* HIPCIE */
326 #define CNL_DSP_REG_HIPCIDA_DONE	BIT(31)
327 #define CNL_DSP_REG_HIPCIDA_MSG_MASK	0x7FFFFFFF
328 
329 /* HIPCCTL */
330 #define CNL_DSP_REG_HIPCCTL_DONE	BIT(1)
331 #define CNL_DSP_REG_HIPCCTL_BUSY	BIT(0)
332 
333 /* HIPCT */
334 #define CNL_DSP_REG_HIPCTDR_BUSY		BIT(31)
335 #define CNL_DSP_REG_HIPCTDR_MSG_MASK	0x7FFFFFFF
336 
337 /* HIPCTDA */
338 #define CNL_DSP_REG_HIPCTDA_DONE	BIT(31)
339 #define CNL_DSP_REG_HIPCTDA_MSG_MASK	0x7FFFFFFF
340 
341 /* HIPCTDD */
342 #define CNL_DSP_REG_HIPCTDD_MSG_MASK	0x7FFFFFFF
343 
344 /* BDL */
345 #define HDA_DSP_BDL_SIZE			4096
346 #define HDA_DSP_MAX_BDL_ENTRIES			\
347 	(HDA_DSP_BDL_SIZE / sizeof(struct sof_intel_dsp_bdl))
348 
349 /* Number of DAIs */
350 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
351 #define SOF_SKL_NUM_DAIS		15
352 #else
353 #define SOF_SKL_NUM_DAIS		8
354 #endif
355 
356 /* Intel HD Audio SRAM Window 0*/
357 #define HDA_ADSP_SRAM0_BASE_SKL		0x8000
358 
359 /* Firmware status window */
360 #define HDA_ADSP_FW_STATUS_SKL		HDA_ADSP_SRAM0_BASE_SKL
361 #define HDA_ADSP_ERROR_CODE_SKL		(HDA_ADSP_FW_STATUS_SKL + 0x4)
362 
363 /* Host Device Memory Space */
364 #define APL_SSP_BASE_OFFSET	0x2000
365 #define CNL_SSP_BASE_OFFSET	0x10000
366 
367 /* Host Device Memory Size of a Single SSP */
368 #define SSP_DEV_MEM_SIZE	0x1000
369 
370 /* SSP Count of the Platform */
371 #define APL_SSP_COUNT		6
372 #define CNL_SSP_COUNT		3
373 #define ICL_SSP_COUNT		6
374 
375 /* SSP Registers */
376 #define SSP_SSC1_OFFSET		0x4
377 #define SSP_SET_SCLK_SLAVE	BIT(25)
378 #define SSP_SET_SFRM_SLAVE	BIT(24)
379 #define SSP_SET_SLAVE		(SSP_SET_SCLK_SLAVE | SSP_SET_SFRM_SLAVE)
380 
381 #define HDA_IDISP_CODEC(x) ((x) & BIT(2))
382 
383 struct sof_intel_dsp_bdl {
384 	__le32 addr_l;
385 	__le32 addr_h;
386 	__le32 size;
387 	__le32 ioc;
388 } __attribute((packed));
389 
390 #define SOF_HDA_PLAYBACK_STREAMS	16
391 #define SOF_HDA_CAPTURE_STREAMS		16
392 #define SOF_HDA_PLAYBACK		0
393 #define SOF_HDA_CAPTURE			1
394 
395 /* represents DSP HDA controller frontend - i.e. host facing control */
396 struct sof_intel_hda_dev {
397 
398 	struct hda_bus hbus;
399 
400 	/* hw config */
401 	const struct sof_intel_dsp_desc *desc;
402 
403 	/* trace */
404 	struct hdac_ext_stream *dtrace_stream;
405 
406 	/* if position update IPC needed */
407 	u32 no_ipc_position;
408 
409 	/* the maximum number of streams (playback + capture) supported */
410 	u32 stream_max;
411 
412 	/* PM related */
413 	bool l1_support_changed;/* during suspend, is L1SEN changed or not */
414 
415 	/* DMIC device */
416 	struct platform_device *dmic_dev;
417 };
418 
419 static inline struct hdac_bus *sof_to_bus(struct snd_sof_dev *s)
420 {
421 	struct sof_intel_hda_dev *hda = s->pdata->hw_pdata;
422 
423 	return &hda->hbus.core;
424 }
425 
426 static inline struct hda_bus *sof_to_hbus(struct snd_sof_dev *s)
427 {
428 	struct sof_intel_hda_dev *hda = s->pdata->hw_pdata;
429 
430 	return &hda->hbus;
431 }
432 
433 struct sof_intel_hda_stream {
434 	struct snd_sof_dev *sdev;
435 	struct hdac_ext_stream hda_stream;
436 	struct sof_intel_stream stream;
437 	int host_reserved; /* reserve host DMA channel */
438 };
439 
440 #define hstream_to_sof_hda_stream(hstream) \
441 	container_of(hstream, struct sof_intel_hda_stream, hda_stream)
442 
443 #define bus_to_sof_hda(bus) \
444 	container_of(bus, struct sof_intel_hda_dev, hbus.core)
445 
446 #define SOF_STREAM_SD_OFFSET(s) \
447 	(SOF_HDA_ADSP_SD_ENTRY_SIZE * ((s)->index) \
448 	 + SOF_HDA_ADSP_LOADER_BASE)
449 
450 /*
451  * DSP Core services.
452  */
453 int hda_dsp_probe(struct snd_sof_dev *sdev);
454 int hda_dsp_remove(struct snd_sof_dev *sdev);
455 int hda_dsp_core_reset_enter(struct snd_sof_dev *sdev,
456 			     unsigned int core_mask);
457 int hda_dsp_core_reset_leave(struct snd_sof_dev *sdev,
458 			     unsigned int core_mask);
459 int hda_dsp_core_stall_reset(struct snd_sof_dev *sdev, unsigned int core_mask);
460 int hda_dsp_core_run(struct snd_sof_dev *sdev, unsigned int core_mask);
461 int hda_dsp_core_power_up(struct snd_sof_dev *sdev, unsigned int core_mask);
462 int hda_dsp_enable_core(struct snd_sof_dev *sdev, unsigned int core_mask);
463 int hda_dsp_core_power_down(struct snd_sof_dev *sdev, unsigned int core_mask);
464 bool hda_dsp_core_is_enabled(struct snd_sof_dev *sdev,
465 			     unsigned int core_mask);
466 int hda_dsp_core_reset_power_down(struct snd_sof_dev *sdev,
467 				  unsigned int core_mask);
468 void hda_dsp_ipc_int_enable(struct snd_sof_dev *sdev);
469 void hda_dsp_ipc_int_disable(struct snd_sof_dev *sdev);
470 
471 int hda_dsp_set_power_state(struct snd_sof_dev *sdev,
472 			    enum sof_d0_substate d0_substate);
473 
474 int hda_dsp_suspend(struct snd_sof_dev *sdev);
475 int hda_dsp_resume(struct snd_sof_dev *sdev);
476 int hda_dsp_runtime_suspend(struct snd_sof_dev *sdev);
477 int hda_dsp_runtime_resume(struct snd_sof_dev *sdev);
478 int hda_dsp_runtime_idle(struct snd_sof_dev *sdev);
479 int hda_dsp_set_hw_params_upon_resume(struct snd_sof_dev *sdev);
480 void hda_dsp_dump_skl(struct snd_sof_dev *sdev, u32 flags);
481 void hda_dsp_dump(struct snd_sof_dev *sdev, u32 flags);
482 void hda_ipc_dump(struct snd_sof_dev *sdev);
483 void hda_ipc_irq_dump(struct snd_sof_dev *sdev);
484 
485 /*
486  * DSP PCM Operations.
487  */
488 int hda_dsp_pcm_open(struct snd_sof_dev *sdev,
489 		     struct snd_pcm_substream *substream);
490 int hda_dsp_pcm_close(struct snd_sof_dev *sdev,
491 		      struct snd_pcm_substream *substream);
492 int hda_dsp_pcm_hw_params(struct snd_sof_dev *sdev,
493 			  struct snd_pcm_substream *substream,
494 			  struct snd_pcm_hw_params *params,
495 			  struct sof_ipc_stream_params *ipc_params);
496 int hda_dsp_stream_hw_free(struct snd_sof_dev *sdev,
497 			   struct snd_pcm_substream *substream);
498 int hda_dsp_pcm_trigger(struct snd_sof_dev *sdev,
499 			struct snd_pcm_substream *substream, int cmd);
500 snd_pcm_uframes_t hda_dsp_pcm_pointer(struct snd_sof_dev *sdev,
501 				      struct snd_pcm_substream *substream);
502 
503 /*
504  * DSP Stream Operations.
505  */
506 
507 int hda_dsp_stream_init(struct snd_sof_dev *sdev);
508 void hda_dsp_stream_free(struct snd_sof_dev *sdev);
509 int hda_dsp_stream_hw_params(struct snd_sof_dev *sdev,
510 			     struct hdac_ext_stream *stream,
511 			     struct snd_dma_buffer *dmab,
512 			     struct snd_pcm_hw_params *params);
513 int hda_dsp_stream_trigger(struct snd_sof_dev *sdev,
514 			   struct hdac_ext_stream *stream, int cmd);
515 irqreturn_t hda_dsp_stream_threaded_handler(int irq, void *context);
516 int hda_dsp_stream_setup_bdl(struct snd_sof_dev *sdev,
517 			     struct snd_dma_buffer *dmab,
518 			     struct hdac_stream *stream);
519 bool hda_dsp_check_ipc_irq(struct snd_sof_dev *sdev);
520 bool hda_dsp_check_stream_irq(struct snd_sof_dev *sdev);
521 
522 struct hdac_ext_stream *
523 	hda_dsp_stream_get(struct snd_sof_dev *sdev, int direction);
524 int hda_dsp_stream_put(struct snd_sof_dev *sdev, int direction, int stream_tag);
525 int hda_dsp_stream_spib_config(struct snd_sof_dev *sdev,
526 			       struct hdac_ext_stream *stream,
527 			       int enable, u32 size);
528 
529 void hda_ipc_msg_data(struct snd_sof_dev *sdev,
530 		      struct snd_pcm_substream *substream,
531 		      void *p, size_t sz);
532 int hda_ipc_pcm_params(struct snd_sof_dev *sdev,
533 		       struct snd_pcm_substream *substream,
534 		       const struct sof_ipc_pcm_params_reply *reply);
535 
536 /*
537  * DSP IPC Operations.
538  */
539 int hda_dsp_ipc_send_msg(struct snd_sof_dev *sdev,
540 			 struct snd_sof_ipc_msg *msg);
541 void hda_dsp_ipc_get_reply(struct snd_sof_dev *sdev);
542 int hda_dsp_ipc_get_mailbox_offset(struct snd_sof_dev *sdev);
543 int hda_dsp_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id);
544 
545 irqreturn_t hda_dsp_ipc_irq_thread(int irq, void *context);
546 int hda_dsp_ipc_cmd_done(struct snd_sof_dev *sdev, int dir);
547 
548 /*
549  * DSP Code loader.
550  */
551 int hda_dsp_cl_boot_firmware(struct snd_sof_dev *sdev);
552 int hda_dsp_cl_boot_firmware_skl(struct snd_sof_dev *sdev);
553 
554 /* pre and post fw run ops */
555 int hda_dsp_pre_fw_run(struct snd_sof_dev *sdev);
556 int hda_dsp_post_fw_run(struct snd_sof_dev *sdev);
557 
558 /*
559  * HDA Controller Operations.
560  */
561 int hda_dsp_ctrl_get_caps(struct snd_sof_dev *sdev);
562 void hda_dsp_ctrl_ppcap_enable(struct snd_sof_dev *sdev, bool enable);
563 void hda_dsp_ctrl_ppcap_int_enable(struct snd_sof_dev *sdev, bool enable);
564 int hda_dsp_ctrl_link_reset(struct snd_sof_dev *sdev, bool reset);
565 void hda_dsp_ctrl_misc_clock_gating(struct snd_sof_dev *sdev, bool enable);
566 int hda_dsp_ctrl_clock_power_gating(struct snd_sof_dev *sdev, bool enable);
567 int hda_dsp_ctrl_init_chip(struct snd_sof_dev *sdev, bool full_reset);
568 void hda_dsp_ctrl_stop_chip(struct snd_sof_dev *sdev);
569 /*
570  * HDA bus operations.
571  */
572 void sof_hda_bus_init(struct hdac_bus *bus, struct device *dev);
573 
574 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
575 /*
576  * HDA Codec operations.
577  */
578 void hda_codec_probe_bus(struct snd_sof_dev *sdev,
579 			 bool hda_codec_use_common_hdmi);
580 void hda_codec_jack_wake_enable(struct snd_sof_dev *sdev);
581 void hda_codec_jack_check(struct snd_sof_dev *sdev);
582 
583 #endif /* CONFIG_SND_SOC_SOF_HDA */
584 
585 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) && \
586 	(IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI) || \
587 	 IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI))
588 
589 void hda_codec_i915_display_power(struct snd_sof_dev *sdev, bool enable);
590 int hda_codec_i915_init(struct snd_sof_dev *sdev);
591 int hda_codec_i915_exit(struct snd_sof_dev *sdev);
592 
593 #else
594 
595 static inline void hda_codec_i915_display_power(struct snd_sof_dev *sdev,
596 						bool enable) { }
597 static inline int hda_codec_i915_init(struct snd_sof_dev *sdev) { return 0; }
598 static inline int hda_codec_i915_exit(struct snd_sof_dev *sdev) { return 0; }
599 
600 #endif
601 
602 /*
603  * Trace Control.
604  */
605 int hda_dsp_trace_init(struct snd_sof_dev *sdev, u32 *stream_tag);
606 int hda_dsp_trace_release(struct snd_sof_dev *sdev);
607 int hda_dsp_trace_trigger(struct snd_sof_dev *sdev, int cmd);
608 
609 /* common dai driver */
610 extern struct snd_soc_dai_driver skl_dai[];
611 
612 /*
613  * Platform Specific HW abstraction Ops.
614  */
615 extern const struct snd_sof_dsp_ops sof_apl_ops;
616 extern const struct snd_sof_dsp_ops sof_cnl_ops;
617 
618 extern const struct sof_intel_dsp_desc apl_chip_info;
619 extern const struct sof_intel_dsp_desc cnl_chip_info;
620 extern const struct sof_intel_dsp_desc skl_chip_info;
621 extern const struct sof_intel_dsp_desc icl_chip_info;
622 extern const struct sof_intel_dsp_desc tgl_chip_info;
623 extern const struct sof_intel_dsp_desc ehl_chip_info;
624 extern const struct sof_intel_dsp_desc jsl_chip_info;
625 
626 /* machine driver select */
627 void hda_machine_select(struct snd_sof_dev *sdev);
628 void hda_set_mach_params(const struct snd_soc_acpi_mach *mach,
629 			 struct device *dev);
630 
631 #endif
632