1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */ 2 /* 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * Copyright(c) 2017 Intel Corporation. All rights reserved. 7 * 8 * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com> 9 */ 10 11 #ifndef __SOF_INTEL_HDA_H 12 #define __SOF_INTEL_HDA_H 13 14 #include <sound/compress_driver.h> 15 #include <sound/hda_codec.h> 16 #include <sound/hdaudio_ext.h> 17 #include "shim.h" 18 19 /* PCI registers */ 20 #define PCI_TCSEL 0x44 21 #define PCI_PGCTL PCI_TCSEL 22 #define PCI_CGCTL 0x48 23 24 /* PCI_PGCTL bits */ 25 #define PCI_PGCTL_ADSPPGD BIT(2) 26 #define PCI_PGCTL_LSRMD_MASK BIT(4) 27 28 /* PCI_CGCTL bits */ 29 #define PCI_CGCTL_MISCBDCGE_MASK BIT(6) 30 #define PCI_CGCTL_ADSPDCGE BIT(1) 31 32 /* Legacy HDA registers and bits used - widths are variable */ 33 #define SOF_HDA_GCAP 0x0 34 #define SOF_HDA_GCTL 0x8 35 /* accept unsol. response enable */ 36 #define SOF_HDA_GCTL_UNSOL BIT(8) 37 #define SOF_HDA_LLCH 0x14 38 #define SOF_HDA_INTCTL 0x20 39 #define SOF_HDA_INTSTS 0x24 40 #define SOF_HDA_WAKESTS 0x0E 41 #define SOF_HDA_WAKESTS_INT_MASK ((1 << 8) - 1) 42 #define SOF_HDA_RIRBSTS 0x5d 43 44 /* SOF_HDA_GCTL register bist */ 45 #define SOF_HDA_GCTL_RESET BIT(0) 46 47 /* SOF_HDA_INCTL regs */ 48 #define SOF_HDA_INT_GLOBAL_EN BIT(31) 49 #define SOF_HDA_INT_CTRL_EN BIT(30) 50 #define SOF_HDA_INT_ALL_STREAM 0xff 51 52 /* SOF_HDA_INTSTS regs */ 53 #define SOF_HDA_INTSTS_GIS BIT(31) 54 55 #define SOF_HDA_MAX_CAPS 10 56 #define SOF_HDA_CAP_ID_OFF 16 57 #define SOF_HDA_CAP_ID_MASK GENMASK(SOF_HDA_CAP_ID_OFF + 11,\ 58 SOF_HDA_CAP_ID_OFF) 59 #define SOF_HDA_CAP_NEXT_MASK 0xFFFF 60 61 #define SOF_HDA_GTS_CAP_ID 0x1 62 #define SOF_HDA_ML_CAP_ID 0x2 63 64 #define SOF_HDA_PP_CAP_ID 0x3 65 #define SOF_HDA_REG_PP_PPCH 0x10 66 #define SOF_HDA_REG_PP_PPCTL 0x04 67 #define SOF_HDA_REG_PP_PPSTS 0x08 68 #define SOF_HDA_PPCTL_PIE BIT(31) 69 #define SOF_HDA_PPCTL_GPROCEN BIT(30) 70 71 /*Vendor Specific Registers*/ 72 #define SOF_HDA_VS_D0I3C 0x104A 73 74 /* D0I3C Register fields */ 75 #define SOF_HDA_VS_D0I3C_CIP BIT(0) /* Command-In-Progress */ 76 #define SOF_HDA_VS_D0I3C_I3 BIT(2) /* D0i3 enable bit */ 77 78 /* DPIB entry size: 8 Bytes = 2 DWords */ 79 #define SOF_HDA_DPIB_ENTRY_SIZE 0x8 80 81 #define SOF_HDA_SPIB_CAP_ID 0x4 82 #define SOF_HDA_DRSM_CAP_ID 0x5 83 84 #define SOF_HDA_SPIB_BASE 0x08 85 #define SOF_HDA_SPIB_INTERVAL 0x08 86 #define SOF_HDA_SPIB_SPIB 0x00 87 #define SOF_HDA_SPIB_MAXFIFO 0x04 88 89 #define SOF_HDA_PPHC_BASE 0x10 90 #define SOF_HDA_PPHC_INTERVAL 0x10 91 92 #define SOF_HDA_PPLC_BASE 0x10 93 #define SOF_HDA_PPLC_MULTI 0x10 94 #define SOF_HDA_PPLC_INTERVAL 0x10 95 96 #define SOF_HDA_DRSM_BASE 0x08 97 #define SOF_HDA_DRSM_INTERVAL 0x08 98 99 /* Descriptor error interrupt */ 100 #define SOF_HDA_CL_DMA_SD_INT_DESC_ERR 0x10 101 102 /* FIFO error interrupt */ 103 #define SOF_HDA_CL_DMA_SD_INT_FIFO_ERR 0x08 104 105 /* Buffer completion interrupt */ 106 #define SOF_HDA_CL_DMA_SD_INT_COMPLETE 0x04 107 108 #define SOF_HDA_CL_DMA_SD_INT_MASK \ 109 (SOF_HDA_CL_DMA_SD_INT_DESC_ERR | \ 110 SOF_HDA_CL_DMA_SD_INT_FIFO_ERR | \ 111 SOF_HDA_CL_DMA_SD_INT_COMPLETE) 112 #define SOF_HDA_SD_CTL_DMA_START 0x02 /* Stream DMA start bit */ 113 114 /* Intel HD Audio Code Loader DMA Registers */ 115 #define SOF_HDA_ADSP_LOADER_BASE 0x80 116 #define SOF_HDA_ADSP_DPLBASE 0x70 117 #define SOF_HDA_ADSP_DPUBASE 0x74 118 #define SOF_HDA_ADSP_DPLBASE_ENABLE 0x01 119 120 /* Stream Registers */ 121 #define SOF_HDA_ADSP_REG_CL_SD_CTL 0x00 122 #define SOF_HDA_ADSP_REG_CL_SD_STS 0x03 123 #define SOF_HDA_ADSP_REG_CL_SD_LPIB 0x04 124 #define SOF_HDA_ADSP_REG_CL_SD_CBL 0x08 125 #define SOF_HDA_ADSP_REG_CL_SD_LVI 0x0C 126 #define SOF_HDA_ADSP_REG_CL_SD_FIFOW 0x0E 127 #define SOF_HDA_ADSP_REG_CL_SD_FIFOSIZE 0x10 128 #define SOF_HDA_ADSP_REG_CL_SD_FORMAT 0x12 129 #define SOF_HDA_ADSP_REG_CL_SD_FIFOL 0x14 130 #define SOF_HDA_ADSP_REG_CL_SD_BDLPL 0x18 131 #define SOF_HDA_ADSP_REG_CL_SD_BDLPU 0x1C 132 #define SOF_HDA_ADSP_SD_ENTRY_SIZE 0x20 133 134 /* CL: Software Position Based FIFO Capability Registers */ 135 #define SOF_DSP_REG_CL_SPBFIFO \ 136 (SOF_HDA_ADSP_LOADER_BASE + 0x20) 137 #define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCH 0x0 138 #define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCCTL 0x4 139 #define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPIB 0x8 140 #define SOF_HDA_ADSP_REG_CL_SPBFIFO_MAXFIFOS 0xc 141 142 /* Stream Number */ 143 #define SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT 20 144 #define SOF_HDA_CL_SD_CTL_STREAM_TAG_MASK \ 145 GENMASK(SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT + 3,\ 146 SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT) 147 148 #define HDA_DSP_HDA_BAR 0 149 #define HDA_DSP_PP_BAR 1 150 #define HDA_DSP_SPIB_BAR 2 151 #define HDA_DSP_DRSM_BAR 3 152 #define HDA_DSP_BAR 4 153 154 #define SRAM_WINDOW_OFFSET(x) (0x80000 + (x) * 0x20000) 155 156 #define HDA_DSP_MBOX_OFFSET SRAM_WINDOW_OFFSET(0) 157 158 #define HDA_DSP_PANIC_OFFSET(x) \ 159 (((x) & 0xFFFFFF) + HDA_DSP_MBOX_OFFSET) 160 161 /* SRAM window 0 FW "registers" */ 162 #define HDA_DSP_SRAM_REG_ROM_STATUS (HDA_DSP_MBOX_OFFSET + 0x0) 163 #define HDA_DSP_SRAM_REG_ROM_ERROR (HDA_DSP_MBOX_OFFSET + 0x4) 164 /* FW and ROM share offset 4 */ 165 #define HDA_DSP_SRAM_REG_FW_STATUS (HDA_DSP_MBOX_OFFSET + 0x4) 166 #define HDA_DSP_SRAM_REG_FW_TRACEP (HDA_DSP_MBOX_OFFSET + 0x8) 167 #define HDA_DSP_SRAM_REG_FW_END (HDA_DSP_MBOX_OFFSET + 0xc) 168 169 #define HDA_DSP_MBOX_UPLINK_OFFSET 0x81000 170 171 #define HDA_DSP_STREAM_RESET_TIMEOUT 300 172 /* 173 * Timeout in us, for setting the stream RUN bit, during 174 * start/stop the stream. The timeout expires if new RUN bit 175 * value cannot be read back within the specified time. 176 */ 177 #define HDA_DSP_STREAM_RUN_TIMEOUT 300 178 #define HDA_DSP_CL_TRIGGER_TIMEOUT 300 179 180 #define HDA_DSP_SPIB_ENABLE 1 181 #define HDA_DSP_SPIB_DISABLE 0 182 183 #define SOF_HDA_MAX_BUFFER_SIZE (32 * PAGE_SIZE) 184 185 #define HDA_DSP_STACK_DUMP_SIZE 32 186 187 /* ROM status/error values */ 188 #define HDA_DSP_ROM_STS_MASK GENMASK(23, 0) 189 #define HDA_DSP_ROM_INIT 0x1 190 #define HDA_DSP_ROM_FW_MANIFEST_LOADED 0x3 191 #define HDA_DSP_ROM_FW_FW_LOADED 0x4 192 #define HDA_DSP_ROM_FW_ENTERED 0x5 193 #define HDA_DSP_ROM_RFW_START 0xf 194 #define HDA_DSP_ROM_CSE_ERROR 40 195 #define HDA_DSP_ROM_CSE_WRONG_RESPONSE 41 196 #define HDA_DSP_ROM_IMR_TO_SMALL 42 197 #define HDA_DSP_ROM_BASE_FW_NOT_FOUND 43 198 #define HDA_DSP_ROM_CSE_VALIDATION_FAILED 44 199 #define HDA_DSP_ROM_IPC_FATAL_ERROR 45 200 #define HDA_DSP_ROM_L2_CACHE_ERROR 46 201 #define HDA_DSP_ROM_LOAD_OFFSET_TO_SMALL 47 202 #define HDA_DSP_ROM_API_PTR_INVALID 50 203 #define HDA_DSP_ROM_BASEFW_INCOMPAT 51 204 #define HDA_DSP_ROM_UNHANDLED_INTERRUPT 0xBEE00000 205 #define HDA_DSP_ROM_MEMORY_HOLE_ECC 0xECC00000 206 #define HDA_DSP_ROM_KERNEL_EXCEPTION 0xCAFE0000 207 #define HDA_DSP_ROM_USER_EXCEPTION 0xBEEF0000 208 #define HDA_DSP_ROM_UNEXPECTED_RESET 0xDECAF000 209 #define HDA_DSP_ROM_NULL_FW_ENTRY 0x4c4c4e55 210 #define HDA_DSP_IPC_PURGE_FW 0x01004000 211 212 /* various timeout values */ 213 #define HDA_DSP_PU_TIMEOUT 50 214 #define HDA_DSP_PD_TIMEOUT 50 215 #define HDA_DSP_RESET_TIMEOUT_US 50000 216 #define HDA_DSP_BASEFW_TIMEOUT_US 3000000 217 #define HDA_DSP_INIT_TIMEOUT_US 500000 218 #define HDA_DSP_CTRL_RESET_TIMEOUT 100 219 #define HDA_DSP_WAIT_TIMEOUT 500 /* 500 msec */ 220 #define HDA_DSP_REG_POLL_INTERVAL_US 500 /* 0.5 msec */ 221 #define HDA_DSP_REG_POLL_RETRY_COUNT 50 222 223 #define HDA_DSP_ADSPIC_IPC 1 224 #define HDA_DSP_ADSPIS_IPC 1 225 226 /* Intel HD Audio General DSP Registers */ 227 #define HDA_DSP_GEN_BASE 0x0 228 #define HDA_DSP_REG_ADSPCS (HDA_DSP_GEN_BASE + 0x04) 229 #define HDA_DSP_REG_ADSPIC (HDA_DSP_GEN_BASE + 0x08) 230 #define HDA_DSP_REG_ADSPIS (HDA_DSP_GEN_BASE + 0x0C) 231 #define HDA_DSP_REG_ADSPIC2 (HDA_DSP_GEN_BASE + 0x10) 232 #define HDA_DSP_REG_ADSPIS2 (HDA_DSP_GEN_BASE + 0x14) 233 234 /* Intel HD Audio Inter-Processor Communication Registers */ 235 #define HDA_DSP_IPC_BASE 0x40 236 #define HDA_DSP_REG_HIPCT (HDA_DSP_IPC_BASE + 0x00) 237 #define HDA_DSP_REG_HIPCTE (HDA_DSP_IPC_BASE + 0x04) 238 #define HDA_DSP_REG_HIPCI (HDA_DSP_IPC_BASE + 0x08) 239 #define HDA_DSP_REG_HIPCIE (HDA_DSP_IPC_BASE + 0x0C) 240 #define HDA_DSP_REG_HIPCCTL (HDA_DSP_IPC_BASE + 0x10) 241 242 /* Intel Vendor Specific Registers */ 243 #define HDA_VS_INTEL_EM2 0x1030 244 #define HDA_VS_INTEL_EM2_L1SEN BIT(13) 245 246 /* HIPCI */ 247 #define HDA_DSP_REG_HIPCI_BUSY BIT(31) 248 #define HDA_DSP_REG_HIPCI_MSG_MASK 0x7FFFFFFF 249 250 /* HIPCIE */ 251 #define HDA_DSP_REG_HIPCIE_DONE BIT(30) 252 #define HDA_DSP_REG_HIPCIE_MSG_MASK 0x3FFFFFFF 253 254 /* HIPCCTL */ 255 #define HDA_DSP_REG_HIPCCTL_DONE BIT(1) 256 #define HDA_DSP_REG_HIPCCTL_BUSY BIT(0) 257 258 /* HIPCT */ 259 #define HDA_DSP_REG_HIPCT_BUSY BIT(31) 260 #define HDA_DSP_REG_HIPCT_MSG_MASK 0x7FFFFFFF 261 262 /* HIPCTE */ 263 #define HDA_DSP_REG_HIPCTE_MSG_MASK 0x3FFFFFFF 264 265 #define HDA_DSP_ADSPIC_CL_DMA 0x2 266 #define HDA_DSP_ADSPIS_CL_DMA 0x2 267 268 /* Delay before scheduling D0i3 entry */ 269 #define BXT_D0I3_DELAY 5000 270 271 #define FW_CL_STREAM_NUMBER 0x1 272 273 /* ADSPCS - Audio DSP Control & Status */ 274 275 /* 276 * Core Reset - asserted high 277 * CRST Mask for a given core mask pattern, cm 278 */ 279 #define HDA_DSP_ADSPCS_CRST_SHIFT 0 280 #define HDA_DSP_ADSPCS_CRST_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CRST_SHIFT) 281 282 /* 283 * Core run/stall - when set to '1' core is stalled 284 * CSTALL Mask for a given core mask pattern, cm 285 */ 286 #define HDA_DSP_ADSPCS_CSTALL_SHIFT 8 287 #define HDA_DSP_ADSPCS_CSTALL_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CSTALL_SHIFT) 288 289 /* 290 * Set Power Active - when set to '1' turn cores on 291 * SPA Mask for a given core mask pattern, cm 292 */ 293 #define HDA_DSP_ADSPCS_SPA_SHIFT 16 294 #define HDA_DSP_ADSPCS_SPA_MASK(cm) ((cm) << HDA_DSP_ADSPCS_SPA_SHIFT) 295 296 /* 297 * Current Power Active - power status of cores, set by hardware 298 * CPA Mask for a given core mask pattern, cm 299 */ 300 #define HDA_DSP_ADSPCS_CPA_SHIFT 24 301 #define HDA_DSP_ADSPCS_CPA_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CPA_SHIFT) 302 303 /* Mask for a given core index, c = 0.. number of supported cores - 1 */ 304 #define HDA_DSP_CORE_MASK(c) BIT(c) 305 306 /* 307 * Mask for a given number of cores 308 * nc = number of supported cores 309 */ 310 #define SOF_DSP_CORES_MASK(nc) GENMASK(((nc) - 1), 0) 311 312 /* Intel HD Audio Inter-Processor Communication Registers for Cannonlake*/ 313 #define CNL_DSP_IPC_BASE 0xc0 314 #define CNL_DSP_REG_HIPCTDR (CNL_DSP_IPC_BASE + 0x00) 315 #define CNL_DSP_REG_HIPCTDA (CNL_DSP_IPC_BASE + 0x04) 316 #define CNL_DSP_REG_HIPCTDD (CNL_DSP_IPC_BASE + 0x08) 317 #define CNL_DSP_REG_HIPCIDR (CNL_DSP_IPC_BASE + 0x10) 318 #define CNL_DSP_REG_HIPCIDA (CNL_DSP_IPC_BASE + 0x14) 319 #define CNL_DSP_REG_HIPCIDD (CNL_DSP_IPC_BASE + 0x18) 320 #define CNL_DSP_REG_HIPCCTL (CNL_DSP_IPC_BASE + 0x28) 321 322 /* HIPCI */ 323 #define CNL_DSP_REG_HIPCIDR_BUSY BIT(31) 324 #define CNL_DSP_REG_HIPCIDR_MSG_MASK 0x7FFFFFFF 325 326 /* HIPCIE */ 327 #define CNL_DSP_REG_HIPCIDA_DONE BIT(31) 328 #define CNL_DSP_REG_HIPCIDA_MSG_MASK 0x7FFFFFFF 329 330 /* HIPCCTL */ 331 #define CNL_DSP_REG_HIPCCTL_DONE BIT(1) 332 #define CNL_DSP_REG_HIPCCTL_BUSY BIT(0) 333 334 /* HIPCT */ 335 #define CNL_DSP_REG_HIPCTDR_BUSY BIT(31) 336 #define CNL_DSP_REG_HIPCTDR_MSG_MASK 0x7FFFFFFF 337 338 /* HIPCTDA */ 339 #define CNL_DSP_REG_HIPCTDA_DONE BIT(31) 340 #define CNL_DSP_REG_HIPCTDA_MSG_MASK 0x7FFFFFFF 341 342 /* HIPCTDD */ 343 #define CNL_DSP_REG_HIPCTDD_MSG_MASK 0x7FFFFFFF 344 345 /* BDL */ 346 #define HDA_DSP_BDL_SIZE 4096 347 #define HDA_DSP_MAX_BDL_ENTRIES \ 348 (HDA_DSP_BDL_SIZE / sizeof(struct sof_intel_dsp_bdl)) 349 350 /* Number of DAIs */ 351 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) 352 #define SOF_SKL_NUM_DAIS 15 353 #else 354 #define SOF_SKL_NUM_DAIS 8 355 #endif 356 357 /* Intel HD Audio SRAM Window 0*/ 358 #define HDA_ADSP_SRAM0_BASE_SKL 0x8000 359 360 /* Firmware status window */ 361 #define HDA_ADSP_FW_STATUS_SKL HDA_ADSP_SRAM0_BASE_SKL 362 #define HDA_ADSP_ERROR_CODE_SKL (HDA_ADSP_FW_STATUS_SKL + 0x4) 363 364 /* Host Device Memory Space */ 365 #define APL_SSP_BASE_OFFSET 0x2000 366 #define CNL_SSP_BASE_OFFSET 0x10000 367 368 /* Host Device Memory Size of a Single SSP */ 369 #define SSP_DEV_MEM_SIZE 0x1000 370 371 /* SSP Count of the Platform */ 372 #define APL_SSP_COUNT 6 373 #define CNL_SSP_COUNT 3 374 #define ICL_SSP_COUNT 6 375 376 /* SSP Registers */ 377 #define SSP_SSC1_OFFSET 0x4 378 #define SSP_SET_SCLK_SLAVE BIT(25) 379 #define SSP_SET_SFRM_SLAVE BIT(24) 380 #define SSP_SET_SLAVE (SSP_SET_SCLK_SLAVE | SSP_SET_SFRM_SLAVE) 381 382 #define HDA_IDISP_CODEC(x) ((x) & BIT(2)) 383 384 struct sof_intel_dsp_bdl { 385 __le32 addr_l; 386 __le32 addr_h; 387 __le32 size; 388 __le32 ioc; 389 } __attribute((packed)); 390 391 #define SOF_HDA_PLAYBACK_STREAMS 16 392 #define SOF_HDA_CAPTURE_STREAMS 16 393 #define SOF_HDA_PLAYBACK 0 394 #define SOF_HDA_CAPTURE 1 395 396 /* 397 * Time in ms for opportunistic D0I3 entry delay. 398 * This has been deliberately chosen to be long to avoid race conditions. 399 * Could be optimized in future. 400 */ 401 #define SOF_HDA_D0I3_WORK_DELAY_MS 5000 402 403 /* HDA DSP D0 substate */ 404 enum sof_hda_D0_substate { 405 SOF_HDA_DSP_PM_D0I0, /* default D0 substate */ 406 SOF_HDA_DSP_PM_D0I3, /* low power D0 substate */ 407 }; 408 409 /* represents DSP HDA controller frontend - i.e. host facing control */ 410 struct sof_intel_hda_dev { 411 412 struct hda_bus hbus; 413 414 /* hw config */ 415 const struct sof_intel_dsp_desc *desc; 416 417 /* trace */ 418 struct hdac_ext_stream *dtrace_stream; 419 420 /* if position update IPC needed */ 421 u32 no_ipc_position; 422 423 /* the maximum number of streams (playback + capture) supported */ 424 u32 stream_max; 425 426 /* PM related */ 427 bool l1_support_changed;/* during suspend, is L1SEN changed or not */ 428 429 /* DMIC device */ 430 struct platform_device *dmic_dev; 431 432 /* delayed work to enter D0I3 opportunistically */ 433 struct delayed_work d0i3_work; 434 }; 435 436 static inline struct hdac_bus *sof_to_bus(struct snd_sof_dev *s) 437 { 438 struct sof_intel_hda_dev *hda = s->pdata->hw_pdata; 439 440 return &hda->hbus.core; 441 } 442 443 static inline struct hda_bus *sof_to_hbus(struct snd_sof_dev *s) 444 { 445 struct sof_intel_hda_dev *hda = s->pdata->hw_pdata; 446 447 return &hda->hbus; 448 } 449 450 struct sof_intel_hda_stream { 451 struct snd_sof_dev *sdev; 452 struct hdac_ext_stream hda_stream; 453 struct sof_intel_stream stream; 454 int host_reserved; /* reserve host DMA channel */ 455 }; 456 457 #define hstream_to_sof_hda_stream(hstream) \ 458 container_of(hstream, struct sof_intel_hda_stream, hda_stream) 459 460 #define bus_to_sof_hda(bus) \ 461 container_of(bus, struct sof_intel_hda_dev, hbus.core) 462 463 #define SOF_STREAM_SD_OFFSET(s) \ 464 (SOF_HDA_ADSP_SD_ENTRY_SIZE * ((s)->index) \ 465 + SOF_HDA_ADSP_LOADER_BASE) 466 467 /* 468 * DSP Core services. 469 */ 470 int hda_dsp_probe(struct snd_sof_dev *sdev); 471 int hda_dsp_remove(struct snd_sof_dev *sdev); 472 int hda_dsp_core_reset_enter(struct snd_sof_dev *sdev, 473 unsigned int core_mask); 474 int hda_dsp_core_reset_leave(struct snd_sof_dev *sdev, 475 unsigned int core_mask); 476 int hda_dsp_core_stall_reset(struct snd_sof_dev *sdev, unsigned int core_mask); 477 int hda_dsp_core_run(struct snd_sof_dev *sdev, unsigned int core_mask); 478 int hda_dsp_core_power_up(struct snd_sof_dev *sdev, unsigned int core_mask); 479 int hda_dsp_enable_core(struct snd_sof_dev *sdev, unsigned int core_mask); 480 int hda_dsp_core_power_down(struct snd_sof_dev *sdev, unsigned int core_mask); 481 bool hda_dsp_core_is_enabled(struct snd_sof_dev *sdev, 482 unsigned int core_mask); 483 int hda_dsp_core_reset_power_down(struct snd_sof_dev *sdev, 484 unsigned int core_mask); 485 void hda_dsp_ipc_int_enable(struct snd_sof_dev *sdev); 486 void hda_dsp_ipc_int_disable(struct snd_sof_dev *sdev); 487 488 int hda_dsp_set_power_state(struct snd_sof_dev *sdev, 489 const struct sof_dsp_power_state *target_state); 490 491 int hda_dsp_suspend(struct snd_sof_dev *sdev, u32 target_state); 492 int hda_dsp_resume(struct snd_sof_dev *sdev); 493 int hda_dsp_runtime_suspend(struct snd_sof_dev *sdev); 494 int hda_dsp_runtime_resume(struct snd_sof_dev *sdev); 495 int hda_dsp_runtime_idle(struct snd_sof_dev *sdev); 496 int hda_dsp_set_hw_params_upon_resume(struct snd_sof_dev *sdev); 497 void hda_dsp_dump_skl(struct snd_sof_dev *sdev, u32 flags); 498 void hda_dsp_dump(struct snd_sof_dev *sdev, u32 flags); 499 void hda_ipc_dump(struct snd_sof_dev *sdev); 500 void hda_ipc_irq_dump(struct snd_sof_dev *sdev); 501 void hda_dsp_d0i3_work(struct work_struct *work); 502 503 /* 504 * DSP PCM Operations. 505 */ 506 u32 hda_dsp_get_mult_div(struct snd_sof_dev *sdev, int rate); 507 u32 hda_dsp_get_bits(struct snd_sof_dev *sdev, int sample_bits); 508 int hda_dsp_pcm_open(struct snd_sof_dev *sdev, 509 struct snd_pcm_substream *substream); 510 int hda_dsp_pcm_close(struct snd_sof_dev *sdev, 511 struct snd_pcm_substream *substream); 512 int hda_dsp_pcm_hw_params(struct snd_sof_dev *sdev, 513 struct snd_pcm_substream *substream, 514 struct snd_pcm_hw_params *params, 515 struct sof_ipc_stream_params *ipc_params); 516 int hda_dsp_stream_hw_free(struct snd_sof_dev *sdev, 517 struct snd_pcm_substream *substream); 518 int hda_dsp_pcm_trigger(struct snd_sof_dev *sdev, 519 struct snd_pcm_substream *substream, int cmd); 520 snd_pcm_uframes_t hda_dsp_pcm_pointer(struct snd_sof_dev *sdev, 521 struct snd_pcm_substream *substream); 522 523 /* 524 * DSP Stream Operations. 525 */ 526 527 int hda_dsp_stream_init(struct snd_sof_dev *sdev); 528 void hda_dsp_stream_free(struct snd_sof_dev *sdev); 529 int hda_dsp_stream_hw_params(struct snd_sof_dev *sdev, 530 struct hdac_ext_stream *stream, 531 struct snd_dma_buffer *dmab, 532 struct snd_pcm_hw_params *params); 533 int hda_dsp_stream_trigger(struct snd_sof_dev *sdev, 534 struct hdac_ext_stream *stream, int cmd); 535 irqreturn_t hda_dsp_stream_threaded_handler(int irq, void *context); 536 int hda_dsp_stream_setup_bdl(struct snd_sof_dev *sdev, 537 struct snd_dma_buffer *dmab, 538 struct hdac_stream *stream); 539 bool hda_dsp_check_ipc_irq(struct snd_sof_dev *sdev); 540 bool hda_dsp_check_stream_irq(struct snd_sof_dev *sdev); 541 542 struct hdac_ext_stream * 543 hda_dsp_stream_get(struct snd_sof_dev *sdev, int direction); 544 int hda_dsp_stream_put(struct snd_sof_dev *sdev, int direction, int stream_tag); 545 int hda_dsp_stream_spib_config(struct snd_sof_dev *sdev, 546 struct hdac_ext_stream *stream, 547 int enable, u32 size); 548 549 void hda_ipc_msg_data(struct snd_sof_dev *sdev, 550 struct snd_pcm_substream *substream, 551 void *p, size_t sz); 552 int hda_ipc_pcm_params(struct snd_sof_dev *sdev, 553 struct snd_pcm_substream *substream, 554 const struct sof_ipc_pcm_params_reply *reply); 555 556 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_PROBES) 557 /* 558 * Probe Compress Operations. 559 */ 560 int hda_probe_compr_assign(struct snd_sof_dev *sdev, 561 struct snd_compr_stream *cstream, 562 struct snd_soc_dai *dai); 563 int hda_probe_compr_free(struct snd_sof_dev *sdev, 564 struct snd_compr_stream *cstream, 565 struct snd_soc_dai *dai); 566 int hda_probe_compr_set_params(struct snd_sof_dev *sdev, 567 struct snd_compr_stream *cstream, 568 struct snd_compr_params *params, 569 struct snd_soc_dai *dai); 570 int hda_probe_compr_trigger(struct snd_sof_dev *sdev, 571 struct snd_compr_stream *cstream, int cmd, 572 struct snd_soc_dai *dai); 573 int hda_probe_compr_pointer(struct snd_sof_dev *sdev, 574 struct snd_compr_stream *cstream, 575 struct snd_compr_tstamp *tstamp, 576 struct snd_soc_dai *dai); 577 #endif 578 579 /* 580 * DSP IPC Operations. 581 */ 582 int hda_dsp_ipc_send_msg(struct snd_sof_dev *sdev, 583 struct snd_sof_ipc_msg *msg); 584 void hda_dsp_ipc_get_reply(struct snd_sof_dev *sdev); 585 int hda_dsp_ipc_get_mailbox_offset(struct snd_sof_dev *sdev); 586 int hda_dsp_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id); 587 588 irqreturn_t hda_dsp_ipc_irq_thread(int irq, void *context); 589 int hda_dsp_ipc_cmd_done(struct snd_sof_dev *sdev, int dir); 590 591 /* 592 * DSP Code loader. 593 */ 594 int hda_dsp_cl_boot_firmware(struct snd_sof_dev *sdev); 595 int hda_dsp_cl_boot_firmware_skl(struct snd_sof_dev *sdev); 596 597 /* pre and post fw run ops */ 598 int hda_dsp_pre_fw_run(struct snd_sof_dev *sdev); 599 int hda_dsp_post_fw_run(struct snd_sof_dev *sdev); 600 601 /* 602 * HDA Controller Operations. 603 */ 604 int hda_dsp_ctrl_get_caps(struct snd_sof_dev *sdev); 605 void hda_dsp_ctrl_ppcap_enable(struct snd_sof_dev *sdev, bool enable); 606 void hda_dsp_ctrl_ppcap_int_enable(struct snd_sof_dev *sdev, bool enable); 607 int hda_dsp_ctrl_link_reset(struct snd_sof_dev *sdev, bool reset); 608 void hda_dsp_ctrl_misc_clock_gating(struct snd_sof_dev *sdev, bool enable); 609 int hda_dsp_ctrl_clock_power_gating(struct snd_sof_dev *sdev, bool enable); 610 int hda_dsp_ctrl_init_chip(struct snd_sof_dev *sdev, bool full_reset); 611 void hda_dsp_ctrl_stop_chip(struct snd_sof_dev *sdev); 612 /* 613 * HDA bus operations. 614 */ 615 void sof_hda_bus_init(struct hdac_bus *bus, struct device *dev); 616 617 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) 618 /* 619 * HDA Codec operations. 620 */ 621 void hda_codec_probe_bus(struct snd_sof_dev *sdev, 622 bool hda_codec_use_common_hdmi); 623 void hda_codec_jack_wake_enable(struct snd_sof_dev *sdev); 624 void hda_codec_jack_check(struct snd_sof_dev *sdev); 625 626 #endif /* CONFIG_SND_SOC_SOF_HDA */ 627 628 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) && \ 629 (IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI) || \ 630 IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) 631 632 void hda_codec_i915_display_power(struct snd_sof_dev *sdev, bool enable); 633 int hda_codec_i915_init(struct snd_sof_dev *sdev); 634 int hda_codec_i915_exit(struct snd_sof_dev *sdev); 635 636 #else 637 638 static inline void hda_codec_i915_display_power(struct snd_sof_dev *sdev, 639 bool enable) { } 640 static inline int hda_codec_i915_init(struct snd_sof_dev *sdev) { return 0; } 641 static inline int hda_codec_i915_exit(struct snd_sof_dev *sdev) { return 0; } 642 643 #endif 644 645 /* 646 * Trace Control. 647 */ 648 int hda_dsp_trace_init(struct snd_sof_dev *sdev, u32 *stream_tag); 649 int hda_dsp_trace_release(struct snd_sof_dev *sdev); 650 int hda_dsp_trace_trigger(struct snd_sof_dev *sdev, int cmd); 651 652 /* common dai driver */ 653 extern struct snd_soc_dai_driver skl_dai[]; 654 655 /* 656 * Platform Specific HW abstraction Ops. 657 */ 658 extern const struct snd_sof_dsp_ops sof_apl_ops; 659 extern const struct snd_sof_dsp_ops sof_cnl_ops; 660 661 extern const struct sof_intel_dsp_desc apl_chip_info; 662 extern const struct sof_intel_dsp_desc cnl_chip_info; 663 extern const struct sof_intel_dsp_desc skl_chip_info; 664 extern const struct sof_intel_dsp_desc icl_chip_info; 665 extern const struct sof_intel_dsp_desc tgl_chip_info; 666 extern const struct sof_intel_dsp_desc ehl_chip_info; 667 extern const struct sof_intel_dsp_desc jsl_chip_info; 668 669 /* machine driver select */ 670 void hda_machine_select(struct snd_sof_dev *sdev); 671 void hda_set_mach_params(const struct snd_soc_acpi_mach *mach, 672 struct device *dev); 673 674 #endif 675