1e149ca29SPierre-Louis Bossart /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ 2dd96dacaSLiam Girdwood /* 3dd96dacaSLiam Girdwood * This file is provided under a dual BSD/GPLv2 license. When using or 4dd96dacaSLiam Girdwood * redistributing this file, you may do so under either license. 5dd96dacaSLiam Girdwood * 6dd96dacaSLiam Girdwood * Copyright(c) 2017 Intel Corporation. All rights reserved. 7dd96dacaSLiam Girdwood * 8dd96dacaSLiam Girdwood * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com> 9dd96dacaSLiam Girdwood */ 10dd96dacaSLiam Girdwood 11dd96dacaSLiam Girdwood #ifndef __SOF_INTEL_HDA_H 12dd96dacaSLiam Girdwood #define __SOF_INTEL_HDA_H 13dd96dacaSLiam Girdwood 1451dfed1eSPierre-Louis Bossart #include <linux/soundwire/sdw.h> 1551dfed1eSPierre-Louis Bossart #include <linux/soundwire/sdw_intel.h> 164c414da9SCezary Rojewski #include <sound/compress_driver.h> 17dd96dacaSLiam Girdwood #include <sound/hda_codec.h> 18dd96dacaSLiam Girdwood #include <sound/hdaudio_ext.h> 193dc0d709SPeter Ujfalusi #include "../sof-client-probes.h" 20051744b1SRanjani Sridharan #include "../sof-audio.h" 21dd96dacaSLiam Girdwood #include "shim.h" 22dd96dacaSLiam Girdwood 23dd96dacaSLiam Girdwood /* PCI registers */ 24dd96dacaSLiam Girdwood #define PCI_TCSEL 0x44 25dd96dacaSLiam Girdwood #define PCI_PGCTL PCI_TCSEL 26dd96dacaSLiam Girdwood #define PCI_CGCTL 0x48 27dd96dacaSLiam Girdwood 28dd96dacaSLiam Girdwood /* PCI_PGCTL bits */ 29dd96dacaSLiam Girdwood #define PCI_PGCTL_ADSPPGD BIT(2) 30dd96dacaSLiam Girdwood #define PCI_PGCTL_LSRMD_MASK BIT(4) 31dd96dacaSLiam Girdwood 32dd96dacaSLiam Girdwood /* PCI_CGCTL bits */ 33dd96dacaSLiam Girdwood #define PCI_CGCTL_MISCBDCGE_MASK BIT(6) 34dd96dacaSLiam Girdwood #define PCI_CGCTL_ADSPDCGE BIT(1) 35dd96dacaSLiam Girdwood 36dd96dacaSLiam Girdwood /* Legacy HDA registers and bits used - widths are variable */ 37dd96dacaSLiam Girdwood #define SOF_HDA_GCAP 0x0 38dd96dacaSLiam Girdwood #define SOF_HDA_GCTL 0x8 39dd96dacaSLiam Girdwood /* accept unsol. response enable */ 40dd96dacaSLiam Girdwood #define SOF_HDA_GCTL_UNSOL BIT(8) 41dd96dacaSLiam Girdwood #define SOF_HDA_LLCH 0x14 42dd96dacaSLiam Girdwood #define SOF_HDA_INTCTL 0x20 43dd96dacaSLiam Girdwood #define SOF_HDA_INTSTS 0x24 44dd96dacaSLiam Girdwood #define SOF_HDA_WAKESTS 0x0E 45dd96dacaSLiam Girdwood #define SOF_HDA_WAKESTS_INT_MASK ((1 << 8) - 1) 46dd96dacaSLiam Girdwood #define SOF_HDA_RIRBSTS 0x5d 47dd96dacaSLiam Girdwood 48dd96dacaSLiam Girdwood /* SOF_HDA_GCTL register bist */ 49dd96dacaSLiam Girdwood #define SOF_HDA_GCTL_RESET BIT(0) 50dd96dacaSLiam Girdwood 517c11af9fSBard Liao /* SOF_HDA_INCTL regs */ 52dd96dacaSLiam Girdwood #define SOF_HDA_INT_GLOBAL_EN BIT(31) 53dd96dacaSLiam Girdwood #define SOF_HDA_INT_CTRL_EN BIT(30) 54dd96dacaSLiam Girdwood #define SOF_HDA_INT_ALL_STREAM 0xff 55dd96dacaSLiam Girdwood 567c11af9fSBard Liao /* SOF_HDA_INTSTS regs */ 577c11af9fSBard Liao #define SOF_HDA_INTSTS_GIS BIT(31) 587c11af9fSBard Liao 59dd96dacaSLiam Girdwood #define SOF_HDA_MAX_CAPS 10 60dd96dacaSLiam Girdwood #define SOF_HDA_CAP_ID_OFF 16 61dd96dacaSLiam Girdwood #define SOF_HDA_CAP_ID_MASK GENMASK(SOF_HDA_CAP_ID_OFF + 11,\ 62dd96dacaSLiam Girdwood SOF_HDA_CAP_ID_OFF) 63dd96dacaSLiam Girdwood #define SOF_HDA_CAP_NEXT_MASK 0xFFFF 64dd96dacaSLiam Girdwood 65dd96dacaSLiam Girdwood #define SOF_HDA_GTS_CAP_ID 0x1 66dd96dacaSLiam Girdwood #define SOF_HDA_ML_CAP_ID 0x2 67dd96dacaSLiam Girdwood 68dd96dacaSLiam Girdwood #define SOF_HDA_PP_CAP_ID 0x3 69dd96dacaSLiam Girdwood #define SOF_HDA_REG_PP_PPCH 0x10 70dd96dacaSLiam Girdwood #define SOF_HDA_REG_PP_PPCTL 0x04 71f1fd9d0eSKai Vehmanen #define SOF_HDA_REG_PP_PPSTS 0x08 72dd96dacaSLiam Girdwood #define SOF_HDA_PPCTL_PIE BIT(31) 73dd96dacaSLiam Girdwood #define SOF_HDA_PPCTL_GPROCEN BIT(30) 74dd96dacaSLiam Girdwood 7562f8f766SKeyon Jie /*Vendor Specific Registers*/ 7662f8f766SKeyon Jie #define SOF_HDA_VS_D0I3C 0x104A 7762f8f766SKeyon Jie 7862f8f766SKeyon Jie /* D0I3C Register fields */ 7962f8f766SKeyon Jie #define SOF_HDA_VS_D0I3C_CIP BIT(0) /* Command-In-Progress */ 8062f8f766SKeyon Jie #define SOF_HDA_VS_D0I3C_I3 BIT(2) /* D0i3 enable bit */ 8162f8f766SKeyon Jie 82dd96dacaSLiam Girdwood /* DPIB entry size: 8 Bytes = 2 DWords */ 83dd96dacaSLiam Girdwood #define SOF_HDA_DPIB_ENTRY_SIZE 0x8 84dd96dacaSLiam Girdwood 85dd96dacaSLiam Girdwood #define SOF_HDA_SPIB_CAP_ID 0x4 86dd96dacaSLiam Girdwood #define SOF_HDA_DRSM_CAP_ID 0x5 87dd96dacaSLiam Girdwood 88dd96dacaSLiam Girdwood #define SOF_HDA_SPIB_BASE 0x08 89dd96dacaSLiam Girdwood #define SOF_HDA_SPIB_INTERVAL 0x08 90dd96dacaSLiam Girdwood #define SOF_HDA_SPIB_SPIB 0x00 91dd96dacaSLiam Girdwood #define SOF_HDA_SPIB_MAXFIFO 0x04 92dd96dacaSLiam Girdwood 93dd96dacaSLiam Girdwood #define SOF_HDA_PPHC_BASE 0x10 94dd96dacaSLiam Girdwood #define SOF_HDA_PPHC_INTERVAL 0x10 95dd96dacaSLiam Girdwood 96dd96dacaSLiam Girdwood #define SOF_HDA_PPLC_BASE 0x10 97dd96dacaSLiam Girdwood #define SOF_HDA_PPLC_MULTI 0x10 98dd96dacaSLiam Girdwood #define SOF_HDA_PPLC_INTERVAL 0x10 99dd96dacaSLiam Girdwood 100dd96dacaSLiam Girdwood #define SOF_HDA_DRSM_BASE 0x08 101dd96dacaSLiam Girdwood #define SOF_HDA_DRSM_INTERVAL 0x08 102dd96dacaSLiam Girdwood 103dd96dacaSLiam Girdwood /* Descriptor error interrupt */ 104dd96dacaSLiam Girdwood #define SOF_HDA_CL_DMA_SD_INT_DESC_ERR 0x10 105dd96dacaSLiam Girdwood 106dd96dacaSLiam Girdwood /* FIFO error interrupt */ 107dd96dacaSLiam Girdwood #define SOF_HDA_CL_DMA_SD_INT_FIFO_ERR 0x08 108dd96dacaSLiam Girdwood 109dd96dacaSLiam Girdwood /* Buffer completion interrupt */ 110dd96dacaSLiam Girdwood #define SOF_HDA_CL_DMA_SD_INT_COMPLETE 0x04 111dd96dacaSLiam Girdwood 112dd96dacaSLiam Girdwood #define SOF_HDA_CL_DMA_SD_INT_MASK \ 113dd96dacaSLiam Girdwood (SOF_HDA_CL_DMA_SD_INT_DESC_ERR | \ 114dd96dacaSLiam Girdwood SOF_HDA_CL_DMA_SD_INT_FIFO_ERR | \ 115dd96dacaSLiam Girdwood SOF_HDA_CL_DMA_SD_INT_COMPLETE) 116dd96dacaSLiam Girdwood #define SOF_HDA_SD_CTL_DMA_START 0x02 /* Stream DMA start bit */ 117dd96dacaSLiam Girdwood 118dd96dacaSLiam Girdwood /* Intel HD Audio Code Loader DMA Registers */ 119dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_LOADER_BASE 0x80 120dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_DPLBASE 0x70 121dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_DPUBASE 0x74 122dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_DPLBASE_ENABLE 0x01 123dd96dacaSLiam Girdwood 124dd96dacaSLiam Girdwood /* Stream Registers */ 125dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SD_CTL 0x00 126dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SD_STS 0x03 127dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SD_LPIB 0x04 128dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SD_CBL 0x08 129dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SD_LVI 0x0C 130dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SD_FIFOW 0x0E 131dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SD_FIFOSIZE 0x10 132dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SD_FORMAT 0x12 133dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SD_FIFOL 0x14 134dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SD_BDLPL 0x18 135dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SD_BDLPU 0x1C 136dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_SD_ENTRY_SIZE 0x20 137dd96dacaSLiam Girdwood 138dd96dacaSLiam Girdwood /* CL: Software Position Based FIFO Capability Registers */ 139dd96dacaSLiam Girdwood #define SOF_DSP_REG_CL_SPBFIFO \ 140dd96dacaSLiam Girdwood (SOF_HDA_ADSP_LOADER_BASE + 0x20) 141dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCH 0x0 142dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCCTL 0x4 143dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPIB 0x8 144dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SPBFIFO_MAXFIFOS 0xc 145dd96dacaSLiam Girdwood 146dd96dacaSLiam Girdwood /* Stream Number */ 147dd96dacaSLiam Girdwood #define SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT 20 148dd96dacaSLiam Girdwood #define SOF_HDA_CL_SD_CTL_STREAM_TAG_MASK \ 149dd96dacaSLiam Girdwood GENMASK(SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT + 3,\ 150dd96dacaSLiam Girdwood SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT) 151dd96dacaSLiam Girdwood 152dd96dacaSLiam Girdwood #define HDA_DSP_HDA_BAR 0 153dd96dacaSLiam Girdwood #define HDA_DSP_PP_BAR 1 154dd96dacaSLiam Girdwood #define HDA_DSP_SPIB_BAR 2 155dd96dacaSLiam Girdwood #define HDA_DSP_DRSM_BAR 3 156dd96dacaSLiam Girdwood #define HDA_DSP_BAR 4 157dd96dacaSLiam Girdwood 158dd96dacaSLiam Girdwood #define SRAM_WINDOW_OFFSET(x) (0x80000 + (x) * 0x20000) 159dd96dacaSLiam Girdwood 160dd96dacaSLiam Girdwood #define HDA_DSP_MBOX_OFFSET SRAM_WINDOW_OFFSET(0) 161dd96dacaSLiam Girdwood 162dd96dacaSLiam Girdwood #define HDA_DSP_PANIC_OFFSET(x) \ 163dd96dacaSLiam Girdwood (((x) & 0xFFFFFF) + HDA_DSP_MBOX_OFFSET) 164dd96dacaSLiam Girdwood 165dd96dacaSLiam Girdwood /* SRAM window 0 FW "registers" */ 166dd96dacaSLiam Girdwood #define HDA_DSP_SRAM_REG_ROM_STATUS (HDA_DSP_MBOX_OFFSET + 0x0) 167dd96dacaSLiam Girdwood #define HDA_DSP_SRAM_REG_ROM_ERROR (HDA_DSP_MBOX_OFFSET + 0x4) 168dd96dacaSLiam Girdwood /* FW and ROM share offset 4 */ 169dd96dacaSLiam Girdwood #define HDA_DSP_SRAM_REG_FW_STATUS (HDA_DSP_MBOX_OFFSET + 0x4) 170dd96dacaSLiam Girdwood #define HDA_DSP_SRAM_REG_FW_TRACEP (HDA_DSP_MBOX_OFFSET + 0x8) 171dd96dacaSLiam Girdwood #define HDA_DSP_SRAM_REG_FW_END (HDA_DSP_MBOX_OFFSET + 0xc) 172dd96dacaSLiam Girdwood 173dd96dacaSLiam Girdwood #define HDA_DSP_MBOX_UPLINK_OFFSET 0x81000 174dd96dacaSLiam Girdwood 175dd96dacaSLiam Girdwood #define HDA_DSP_STREAM_RESET_TIMEOUT 300 1767bcaf0f2SZhu Yingjiang /* 1777bcaf0f2SZhu Yingjiang * Timeout in us, for setting the stream RUN bit, during 1787bcaf0f2SZhu Yingjiang * start/stop the stream. The timeout expires if new RUN bit 1797bcaf0f2SZhu Yingjiang * value cannot be read back within the specified time. 1807bcaf0f2SZhu Yingjiang */ 1817bcaf0f2SZhu Yingjiang #define HDA_DSP_STREAM_RUN_TIMEOUT 300 182dd96dacaSLiam Girdwood 183dd96dacaSLiam Girdwood #define HDA_DSP_SPIB_ENABLE 1 184dd96dacaSLiam Girdwood #define HDA_DSP_SPIB_DISABLE 0 185dd96dacaSLiam Girdwood 186dd96dacaSLiam Girdwood #define SOF_HDA_MAX_BUFFER_SIZE (32 * PAGE_SIZE) 187dd96dacaSLiam Girdwood 188dd96dacaSLiam Girdwood #define HDA_DSP_STACK_DUMP_SIZE 32 189dd96dacaSLiam Girdwood 190dd96dacaSLiam Girdwood /* ROM status/error values */ 191184fdfcaSKeyon Jie #define HDA_DSP_ROM_STS_MASK GENMASK(23, 0) 192dd96dacaSLiam Girdwood #define HDA_DSP_ROM_INIT 0x1 193dd96dacaSLiam Girdwood #define HDA_DSP_ROM_FW_MANIFEST_LOADED 0x3 194dd96dacaSLiam Girdwood #define HDA_DSP_ROM_FW_FW_LOADED 0x4 195dd96dacaSLiam Girdwood #define HDA_DSP_ROM_FW_ENTERED 0x5 196dd96dacaSLiam Girdwood #define HDA_DSP_ROM_RFW_START 0xf 197dd96dacaSLiam Girdwood #define HDA_DSP_ROM_CSE_ERROR 40 198dd96dacaSLiam Girdwood #define HDA_DSP_ROM_CSE_WRONG_RESPONSE 41 199dd96dacaSLiam Girdwood #define HDA_DSP_ROM_IMR_TO_SMALL 42 200dd96dacaSLiam Girdwood #define HDA_DSP_ROM_BASE_FW_NOT_FOUND 43 201dd96dacaSLiam Girdwood #define HDA_DSP_ROM_CSE_VALIDATION_FAILED 44 202dd96dacaSLiam Girdwood #define HDA_DSP_ROM_IPC_FATAL_ERROR 45 203dd96dacaSLiam Girdwood #define HDA_DSP_ROM_L2_CACHE_ERROR 46 204dd96dacaSLiam Girdwood #define HDA_DSP_ROM_LOAD_OFFSET_TO_SMALL 47 205dd96dacaSLiam Girdwood #define HDA_DSP_ROM_API_PTR_INVALID 50 206dd96dacaSLiam Girdwood #define HDA_DSP_ROM_BASEFW_INCOMPAT 51 207dd96dacaSLiam Girdwood #define HDA_DSP_ROM_UNHANDLED_INTERRUPT 0xBEE00000 208dd96dacaSLiam Girdwood #define HDA_DSP_ROM_MEMORY_HOLE_ECC 0xECC00000 209dd96dacaSLiam Girdwood #define HDA_DSP_ROM_KERNEL_EXCEPTION 0xCAFE0000 210dd96dacaSLiam Girdwood #define HDA_DSP_ROM_USER_EXCEPTION 0xBEEF0000 211dd96dacaSLiam Girdwood #define HDA_DSP_ROM_UNEXPECTED_RESET 0xDECAF000 212dd96dacaSLiam Girdwood #define HDA_DSP_ROM_NULL_FW_ENTRY 0x4c4c4e55 2132a68ff84SPeter Ujfalusi 2142a68ff84SPeter Ujfalusi #define HDA_DSP_ROM_IPC_CONTROL 0x01000000 2152a68ff84SPeter Ujfalusi #define HDA_DSP_ROM_IPC_PURGE_FW 0x00004000 216dd96dacaSLiam Girdwood 217dd96dacaSLiam Girdwood /* various timeout values */ 218dd96dacaSLiam Girdwood #define HDA_DSP_PU_TIMEOUT 50 219dd96dacaSLiam Girdwood #define HDA_DSP_PD_TIMEOUT 50 220dd96dacaSLiam Girdwood #define HDA_DSP_RESET_TIMEOUT_US 50000 221dd96dacaSLiam Girdwood #define HDA_DSP_BASEFW_TIMEOUT_US 3000000 222dd96dacaSLiam Girdwood #define HDA_DSP_INIT_TIMEOUT_US 500000 223dd96dacaSLiam Girdwood #define HDA_DSP_CTRL_RESET_TIMEOUT 100 224dd96dacaSLiam Girdwood #define HDA_DSP_WAIT_TIMEOUT 500 /* 500 msec */ 225dd96dacaSLiam Girdwood #define HDA_DSP_REG_POLL_INTERVAL_US 500 /* 0.5 msec */ 22692f4beb7SKeyon Jie #define HDA_DSP_REG_POLL_RETRY_COUNT 50 227dd96dacaSLiam Girdwood 2289d201b69SPierre-Louis Bossart #define HDA_DSP_ADSPIC_IPC BIT(0) 2299d201b69SPierre-Louis Bossart #define HDA_DSP_ADSPIS_IPC BIT(0) 230dd96dacaSLiam Girdwood 231dd96dacaSLiam Girdwood /* Intel HD Audio General DSP Registers */ 232dd96dacaSLiam Girdwood #define HDA_DSP_GEN_BASE 0x0 233dd96dacaSLiam Girdwood #define HDA_DSP_REG_ADSPCS (HDA_DSP_GEN_BASE + 0x04) 234dd96dacaSLiam Girdwood #define HDA_DSP_REG_ADSPIC (HDA_DSP_GEN_BASE + 0x08) 235dd96dacaSLiam Girdwood #define HDA_DSP_REG_ADSPIS (HDA_DSP_GEN_BASE + 0x0C) 236dd96dacaSLiam Girdwood #define HDA_DSP_REG_ADSPIC2 (HDA_DSP_GEN_BASE + 0x10) 237dd96dacaSLiam Girdwood #define HDA_DSP_REG_ADSPIS2 (HDA_DSP_GEN_BASE + 0x14) 238dd96dacaSLiam Girdwood 239722ba5f1SBard Liao #define HDA_DSP_REG_ADSPIS2_SNDW BIT(5) 240722ba5f1SBard Liao 241dd96dacaSLiam Girdwood /* Intel HD Audio Inter-Processor Communication Registers */ 242dd96dacaSLiam Girdwood #define HDA_DSP_IPC_BASE 0x40 243dd96dacaSLiam Girdwood #define HDA_DSP_REG_HIPCT (HDA_DSP_IPC_BASE + 0x00) 244dd96dacaSLiam Girdwood #define HDA_DSP_REG_HIPCTE (HDA_DSP_IPC_BASE + 0x04) 245dd96dacaSLiam Girdwood #define HDA_DSP_REG_HIPCI (HDA_DSP_IPC_BASE + 0x08) 246dd96dacaSLiam Girdwood #define HDA_DSP_REG_HIPCIE (HDA_DSP_IPC_BASE + 0x0C) 247dd96dacaSLiam Girdwood #define HDA_DSP_REG_HIPCCTL (HDA_DSP_IPC_BASE + 0x10) 248dd96dacaSLiam Girdwood 24943b2ab90SRanjani Sridharan /* Intel Vendor Specific Registers */ 25043b2ab90SRanjani Sridharan #define HDA_VS_INTEL_EM2 0x1030 25143b2ab90SRanjani Sridharan #define HDA_VS_INTEL_EM2_L1SEN BIT(13) 252aca961f1SRanjani Sridharan #define HDA_VS_INTEL_LTRP_GB_MASK 0x3F 25343b2ab90SRanjani Sridharan 254dd96dacaSLiam Girdwood /* HIPCI */ 255dd96dacaSLiam Girdwood #define HDA_DSP_REG_HIPCI_BUSY BIT(31) 256dd96dacaSLiam Girdwood #define HDA_DSP_REG_HIPCI_MSG_MASK 0x7FFFFFFF 257dd96dacaSLiam Girdwood 258dd96dacaSLiam Girdwood /* HIPCIE */ 259dd96dacaSLiam Girdwood #define HDA_DSP_REG_HIPCIE_DONE BIT(30) 260dd96dacaSLiam Girdwood #define HDA_DSP_REG_HIPCIE_MSG_MASK 0x3FFFFFFF 261dd96dacaSLiam Girdwood 262dd96dacaSLiam Girdwood /* HIPCCTL */ 263dd96dacaSLiam Girdwood #define HDA_DSP_REG_HIPCCTL_DONE BIT(1) 264dd96dacaSLiam Girdwood #define HDA_DSP_REG_HIPCCTL_BUSY BIT(0) 265dd96dacaSLiam Girdwood 266dd96dacaSLiam Girdwood /* HIPCT */ 267dd96dacaSLiam Girdwood #define HDA_DSP_REG_HIPCT_BUSY BIT(31) 268dd96dacaSLiam Girdwood #define HDA_DSP_REG_HIPCT_MSG_MASK 0x7FFFFFFF 269dd96dacaSLiam Girdwood 270dd96dacaSLiam Girdwood /* HIPCTE */ 271dd96dacaSLiam Girdwood #define HDA_DSP_REG_HIPCTE_MSG_MASK 0x3FFFFFFF 272dd96dacaSLiam Girdwood 2739d201b69SPierre-Louis Bossart #define HDA_DSP_ADSPIC_CL_DMA BIT(1) 2749d201b69SPierre-Louis Bossart #define HDA_DSP_ADSPIS_CL_DMA BIT(1) 275dd96dacaSLiam Girdwood 276dd96dacaSLiam Girdwood /* Delay before scheduling D0i3 entry */ 277dd96dacaSLiam Girdwood #define BXT_D0I3_DELAY 5000 278dd96dacaSLiam Girdwood 279dd96dacaSLiam Girdwood #define FW_CL_STREAM_NUMBER 0x1 280776100a4SPierre-Louis Bossart #define HDA_FW_BOOT_ATTEMPTS 3 281dd96dacaSLiam Girdwood 282dd96dacaSLiam Girdwood /* ADSPCS - Audio DSP Control & Status */ 283dd96dacaSLiam Girdwood 284dd96dacaSLiam Girdwood /* 285dd96dacaSLiam Girdwood * Core Reset - asserted high 286dd96dacaSLiam Girdwood * CRST Mask for a given core mask pattern, cm 287dd96dacaSLiam Girdwood */ 288dd96dacaSLiam Girdwood #define HDA_DSP_ADSPCS_CRST_SHIFT 0 289dd96dacaSLiam Girdwood #define HDA_DSP_ADSPCS_CRST_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CRST_SHIFT) 290dd96dacaSLiam Girdwood 291dd96dacaSLiam Girdwood /* 292dd96dacaSLiam Girdwood * Core run/stall - when set to '1' core is stalled 293dd96dacaSLiam Girdwood * CSTALL Mask for a given core mask pattern, cm 294dd96dacaSLiam Girdwood */ 295dd96dacaSLiam Girdwood #define HDA_DSP_ADSPCS_CSTALL_SHIFT 8 296dd96dacaSLiam Girdwood #define HDA_DSP_ADSPCS_CSTALL_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CSTALL_SHIFT) 297dd96dacaSLiam Girdwood 298dd96dacaSLiam Girdwood /* 299dd96dacaSLiam Girdwood * Set Power Active - when set to '1' turn cores on 300dd96dacaSLiam Girdwood * SPA Mask for a given core mask pattern, cm 301dd96dacaSLiam Girdwood */ 302dd96dacaSLiam Girdwood #define HDA_DSP_ADSPCS_SPA_SHIFT 16 303dd96dacaSLiam Girdwood #define HDA_DSP_ADSPCS_SPA_MASK(cm) ((cm) << HDA_DSP_ADSPCS_SPA_SHIFT) 304dd96dacaSLiam Girdwood 305dd96dacaSLiam Girdwood /* 306dd96dacaSLiam Girdwood * Current Power Active - power status of cores, set by hardware 307dd96dacaSLiam Girdwood * CPA Mask for a given core mask pattern, cm 308dd96dacaSLiam Girdwood */ 309dd96dacaSLiam Girdwood #define HDA_DSP_ADSPCS_CPA_SHIFT 24 310dd96dacaSLiam Girdwood #define HDA_DSP_ADSPCS_CPA_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CPA_SHIFT) 311dd96dacaSLiam Girdwood 312dd96dacaSLiam Girdwood /* 313dd96dacaSLiam Girdwood * Mask for a given number of cores 314dd96dacaSLiam Girdwood * nc = number of supported cores 315dd96dacaSLiam Girdwood */ 316dd96dacaSLiam Girdwood #define SOF_DSP_CORES_MASK(nc) GENMASK(((nc) - 1), 0) 317dd96dacaSLiam Girdwood 318dd96dacaSLiam Girdwood /* Intel HD Audio Inter-Processor Communication Registers for Cannonlake*/ 319dd96dacaSLiam Girdwood #define CNL_DSP_IPC_BASE 0xc0 320dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCTDR (CNL_DSP_IPC_BASE + 0x00) 321dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCTDA (CNL_DSP_IPC_BASE + 0x04) 322dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCTDD (CNL_DSP_IPC_BASE + 0x08) 323dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCIDR (CNL_DSP_IPC_BASE + 0x10) 324dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCIDA (CNL_DSP_IPC_BASE + 0x14) 3250267de58SKeyon Jie #define CNL_DSP_REG_HIPCIDD (CNL_DSP_IPC_BASE + 0x18) 326dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCCTL (CNL_DSP_IPC_BASE + 0x28) 327dd96dacaSLiam Girdwood 328dd96dacaSLiam Girdwood /* HIPCI */ 329dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCIDR_BUSY BIT(31) 330dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCIDR_MSG_MASK 0x7FFFFFFF 331dd96dacaSLiam Girdwood 332dd96dacaSLiam Girdwood /* HIPCIE */ 333dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCIDA_DONE BIT(31) 334dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCIDA_MSG_MASK 0x7FFFFFFF 335dd96dacaSLiam Girdwood 336dd96dacaSLiam Girdwood /* HIPCCTL */ 337dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCCTL_DONE BIT(1) 338dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCCTL_BUSY BIT(0) 339dd96dacaSLiam Girdwood 340dd96dacaSLiam Girdwood /* HIPCT */ 341dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCTDR_BUSY BIT(31) 342dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCTDR_MSG_MASK 0x7FFFFFFF 343dd96dacaSLiam Girdwood 344dd96dacaSLiam Girdwood /* HIPCTDA */ 345dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCTDA_DONE BIT(31) 346dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCTDA_MSG_MASK 0x7FFFFFFF 347dd96dacaSLiam Girdwood 348dd96dacaSLiam Girdwood /* HIPCTDD */ 349dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCTDD_MSG_MASK 0x7FFFFFFF 350dd96dacaSLiam Girdwood 351dd96dacaSLiam Girdwood /* BDL */ 352dd96dacaSLiam Girdwood #define HDA_DSP_BDL_SIZE 4096 353dd96dacaSLiam Girdwood #define HDA_DSP_MAX_BDL_ENTRIES \ 354dd96dacaSLiam Girdwood (HDA_DSP_BDL_SIZE / sizeof(struct sof_intel_dsp_bdl)) 355dd96dacaSLiam Girdwood 356dd96dacaSLiam Girdwood /* Number of DAIs */ 357dd96dacaSLiam Girdwood #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) 358a6947c9dSCezary Rojewski #define SOF_SKL_NUM_DAIS 15 359dd96dacaSLiam Girdwood #else 360dd96dacaSLiam Girdwood #define SOF_SKL_NUM_DAIS 8 361dd96dacaSLiam Girdwood #endif 362dd96dacaSLiam Girdwood 363dd96dacaSLiam Girdwood /* Intel HD Audio SRAM Window 0*/ 364dd96dacaSLiam Girdwood #define HDA_ADSP_SRAM0_BASE_SKL 0x8000 365dd96dacaSLiam Girdwood 366dd96dacaSLiam Girdwood /* Firmware status window */ 367dd96dacaSLiam Girdwood #define HDA_ADSP_FW_STATUS_SKL HDA_ADSP_SRAM0_BASE_SKL 368dd96dacaSLiam Girdwood #define HDA_ADSP_ERROR_CODE_SKL (HDA_ADSP_FW_STATUS_SKL + 0x4) 369dd96dacaSLiam Girdwood 370df7e0de5SZhu Yingjiang /* Host Device Memory Space */ 371df7e0de5SZhu Yingjiang #define APL_SSP_BASE_OFFSET 0x2000 372df7e0de5SZhu Yingjiang #define CNL_SSP_BASE_OFFSET 0x10000 373df7e0de5SZhu Yingjiang 374df7e0de5SZhu Yingjiang /* Host Device Memory Size of a Single SSP */ 375df7e0de5SZhu Yingjiang #define SSP_DEV_MEM_SIZE 0x1000 376df7e0de5SZhu Yingjiang 377b095fe47SZhu Yingjiang /* SSP Count of the Platform */ 378b095fe47SZhu Yingjiang #define APL_SSP_COUNT 6 379b095fe47SZhu Yingjiang #define CNL_SSP_COUNT 3 380ec836daaSZhu Yingjiang #define ICL_SSP_COUNT 6 381b095fe47SZhu Yingjiang 38274ed4097SZhu Yingjiang /* SSP Registers */ 38374ed4097SZhu Yingjiang #define SSP_SSC1_OFFSET 0x4 384bd586a02SPierre-Louis Bossart #define SSP_SET_SCLK_CONSUMER BIT(25) 385bd586a02SPierre-Louis Bossart #define SSP_SET_SFRM_CONSUMER BIT(24) 386bd586a02SPierre-Louis Bossart #define SSP_SET_CBP_CFP (SSP_SET_SCLK_CONSUMER | SSP_SET_SFRM_CONSUMER) 38774ed4097SZhu Yingjiang 388c99fafdfSKai Vehmanen #define HDA_IDISP_ADDR 2 389c99fafdfSKai Vehmanen #define HDA_IDISP_CODEC(x) ((x) & BIT(HDA_IDISP_ADDR)) 390dd96dacaSLiam Girdwood 391dd96dacaSLiam Girdwood struct sof_intel_dsp_bdl { 392dd96dacaSLiam Girdwood __le32 addr_l; 393dd96dacaSLiam Girdwood __le32 addr_h; 394dd96dacaSLiam Girdwood __le32 size; 395dd96dacaSLiam Girdwood __le32 ioc; 396dd96dacaSLiam Girdwood } __attribute((packed)); 397dd96dacaSLiam Girdwood 398dd96dacaSLiam Girdwood #define SOF_HDA_PLAYBACK_STREAMS 16 399dd96dacaSLiam Girdwood #define SOF_HDA_CAPTURE_STREAMS 16 400dd96dacaSLiam Girdwood #define SOF_HDA_PLAYBACK 0 401dd96dacaSLiam Girdwood #define SOF_HDA_CAPTURE 1 402dd96dacaSLiam Girdwood 40389a400bdSRanjani Sridharan /* stream flags */ 40489a400bdSRanjani Sridharan #define SOF_HDA_STREAM_DMI_L1_COMPATIBLE 1 40589a400bdSRanjani Sridharan 40663e51fd3SRanjani Sridharan /* 40763e51fd3SRanjani Sridharan * Time in ms for opportunistic D0I3 entry delay. 40863e51fd3SRanjani Sridharan * This has been deliberately chosen to be long to avoid race conditions. 40963e51fd3SRanjani Sridharan * Could be optimized in future. 41063e51fd3SRanjani Sridharan */ 41163e51fd3SRanjani Sridharan #define SOF_HDA_D0I3_WORK_DELAY_MS 5000 41263e51fd3SRanjani Sridharan 41361e285caSRanjani Sridharan /* HDA DSP D0 substate */ 41461e285caSRanjani Sridharan enum sof_hda_D0_substate { 41561e285caSRanjani Sridharan SOF_HDA_DSP_PM_D0I0, /* default D0 substate */ 41661e285caSRanjani Sridharan SOF_HDA_DSP_PM_D0I3, /* low power D0 substate */ 41761e285caSRanjani Sridharan }; 41861e285caSRanjani Sridharan 419dd96dacaSLiam Girdwood /* represents DSP HDA controller frontend - i.e. host facing control */ 420dd96dacaSLiam Girdwood struct sof_intel_hda_dev { 4212a68ff84SPeter Ujfalusi bool imrboot_supported; 4222a68ff84SPeter Ujfalusi 423776100a4SPierre-Louis Bossart int boot_iteration; 424dd96dacaSLiam Girdwood 425dd96dacaSLiam Girdwood struct hda_bus hbus; 426dd96dacaSLiam Girdwood 427dd96dacaSLiam Girdwood /* hw config */ 428dd96dacaSLiam Girdwood const struct sof_intel_dsp_desc *desc; 429dd96dacaSLiam Girdwood 430dd96dacaSLiam Girdwood /* trace */ 431dd96dacaSLiam Girdwood struct hdac_ext_stream *dtrace_stream; 432dd96dacaSLiam Girdwood 433dd96dacaSLiam Girdwood /* if position update IPC needed */ 434dd96dacaSLiam Girdwood u32 no_ipc_position; 435dd96dacaSLiam Girdwood 436e8e55dbeSKeyon Jie /* the maximum number of streams (playback + capture) supported */ 437e8e55dbeSKeyon Jie u32 stream_max; 438e8e55dbeSKeyon Jie 43916299326SKeyon Jie /* PM related */ 44016299326SKeyon Jie bool l1_support_changed;/* during suspend, is L1SEN changed or not */ 44116299326SKeyon Jie 442dd96dacaSLiam Girdwood /* DMIC device */ 443dd96dacaSLiam Girdwood struct platform_device *dmic_dev; 44463e51fd3SRanjani Sridharan 44563e51fd3SRanjani Sridharan /* delayed work to enter D0I3 opportunistically */ 44663e51fd3SRanjani Sridharan struct delayed_work d0i3_work; 44751dfed1eSPierre-Louis Bossart 44851dfed1eSPierre-Louis Bossart /* ACPI information stored between scan and probe steps */ 44951dfed1eSPierre-Louis Bossart struct sdw_intel_acpi_info info; 45051dfed1eSPierre-Louis Bossart 45151dfed1eSPierre-Louis Bossart /* sdw context allocated by SoundWire driver */ 45251dfed1eSPierre-Louis Bossart struct sdw_intel_ctx *sdw; 453edbaaadaSFred Oh 454edbaaadaSFred Oh /* FW clock config, 0:HPRO, 1:LPRO */ 455edbaaadaSFred Oh bool clk_config_lpro; 45695fa7a62SPierre-Louis Bossart 45795fa7a62SPierre-Louis Bossart /* Intel NHLT information */ 45895fa7a62SPierre-Louis Bossart struct nhlt_acpi_table *nhlt; 459dd96dacaSLiam Girdwood }; 460dd96dacaSLiam Girdwood 461dd96dacaSLiam Girdwood static inline struct hdac_bus *sof_to_bus(struct snd_sof_dev *s) 462dd96dacaSLiam Girdwood { 463dd96dacaSLiam Girdwood struct sof_intel_hda_dev *hda = s->pdata->hw_pdata; 464dd96dacaSLiam Girdwood 465dd96dacaSLiam Girdwood return &hda->hbus.core; 466dd96dacaSLiam Girdwood } 467dd96dacaSLiam Girdwood 468dd96dacaSLiam Girdwood static inline struct hda_bus *sof_to_hbus(struct snd_sof_dev *s) 469dd96dacaSLiam Girdwood { 470dd96dacaSLiam Girdwood struct sof_intel_hda_dev *hda = s->pdata->hw_pdata; 471dd96dacaSLiam Girdwood 472dd96dacaSLiam Girdwood return &hda->hbus; 473dd96dacaSLiam Girdwood } 474dd96dacaSLiam Girdwood 475dd96dacaSLiam Girdwood struct sof_intel_hda_stream { 4767623ae79SRanjani Sridharan struct snd_sof_dev *sdev; 4777d88b960SPierre-Louis Bossart struct hdac_ext_stream hext_stream; 4787d88b960SPierre-Louis Bossart struct sof_intel_stream sof_intel_stream; 4796b2239e3SRanjani Sridharan int host_reserved; /* reserve host DMA channel */ 48089a400bdSRanjani Sridharan u32 flags; 481dd96dacaSLiam Girdwood }; 482dd96dacaSLiam Girdwood 483f5dbba9fSRanjani Sridharan #define hstream_to_sof_hda_stream(hstream) \ 4847d88b960SPierre-Louis Bossart container_of(hstream, struct sof_intel_hda_stream, hext_stream) 485f5dbba9fSRanjani Sridharan 486dd96dacaSLiam Girdwood #define bus_to_sof_hda(bus) \ 487dd96dacaSLiam Girdwood container_of(bus, struct sof_intel_hda_dev, hbus.core) 488dd96dacaSLiam Girdwood 489dd96dacaSLiam Girdwood #define SOF_STREAM_SD_OFFSET(s) \ 490dd96dacaSLiam Girdwood (SOF_HDA_ADSP_SD_ENTRY_SIZE * ((s)->index) \ 491dd96dacaSLiam Girdwood + SOF_HDA_ADSP_LOADER_BASE) 492dd96dacaSLiam Girdwood 4932b1acedcSRanjani Sridharan #define SOF_STREAM_SD_OFFSET_CRST 0x1 4942b1acedcSRanjani Sridharan 495dd96dacaSLiam Girdwood /* 496dd96dacaSLiam Girdwood * DSP Core services. 497dd96dacaSLiam Girdwood */ 498dd96dacaSLiam Girdwood int hda_dsp_probe(struct snd_sof_dev *sdev); 499dd96dacaSLiam Girdwood int hda_dsp_remove(struct snd_sof_dev *sdev); 500dd96dacaSLiam Girdwood int hda_dsp_core_run(struct snd_sof_dev *sdev, unsigned int core_mask); 501dd96dacaSLiam Girdwood int hda_dsp_enable_core(struct snd_sof_dev *sdev, unsigned int core_mask); 502dd96dacaSLiam Girdwood int hda_dsp_core_reset_power_down(struct snd_sof_dev *sdev, 503dd96dacaSLiam Girdwood unsigned int core_mask); 5049cdcbc9fSRanjani Sridharan int hda_dsp_core_get(struct snd_sof_dev *sdev, int core); 505dd96dacaSLiam Girdwood void hda_dsp_ipc_int_enable(struct snd_sof_dev *sdev); 506dd96dacaSLiam Girdwood void hda_dsp_ipc_int_disable(struct snd_sof_dev *sdev); 507dd96dacaSLiam Girdwood 50862f8f766SKeyon Jie int hda_dsp_set_power_state(struct snd_sof_dev *sdev, 50961e285caSRanjani Sridharan const struct sof_dsp_power_state *target_state); 51062f8f766SKeyon Jie 51161e285caSRanjani Sridharan int hda_dsp_suspend(struct snd_sof_dev *sdev, u32 target_state); 512dd96dacaSLiam Girdwood int hda_dsp_resume(struct snd_sof_dev *sdev); 5131c38c922SFred Oh int hda_dsp_runtime_suspend(struct snd_sof_dev *sdev); 514dd96dacaSLiam Girdwood int hda_dsp_runtime_resume(struct snd_sof_dev *sdev); 51562fde977SKai Vehmanen int hda_dsp_runtime_idle(struct snd_sof_dev *sdev); 51622aa9e02SLibin Yang int hda_dsp_shutdown(struct snd_sof_dev *sdev); 5177077a07aSRanjani Sridharan int hda_dsp_set_hw_params_upon_resume(struct snd_sof_dev *sdev); 518dd96dacaSLiam Girdwood void hda_dsp_dump(struct snd_sof_dev *sdev, u32 flags); 519f3da49f0SPan Xiuli void hda_ipc_dump(struct snd_sof_dev *sdev); 520f1fd9d0eSKai Vehmanen void hda_ipc_irq_dump(struct snd_sof_dev *sdev); 52163e51fd3SRanjani Sridharan void hda_dsp_d0i3_work(struct work_struct *work); 522dd96dacaSLiam Girdwood 523dd96dacaSLiam Girdwood /* 524dd96dacaSLiam Girdwood * DSP PCM Operations. 525dd96dacaSLiam Girdwood */ 52649d7948eSCezary Rojewski u32 hda_dsp_get_mult_div(struct snd_sof_dev *sdev, int rate); 52749d7948eSCezary Rojewski u32 hda_dsp_get_bits(struct snd_sof_dev *sdev, int sample_bits); 528dd96dacaSLiam Girdwood int hda_dsp_pcm_open(struct snd_sof_dev *sdev, 529dd96dacaSLiam Girdwood struct snd_pcm_substream *substream); 530dd96dacaSLiam Girdwood int hda_dsp_pcm_close(struct snd_sof_dev *sdev, 531dd96dacaSLiam Girdwood struct snd_pcm_substream *substream); 532dd96dacaSLiam Girdwood int hda_dsp_pcm_hw_params(struct snd_sof_dev *sdev, 533dd96dacaSLiam Girdwood struct snd_pcm_substream *substream, 534dd96dacaSLiam Girdwood struct snd_pcm_hw_params *params, 53531f60a0cSPeter Ujfalusi struct snd_sof_platform_stream_params *platform_params); 53693146bc2SRanjani Sridharan int hda_dsp_stream_hw_free(struct snd_sof_dev *sdev, 53793146bc2SRanjani Sridharan struct snd_pcm_substream *substream); 538dd96dacaSLiam Girdwood int hda_dsp_pcm_trigger(struct snd_sof_dev *sdev, 539dd96dacaSLiam Girdwood struct snd_pcm_substream *substream, int cmd); 540dd96dacaSLiam Girdwood snd_pcm_uframes_t hda_dsp_pcm_pointer(struct snd_sof_dev *sdev, 541dd96dacaSLiam Girdwood struct snd_pcm_substream *substream); 5426c26b505SRanjani Sridharan int hda_dsp_pcm_ack(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream); 543dd96dacaSLiam Girdwood 544dd96dacaSLiam Girdwood /* 545dd96dacaSLiam Girdwood * DSP Stream Operations. 546dd96dacaSLiam Girdwood */ 547dd96dacaSLiam Girdwood 548dd96dacaSLiam Girdwood int hda_dsp_stream_init(struct snd_sof_dev *sdev); 549dd96dacaSLiam Girdwood void hda_dsp_stream_free(struct snd_sof_dev *sdev); 550dd96dacaSLiam Girdwood int hda_dsp_stream_hw_params(struct snd_sof_dev *sdev, 5517d88b960SPierre-Louis Bossart struct hdac_ext_stream *hext_stream, 552dd96dacaSLiam Girdwood struct snd_dma_buffer *dmab, 553dd96dacaSLiam Girdwood struct snd_pcm_hw_params *params); 5547d88b960SPierre-Louis Bossart int hda_dsp_iccmax_stream_hw_params(struct snd_sof_dev *sdev, 5557d88b960SPierre-Louis Bossart struct hdac_ext_stream *hext_stream, 556aca961f1SRanjani Sridharan struct snd_dma_buffer *dmab, 557aca961f1SRanjani Sridharan struct snd_pcm_hw_params *params); 558dd96dacaSLiam Girdwood int hda_dsp_stream_trigger(struct snd_sof_dev *sdev, 5597d88b960SPierre-Louis Bossart struct hdac_ext_stream *hext_stream, int cmd); 560dd96dacaSLiam Girdwood irqreturn_t hda_dsp_stream_threaded_handler(int irq, void *context); 561dd96dacaSLiam Girdwood int hda_dsp_stream_setup_bdl(struct snd_sof_dev *sdev, 562dd96dacaSLiam Girdwood struct snd_dma_buffer *dmab, 5637d88b960SPierre-Louis Bossart struct hdac_stream *hstream); 5647c11af9fSBard Liao bool hda_dsp_check_ipc_irq(struct snd_sof_dev *sdev); 5657c11af9fSBard Liao bool hda_dsp_check_stream_irq(struct snd_sof_dev *sdev); 566dd96dacaSLiam Girdwood 567dd96dacaSLiam Girdwood struct hdac_ext_stream * 56889a400bdSRanjani Sridharan hda_dsp_stream_get(struct snd_sof_dev *sdev, int direction, u32 flags); 569dd96dacaSLiam Girdwood int hda_dsp_stream_put(struct snd_sof_dev *sdev, int direction, int stream_tag); 570dd96dacaSLiam Girdwood int hda_dsp_stream_spib_config(struct snd_sof_dev *sdev, 5717d88b960SPierre-Louis Bossart struct hdac_ext_stream *hext_stream, 572dd96dacaSLiam Girdwood int enable, u32 size); 573dd96dacaSLiam Girdwood 5746a0ba071SGuennadi Liakhovetski int hda_ipc_msg_data(struct snd_sof_dev *sdev, 575dd96dacaSLiam Girdwood struct snd_pcm_substream *substream, 576dd96dacaSLiam Girdwood void *p, size_t sz); 57729e3aa0bSPeter Ujfalusi int hda_set_stream_data_offset(struct snd_sof_dev *sdev, 57829e3aa0bSPeter Ujfalusi struct snd_pcm_substream *substream, 57929e3aa0bSPeter Ujfalusi size_t posn_offset); 580dd96dacaSLiam Girdwood 581dd96dacaSLiam Girdwood /* 582dd96dacaSLiam Girdwood * DSP IPC Operations. 583dd96dacaSLiam Girdwood */ 584dd96dacaSLiam Girdwood int hda_dsp_ipc_send_msg(struct snd_sof_dev *sdev, 585dd96dacaSLiam Girdwood struct snd_sof_ipc_msg *msg); 586dd96dacaSLiam Girdwood void hda_dsp_ipc_get_reply(struct snd_sof_dev *sdev); 5876eebd390SDaniel Baluta int hda_dsp_ipc_get_mailbox_offset(struct snd_sof_dev *sdev); 5886eebd390SDaniel Baluta int hda_dsp_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id); 5896eebd390SDaniel Baluta 590dd96dacaSLiam Girdwood irqreturn_t hda_dsp_ipc_irq_thread(int irq, void *context); 591dd96dacaSLiam Girdwood int hda_dsp_ipc_cmd_done(struct snd_sof_dev *sdev, int dir); 592dd96dacaSLiam Girdwood 593dd96dacaSLiam Girdwood /* 594dd96dacaSLiam Girdwood * DSP Code loader. 595dd96dacaSLiam Girdwood */ 596dd96dacaSLiam Girdwood int hda_dsp_cl_boot_firmware(struct snd_sof_dev *sdev); 597acf705a4SRanjani Sridharan int hda_dsp_cl_boot_firmware_iccmax(struct snd_sof_dev *sdev); 598b4e4c0b9SRanjani Sridharan int hda_cl_copy_fw(struct snd_sof_dev *sdev, struct hdac_ext_stream *hext_stream); 599b4e4c0b9SRanjani Sridharan struct hdac_ext_stream *hda_cl_stream_prepare(struct snd_sof_dev *sdev, unsigned int format, 600b4e4c0b9SRanjani Sridharan unsigned int size, struct snd_dma_buffer *dmab, 601b4e4c0b9SRanjani Sridharan int direction); 602b4e4c0b9SRanjani Sridharan int hda_cl_cleanup(struct snd_sof_dev *sdev, struct snd_dma_buffer *dmab, 603b4e4c0b9SRanjani Sridharan struct hdac_ext_stream *hext_stream); 604406fed80SRanjani Sridharan #define HDA_CL_STREAM_FORMAT 0x40 605dd96dacaSLiam Girdwood 606dd96dacaSLiam Girdwood /* pre and post fw run ops */ 607dd96dacaSLiam Girdwood int hda_dsp_pre_fw_run(struct snd_sof_dev *sdev); 608dd96dacaSLiam Girdwood int hda_dsp_post_fw_run(struct snd_sof_dev *sdev); 609dd96dacaSLiam Girdwood 610edbaaadaSFred Oh /* parse platform specific ext manifest ops */ 611edbaaadaSFred Oh int hda_dsp_ext_man_get_cavs_config_data(struct snd_sof_dev *sdev, 612edbaaadaSFred Oh const struct sof_ext_man_elem_header *hdr); 613edbaaadaSFred Oh 614dd96dacaSLiam Girdwood /* 615dd96dacaSLiam Girdwood * HDA Controller Operations. 616dd96dacaSLiam Girdwood */ 617dd96dacaSLiam Girdwood int hda_dsp_ctrl_get_caps(struct snd_sof_dev *sdev); 618dd96dacaSLiam Girdwood void hda_dsp_ctrl_ppcap_enable(struct snd_sof_dev *sdev, bool enable); 619dd96dacaSLiam Girdwood void hda_dsp_ctrl_ppcap_int_enable(struct snd_sof_dev *sdev, bool enable); 620dd96dacaSLiam Girdwood int hda_dsp_ctrl_link_reset(struct snd_sof_dev *sdev, bool reset); 621dd96dacaSLiam Girdwood void hda_dsp_ctrl_misc_clock_gating(struct snd_sof_dev *sdev, bool enable); 622dd96dacaSLiam Girdwood int hda_dsp_ctrl_clock_power_gating(struct snd_sof_dev *sdev, bool enable); 623dd96dacaSLiam Girdwood int hda_dsp_ctrl_init_chip(struct snd_sof_dev *sdev, bool full_reset); 62413063a2cSZhu Yingjiang void hda_dsp_ctrl_stop_chip(struct snd_sof_dev *sdev); 625dd96dacaSLiam Girdwood /* 626dd96dacaSLiam Girdwood * HDA bus operations. 627dd96dacaSLiam Girdwood */ 628d4ff1b39STakashi Iwai void sof_hda_bus_init(struct hdac_bus *bus, struct device *dev); 629dd96dacaSLiam Girdwood 630dd96dacaSLiam Girdwood #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) 631dd96dacaSLiam Girdwood /* 632dd96dacaSLiam Girdwood * HDA Codec operations. 633dd96dacaSLiam Girdwood */ 63491dce767SKai Vehmanen void hda_codec_probe_bus(struct snd_sof_dev *sdev, 63580acdd4fSRanjani Sridharan bool hda_codec_use_common_hdmi); 63631ba0c07SKai-Heng Feng void hda_codec_jack_wake_enable(struct snd_sof_dev *sdev, bool enable); 637fd15f2f5SRander Wang void hda_codec_jack_check(struct snd_sof_dev *sdev); 638dd96dacaSLiam Girdwood 639dd96dacaSLiam Girdwood #endif /* CONFIG_SND_SOC_SOF_HDA */ 640dd96dacaSLiam Girdwood 641139c7febSKai Vehmanen #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) && \ 642139c7febSKai Vehmanen (IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI) || \ 643139c7febSKai Vehmanen IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) 644dd96dacaSLiam Girdwood 64523ee0903SKai Vehmanen void hda_codec_i915_display_power(struct snd_sof_dev *sdev, bool enable); 646dd96dacaSLiam Girdwood int hda_codec_i915_init(struct snd_sof_dev *sdev); 647dd96dacaSLiam Girdwood int hda_codec_i915_exit(struct snd_sof_dev *sdev); 648dd96dacaSLiam Girdwood 649dd96dacaSLiam Girdwood #else 650dd96dacaSLiam Girdwood 65123ee0903SKai Vehmanen static inline void hda_codec_i915_display_power(struct snd_sof_dev *sdev, 65223ee0903SKai Vehmanen bool enable) { } 653dd96dacaSLiam Girdwood static inline int hda_codec_i915_init(struct snd_sof_dev *sdev) { return 0; } 654dd96dacaSLiam Girdwood static inline int hda_codec_i915_exit(struct snd_sof_dev *sdev) { return 0; } 655dd96dacaSLiam Girdwood 656139c7febSKai Vehmanen #endif 657dd96dacaSLiam Girdwood 658dd96dacaSLiam Girdwood /* 659dd96dacaSLiam Girdwood * Trace Control. 660dd96dacaSLiam Girdwood */ 661bab05b50SPeter Ujfalusi int hda_dsp_trace_init(struct snd_sof_dev *sdev, 662bab05b50SPeter Ujfalusi struct sof_ipc_dma_trace_params_ext *dtrace_params); 663dd96dacaSLiam Girdwood int hda_dsp_trace_release(struct snd_sof_dev *sdev); 664dd96dacaSLiam Girdwood int hda_dsp_trace_trigger(struct snd_sof_dev *sdev, int cmd); 665dd96dacaSLiam Girdwood 66651dfed1eSPierre-Louis Bossart /* 66751dfed1eSPierre-Louis Bossart * SoundWire support 66851dfed1eSPierre-Louis Bossart */ 66951dfed1eSPierre-Louis Bossart #if IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE) 67051dfed1eSPierre-Louis Bossart 67151dfed1eSPierre-Louis Bossart int hda_sdw_startup(struct snd_sof_dev *sdev); 67251dfed1eSPierre-Louis Bossart void hda_sdw_int_enable(struct snd_sof_dev *sdev, bool enable); 673bbd19cdcSRander Wang void hda_sdw_process_wakeen(struct snd_sof_dev *sdev); 674198fa4bcSBard Liao bool hda_common_check_sdw_irq(struct snd_sof_dev *sdev); 67551dfed1eSPierre-Louis Bossart 67651dfed1eSPierre-Louis Bossart #else 67751dfed1eSPierre-Louis Bossart 67851dfed1eSPierre-Louis Bossart static inline int hda_sdw_startup(struct snd_sof_dev *sdev) 67951dfed1eSPierre-Louis Bossart { 68051dfed1eSPierre-Louis Bossart return 0; 68151dfed1eSPierre-Louis Bossart } 68251dfed1eSPierre-Louis Bossart 68351dfed1eSPierre-Louis Bossart static inline void hda_sdw_int_enable(struct snd_sof_dev *sdev, bool enable) 68451dfed1eSPierre-Louis Bossart { 68551dfed1eSPierre-Louis Bossart } 68651dfed1eSPierre-Louis Bossart 687bbd19cdcSRander Wang static inline void hda_sdw_process_wakeen(struct snd_sof_dev *sdev) 688bbd19cdcSRander Wang { 689bbd19cdcSRander Wang } 690198fa4bcSBard Liao 691198fa4bcSBard Liao static inline bool hda_common_check_sdw_irq(struct snd_sof_dev *sdev) 692198fa4bcSBard Liao { 693198fa4bcSBard Liao return false; 694198fa4bcSBard Liao } 695198fa4bcSBard Liao 69651dfed1eSPierre-Louis Bossart #endif 69751dfed1eSPierre-Louis Bossart 698dd96dacaSLiam Girdwood /* common dai driver */ 699dd96dacaSLiam Girdwood extern struct snd_soc_dai_driver skl_dai[]; 700*f09e9284SPierre-Louis Bossart int hda_dsp_dais_suspend(struct snd_sof_dev *sdev); 701dd96dacaSLiam Girdwood 702dd96dacaSLiam Girdwood /* 703dd96dacaSLiam Girdwood * Platform Specific HW abstraction Ops. 704dd96dacaSLiam Girdwood */ 70537e809d5SPierre-Louis Bossart extern struct snd_sof_dsp_ops sof_hda_common_ops; 70637e809d5SPierre-Louis Bossart 707856601e5SPierre-Louis Bossart extern struct snd_sof_dsp_ops sof_apl_ops; 70837e809d5SPierre-Louis Bossart int sof_apl_ops_init(struct snd_sof_dev *sdev); 709856601e5SPierre-Louis Bossart extern struct snd_sof_dsp_ops sof_cnl_ops; 71037e809d5SPierre-Louis Bossart int sof_cnl_ops_init(struct snd_sof_dev *sdev); 711856601e5SPierre-Louis Bossart extern struct snd_sof_dsp_ops sof_tgl_ops; 71237e809d5SPierre-Louis Bossart int sof_tgl_ops_init(struct snd_sof_dev *sdev); 713856601e5SPierre-Louis Bossart extern struct snd_sof_dsp_ops sof_icl_ops; 71437e809d5SPierre-Louis Bossart int sof_icl_ops_init(struct snd_sof_dev *sdev); 715dd96dacaSLiam Girdwood 716dd96dacaSLiam Girdwood extern const struct sof_intel_dsp_desc apl_chip_info; 717dd96dacaSLiam Girdwood extern const struct sof_intel_dsp_desc cnl_chip_info; 718630be964SZhu Yingjiang extern const struct sof_intel_dsp_desc icl_chip_info; 7191205c81eSPan Xiuli extern const struct sof_intel_dsp_desc tgl_chip_info; 72030ee3738SRander Wang extern const struct sof_intel_dsp_desc tglh_chip_info; 72161732690SPan Xiuli extern const struct sof_intel_dsp_desc ehl_chip_info; 7226fd99035SPan Xiuli extern const struct sof_intel_dsp_desc jsl_chip_info; 7236c2b6bb0SKai Vehmanen extern const struct sof_intel_dsp_desc adls_chip_info; 724dd96dacaSLiam Girdwood 7253dc0d709SPeter Ujfalusi /* Probes support */ 7263dc0d709SPeter Ujfalusi #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_PROBES) 7273dc0d709SPeter Ujfalusi int hda_probes_register(struct snd_sof_dev *sdev); 7283dc0d709SPeter Ujfalusi void hda_probes_unregister(struct snd_sof_dev *sdev); 7293dc0d709SPeter Ujfalusi #else 7303dc0d709SPeter Ujfalusi static inline int hda_probes_register(struct snd_sof_dev *sdev) 7313dc0d709SPeter Ujfalusi { 7323dc0d709SPeter Ujfalusi return 0; 7333dc0d709SPeter Ujfalusi } 7343dc0d709SPeter Ujfalusi 7353dc0d709SPeter Ujfalusi static inline void hda_probes_unregister(struct snd_sof_dev *sdev) 7363dc0d709SPeter Ujfalusi { 7373dc0d709SPeter Ujfalusi } 7383dc0d709SPeter Ujfalusi #endif /* CONFIG_SND_SOC_SOF_HDA_PROBES */ 7393dc0d709SPeter Ujfalusi 7403dc0d709SPeter Ujfalusi /* SOF client registration for HDA platforms */ 7413dc0d709SPeter Ujfalusi int hda_register_clients(struct snd_sof_dev *sdev); 7423dc0d709SPeter Ujfalusi void hda_unregister_clients(struct snd_sof_dev *sdev); 7433dc0d709SPeter Ujfalusi 744285880a2SDaniel Baluta /* machine driver select */ 745cb515f10SGuennadi Liakhovetski struct snd_soc_acpi_mach *hda_machine_select(struct snd_sof_dev *sdev); 746cb515f10SGuennadi Liakhovetski void hda_set_mach_params(struct snd_soc_acpi_mach *mach, 74717e9d6b0SPierre-Louis Bossart struct snd_sof_dev *sdev); 748285880a2SDaniel Baluta 749194fe0fcSPierre-Louis Bossart /* PCI driver selection and probe */ 750194fe0fcSPierre-Louis Bossart int hda_pci_intel_probe(struct pci_dev *pci, const struct pci_device_id *pci_id); 751194fe0fcSPierre-Louis Bossart 7520acb48ddSRanjani Sridharan struct snd_sof_dai; 7530acb48ddSRanjani Sridharan struct sof_ipc_dai_config; 754051744b1SRanjani Sridharan int hda_ctrl_dai_widget_setup(struct snd_soc_dapm_widget *w, unsigned int quirk_flags, 755051744b1SRanjani Sridharan struct snd_sof_dai_config_data *data); 756051744b1SRanjani Sridharan int hda_ctrl_dai_widget_free(struct snd_soc_dapm_widget *w, unsigned int quirk_flags, 757051744b1SRanjani Sridharan struct snd_sof_dai_config_data *data); 7580acb48ddSRanjani Sridharan 759288fad2fSPierre-Louis Bossart #define SOF_HDA_POSITION_QUIRK_USE_SKYLAKE_LEGACY (0) /* previous implementation */ 760288fad2fSPierre-Louis Bossart #define SOF_HDA_POSITION_QUIRK_USE_DPIB_REGISTERS (1) /* recommended if VC0 only */ 761288fad2fSPierre-Louis Bossart #define SOF_HDA_POSITION_QUIRK_USE_DPIB_DDR_UPDATE (2) /* recommended with VC0 or VC1 */ 762288fad2fSPierre-Louis Bossart 763288fad2fSPierre-Louis Bossart extern int sof_hda_position_quirk; 764288fad2fSPierre-Louis Bossart 76551ec71dcSRanjani Sridharan void hda_set_dai_drv_ops(struct snd_sof_dev *sdev, struct snd_sof_dsp_ops *ops); 76651ec71dcSRanjani Sridharan 767dd96dacaSLiam Girdwood #endif 768