1dd96dacaSLiam Girdwood /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */ 2dd96dacaSLiam Girdwood /* 3dd96dacaSLiam Girdwood * This file is provided under a dual BSD/GPLv2 license. When using or 4dd96dacaSLiam Girdwood * redistributing this file, you may do so under either license. 5dd96dacaSLiam Girdwood * 6dd96dacaSLiam Girdwood * Copyright(c) 2017 Intel Corporation. All rights reserved. 7dd96dacaSLiam Girdwood * 8dd96dacaSLiam Girdwood * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com> 9dd96dacaSLiam Girdwood */ 10dd96dacaSLiam Girdwood 11dd96dacaSLiam Girdwood #ifndef __SOF_INTEL_HDA_H 12dd96dacaSLiam Girdwood #define __SOF_INTEL_HDA_H 13dd96dacaSLiam Girdwood 14dd96dacaSLiam Girdwood #include <sound/hda_codec.h> 15dd96dacaSLiam Girdwood #include <sound/hdaudio_ext.h> 16dd96dacaSLiam Girdwood #include "shim.h" 17dd96dacaSLiam Girdwood 18dd96dacaSLiam Girdwood /* PCI registers */ 19dd96dacaSLiam Girdwood #define PCI_TCSEL 0x44 20dd96dacaSLiam Girdwood #define PCI_PGCTL PCI_TCSEL 21dd96dacaSLiam Girdwood #define PCI_CGCTL 0x48 22dd96dacaSLiam Girdwood 23dd96dacaSLiam Girdwood /* PCI_PGCTL bits */ 24dd96dacaSLiam Girdwood #define PCI_PGCTL_ADSPPGD BIT(2) 25dd96dacaSLiam Girdwood #define PCI_PGCTL_LSRMD_MASK BIT(4) 26dd96dacaSLiam Girdwood 27dd96dacaSLiam Girdwood /* PCI_CGCTL bits */ 28dd96dacaSLiam Girdwood #define PCI_CGCTL_MISCBDCGE_MASK BIT(6) 29dd96dacaSLiam Girdwood #define PCI_CGCTL_ADSPDCGE BIT(1) 30dd96dacaSLiam Girdwood 31dd96dacaSLiam Girdwood /* Legacy HDA registers and bits used - widths are variable */ 32dd96dacaSLiam Girdwood #define SOF_HDA_GCAP 0x0 33dd96dacaSLiam Girdwood #define SOF_HDA_GCTL 0x8 34dd96dacaSLiam Girdwood /* accept unsol. response enable */ 35dd96dacaSLiam Girdwood #define SOF_HDA_GCTL_UNSOL BIT(8) 36dd96dacaSLiam Girdwood #define SOF_HDA_LLCH 0x14 37dd96dacaSLiam Girdwood #define SOF_HDA_INTCTL 0x20 38dd96dacaSLiam Girdwood #define SOF_HDA_INTSTS 0x24 39dd96dacaSLiam Girdwood #define SOF_HDA_WAKESTS 0x0E 40dd96dacaSLiam Girdwood #define SOF_HDA_WAKESTS_INT_MASK ((1 << 8) - 1) 41dd96dacaSLiam Girdwood #define SOF_HDA_RIRBSTS 0x5d 42dd96dacaSLiam Girdwood #define SOF_HDA_VS_EM2_L1SEN BIT(13) 43dd96dacaSLiam Girdwood 44dd96dacaSLiam Girdwood /* SOF_HDA_GCTL register bist */ 45dd96dacaSLiam Girdwood #define SOF_HDA_GCTL_RESET BIT(0) 46dd96dacaSLiam Girdwood 47dd96dacaSLiam Girdwood /* SOF_HDA_INCTL and SOF_HDA_INTSTS regs */ 48dd96dacaSLiam Girdwood #define SOF_HDA_INT_GLOBAL_EN BIT(31) 49dd96dacaSLiam Girdwood #define SOF_HDA_INT_CTRL_EN BIT(30) 50dd96dacaSLiam Girdwood #define SOF_HDA_INT_ALL_STREAM 0xff 51dd96dacaSLiam Girdwood 52dd96dacaSLiam Girdwood #define SOF_HDA_MAX_CAPS 10 53dd96dacaSLiam Girdwood #define SOF_HDA_CAP_ID_OFF 16 54dd96dacaSLiam Girdwood #define SOF_HDA_CAP_ID_MASK GENMASK(SOF_HDA_CAP_ID_OFF + 11,\ 55dd96dacaSLiam Girdwood SOF_HDA_CAP_ID_OFF) 56dd96dacaSLiam Girdwood #define SOF_HDA_CAP_NEXT_MASK 0xFFFF 57dd96dacaSLiam Girdwood 58dd96dacaSLiam Girdwood #define SOF_HDA_GTS_CAP_ID 0x1 59dd96dacaSLiam Girdwood #define SOF_HDA_ML_CAP_ID 0x2 60dd96dacaSLiam Girdwood 61dd96dacaSLiam Girdwood #define SOF_HDA_PP_CAP_ID 0x3 62dd96dacaSLiam Girdwood #define SOF_HDA_REG_PP_PPCH 0x10 63dd96dacaSLiam Girdwood #define SOF_HDA_REG_PP_PPCTL 0x04 64dd96dacaSLiam Girdwood #define SOF_HDA_PPCTL_PIE BIT(31) 65dd96dacaSLiam Girdwood #define SOF_HDA_PPCTL_GPROCEN BIT(30) 66dd96dacaSLiam Girdwood 67dd96dacaSLiam Girdwood /* DPIB entry size: 8 Bytes = 2 DWords */ 68dd96dacaSLiam Girdwood #define SOF_HDA_DPIB_ENTRY_SIZE 0x8 69dd96dacaSLiam Girdwood 70dd96dacaSLiam Girdwood #define SOF_HDA_SPIB_CAP_ID 0x4 71dd96dacaSLiam Girdwood #define SOF_HDA_DRSM_CAP_ID 0x5 72dd96dacaSLiam Girdwood 73dd96dacaSLiam Girdwood #define SOF_HDA_SPIB_BASE 0x08 74dd96dacaSLiam Girdwood #define SOF_HDA_SPIB_INTERVAL 0x08 75dd96dacaSLiam Girdwood #define SOF_HDA_SPIB_SPIB 0x00 76dd96dacaSLiam Girdwood #define SOF_HDA_SPIB_MAXFIFO 0x04 77dd96dacaSLiam Girdwood 78dd96dacaSLiam Girdwood #define SOF_HDA_PPHC_BASE 0x10 79dd96dacaSLiam Girdwood #define SOF_HDA_PPHC_INTERVAL 0x10 80dd96dacaSLiam Girdwood 81dd96dacaSLiam Girdwood #define SOF_HDA_PPLC_BASE 0x10 82dd96dacaSLiam Girdwood #define SOF_HDA_PPLC_MULTI 0x10 83dd96dacaSLiam Girdwood #define SOF_HDA_PPLC_INTERVAL 0x10 84dd96dacaSLiam Girdwood 85dd96dacaSLiam Girdwood #define SOF_HDA_DRSM_BASE 0x08 86dd96dacaSLiam Girdwood #define SOF_HDA_DRSM_INTERVAL 0x08 87dd96dacaSLiam Girdwood 88dd96dacaSLiam Girdwood /* Descriptor error interrupt */ 89dd96dacaSLiam Girdwood #define SOF_HDA_CL_DMA_SD_INT_DESC_ERR 0x10 90dd96dacaSLiam Girdwood 91dd96dacaSLiam Girdwood /* FIFO error interrupt */ 92dd96dacaSLiam Girdwood #define SOF_HDA_CL_DMA_SD_INT_FIFO_ERR 0x08 93dd96dacaSLiam Girdwood 94dd96dacaSLiam Girdwood /* Buffer completion interrupt */ 95dd96dacaSLiam Girdwood #define SOF_HDA_CL_DMA_SD_INT_COMPLETE 0x04 96dd96dacaSLiam Girdwood 97dd96dacaSLiam Girdwood #define SOF_HDA_CL_DMA_SD_INT_MASK \ 98dd96dacaSLiam Girdwood (SOF_HDA_CL_DMA_SD_INT_DESC_ERR | \ 99dd96dacaSLiam Girdwood SOF_HDA_CL_DMA_SD_INT_FIFO_ERR | \ 100dd96dacaSLiam Girdwood SOF_HDA_CL_DMA_SD_INT_COMPLETE) 101dd96dacaSLiam Girdwood #define SOF_HDA_SD_CTL_DMA_START 0x02 /* Stream DMA start bit */ 102dd96dacaSLiam Girdwood 103dd96dacaSLiam Girdwood /* Intel HD Audio Code Loader DMA Registers */ 104dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_LOADER_BASE 0x80 105dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_DPLBASE 0x70 106dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_DPUBASE 0x74 107dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_DPLBASE_ENABLE 0x01 108dd96dacaSLiam Girdwood 109dd96dacaSLiam Girdwood /* Stream Registers */ 110dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SD_CTL 0x00 111dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SD_STS 0x03 112dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SD_LPIB 0x04 113dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SD_CBL 0x08 114dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SD_LVI 0x0C 115dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SD_FIFOW 0x0E 116dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SD_FIFOSIZE 0x10 117dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SD_FORMAT 0x12 118dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SD_FIFOL 0x14 119dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SD_BDLPL 0x18 120dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SD_BDLPU 0x1C 121dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_SD_ENTRY_SIZE 0x20 122dd96dacaSLiam Girdwood 123dd96dacaSLiam Girdwood /* CL: Software Position Based FIFO Capability Registers */ 124dd96dacaSLiam Girdwood #define SOF_DSP_REG_CL_SPBFIFO \ 125dd96dacaSLiam Girdwood (SOF_HDA_ADSP_LOADER_BASE + 0x20) 126dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCH 0x0 127dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCCTL 0x4 128dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPIB 0x8 129dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SPBFIFO_MAXFIFOS 0xc 130dd96dacaSLiam Girdwood 131dd96dacaSLiam Girdwood /* Stream Number */ 132dd96dacaSLiam Girdwood #define SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT 20 133dd96dacaSLiam Girdwood #define SOF_HDA_CL_SD_CTL_STREAM_TAG_MASK \ 134dd96dacaSLiam Girdwood GENMASK(SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT + 3,\ 135dd96dacaSLiam Girdwood SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT) 136dd96dacaSLiam Girdwood 137dd96dacaSLiam Girdwood #define HDA_DSP_HDA_BAR 0 138dd96dacaSLiam Girdwood #define HDA_DSP_PP_BAR 1 139dd96dacaSLiam Girdwood #define HDA_DSP_SPIB_BAR 2 140dd96dacaSLiam Girdwood #define HDA_DSP_DRSM_BAR 3 141dd96dacaSLiam Girdwood #define HDA_DSP_BAR 4 142dd96dacaSLiam Girdwood 143dd96dacaSLiam Girdwood #define SRAM_WINDOW_OFFSET(x) (0x80000 + (x) * 0x20000) 144dd96dacaSLiam Girdwood 145dd96dacaSLiam Girdwood #define HDA_DSP_MBOX_OFFSET SRAM_WINDOW_OFFSET(0) 146dd96dacaSLiam Girdwood 147dd96dacaSLiam Girdwood #define HDA_DSP_PANIC_OFFSET(x) \ 148dd96dacaSLiam Girdwood (((x) & 0xFFFFFF) + HDA_DSP_MBOX_OFFSET) 149dd96dacaSLiam Girdwood 150dd96dacaSLiam Girdwood /* SRAM window 0 FW "registers" */ 151dd96dacaSLiam Girdwood #define HDA_DSP_SRAM_REG_ROM_STATUS (HDA_DSP_MBOX_OFFSET + 0x0) 152dd96dacaSLiam Girdwood #define HDA_DSP_SRAM_REG_ROM_ERROR (HDA_DSP_MBOX_OFFSET + 0x4) 153dd96dacaSLiam Girdwood /* FW and ROM share offset 4 */ 154dd96dacaSLiam Girdwood #define HDA_DSP_SRAM_REG_FW_STATUS (HDA_DSP_MBOX_OFFSET + 0x4) 155dd96dacaSLiam Girdwood #define HDA_DSP_SRAM_REG_FW_TRACEP (HDA_DSP_MBOX_OFFSET + 0x8) 156dd96dacaSLiam Girdwood #define HDA_DSP_SRAM_REG_FW_END (HDA_DSP_MBOX_OFFSET + 0xc) 157dd96dacaSLiam Girdwood 158dd96dacaSLiam Girdwood #define HDA_DSP_MBOX_UPLINK_OFFSET 0x81000 159dd96dacaSLiam Girdwood 160dd96dacaSLiam Girdwood #define HDA_DSP_STREAM_RESET_TIMEOUT 300 161dd96dacaSLiam Girdwood #define HDA_DSP_CL_TRIGGER_TIMEOUT 300 162dd96dacaSLiam Girdwood 163dd96dacaSLiam Girdwood #define HDA_DSP_SPIB_ENABLE 1 164dd96dacaSLiam Girdwood #define HDA_DSP_SPIB_DISABLE 0 165dd96dacaSLiam Girdwood 166dd96dacaSLiam Girdwood #define SOF_HDA_MAX_BUFFER_SIZE (32 * PAGE_SIZE) 167dd96dacaSLiam Girdwood 168dd96dacaSLiam Girdwood #define HDA_DSP_STACK_DUMP_SIZE 32 169dd96dacaSLiam Girdwood 170dd96dacaSLiam Girdwood /* ROM status/error values */ 171dd96dacaSLiam Girdwood #define HDA_DSP_ROM_STS_MASK 0xf 172dd96dacaSLiam Girdwood #define HDA_DSP_ROM_INIT 0x1 173dd96dacaSLiam Girdwood #define HDA_DSP_ROM_FW_MANIFEST_LOADED 0x3 174dd96dacaSLiam Girdwood #define HDA_DSP_ROM_FW_FW_LOADED 0x4 175dd96dacaSLiam Girdwood #define HDA_DSP_ROM_FW_ENTERED 0x5 176dd96dacaSLiam Girdwood #define HDA_DSP_ROM_RFW_START 0xf 177dd96dacaSLiam Girdwood #define HDA_DSP_ROM_CSE_ERROR 40 178dd96dacaSLiam Girdwood #define HDA_DSP_ROM_CSE_WRONG_RESPONSE 41 179dd96dacaSLiam Girdwood #define HDA_DSP_ROM_IMR_TO_SMALL 42 180dd96dacaSLiam Girdwood #define HDA_DSP_ROM_BASE_FW_NOT_FOUND 43 181dd96dacaSLiam Girdwood #define HDA_DSP_ROM_CSE_VALIDATION_FAILED 44 182dd96dacaSLiam Girdwood #define HDA_DSP_ROM_IPC_FATAL_ERROR 45 183dd96dacaSLiam Girdwood #define HDA_DSP_ROM_L2_CACHE_ERROR 46 184dd96dacaSLiam Girdwood #define HDA_DSP_ROM_LOAD_OFFSET_TO_SMALL 47 185dd96dacaSLiam Girdwood #define HDA_DSP_ROM_API_PTR_INVALID 50 186dd96dacaSLiam Girdwood #define HDA_DSP_ROM_BASEFW_INCOMPAT 51 187dd96dacaSLiam Girdwood #define HDA_DSP_ROM_UNHANDLED_INTERRUPT 0xBEE00000 188dd96dacaSLiam Girdwood #define HDA_DSP_ROM_MEMORY_HOLE_ECC 0xECC00000 189dd96dacaSLiam Girdwood #define HDA_DSP_ROM_KERNEL_EXCEPTION 0xCAFE0000 190dd96dacaSLiam Girdwood #define HDA_DSP_ROM_USER_EXCEPTION 0xBEEF0000 191dd96dacaSLiam Girdwood #define HDA_DSP_ROM_UNEXPECTED_RESET 0xDECAF000 192dd96dacaSLiam Girdwood #define HDA_DSP_ROM_NULL_FW_ENTRY 0x4c4c4e55 193dd96dacaSLiam Girdwood #define HDA_DSP_IPC_PURGE_FW 0x01004000 194dd96dacaSLiam Girdwood 195dd96dacaSLiam Girdwood /* various timeout values */ 196dd96dacaSLiam Girdwood #define HDA_DSP_PU_TIMEOUT 50 197dd96dacaSLiam Girdwood #define HDA_DSP_PD_TIMEOUT 50 198dd96dacaSLiam Girdwood #define HDA_DSP_RESET_TIMEOUT_US 50000 199dd96dacaSLiam Girdwood #define HDA_DSP_BASEFW_TIMEOUT_US 3000000 200dd96dacaSLiam Girdwood #define HDA_DSP_INIT_TIMEOUT_US 500000 201dd96dacaSLiam Girdwood #define HDA_DSP_CTRL_RESET_TIMEOUT 100 202dd96dacaSLiam Girdwood #define HDA_DSP_WAIT_TIMEOUT 500 /* 500 msec */ 203dd96dacaSLiam Girdwood #define HDA_DSP_REG_POLL_INTERVAL_US 500 /* 0.5 msec */ 204dd96dacaSLiam Girdwood 205dd96dacaSLiam Girdwood #define HDA_DSP_ADSPIC_IPC 1 206dd96dacaSLiam Girdwood #define HDA_DSP_ADSPIS_IPC 1 207dd96dacaSLiam Girdwood 208dd96dacaSLiam Girdwood /* Intel HD Audio General DSP Registers */ 209dd96dacaSLiam Girdwood #define HDA_DSP_GEN_BASE 0x0 210dd96dacaSLiam Girdwood #define HDA_DSP_REG_ADSPCS (HDA_DSP_GEN_BASE + 0x04) 211dd96dacaSLiam Girdwood #define HDA_DSP_REG_ADSPIC (HDA_DSP_GEN_BASE + 0x08) 212dd96dacaSLiam Girdwood #define HDA_DSP_REG_ADSPIS (HDA_DSP_GEN_BASE + 0x0C) 213dd96dacaSLiam Girdwood #define HDA_DSP_REG_ADSPIC2 (HDA_DSP_GEN_BASE + 0x10) 214dd96dacaSLiam Girdwood #define HDA_DSP_REG_ADSPIS2 (HDA_DSP_GEN_BASE + 0x14) 215dd96dacaSLiam Girdwood 216dd96dacaSLiam Girdwood /* Intel HD Audio Inter-Processor Communication Registers */ 217dd96dacaSLiam Girdwood #define HDA_DSP_IPC_BASE 0x40 218dd96dacaSLiam Girdwood #define HDA_DSP_REG_HIPCT (HDA_DSP_IPC_BASE + 0x00) 219dd96dacaSLiam Girdwood #define HDA_DSP_REG_HIPCTE (HDA_DSP_IPC_BASE + 0x04) 220dd96dacaSLiam Girdwood #define HDA_DSP_REG_HIPCI (HDA_DSP_IPC_BASE + 0x08) 221dd96dacaSLiam Girdwood #define HDA_DSP_REG_HIPCIE (HDA_DSP_IPC_BASE + 0x0C) 222dd96dacaSLiam Girdwood #define HDA_DSP_REG_HIPCCTL (HDA_DSP_IPC_BASE + 0x10) 223dd96dacaSLiam Girdwood 224dd96dacaSLiam Girdwood /* HIPCI */ 225dd96dacaSLiam Girdwood #define HDA_DSP_REG_HIPCI_BUSY BIT(31) 226dd96dacaSLiam Girdwood #define HDA_DSP_REG_HIPCI_MSG_MASK 0x7FFFFFFF 227dd96dacaSLiam Girdwood 228dd96dacaSLiam Girdwood /* HIPCIE */ 229dd96dacaSLiam Girdwood #define HDA_DSP_REG_HIPCIE_DONE BIT(30) 230dd96dacaSLiam Girdwood #define HDA_DSP_REG_HIPCIE_MSG_MASK 0x3FFFFFFF 231dd96dacaSLiam Girdwood 232dd96dacaSLiam Girdwood /* HIPCCTL */ 233dd96dacaSLiam Girdwood #define HDA_DSP_REG_HIPCCTL_DONE BIT(1) 234dd96dacaSLiam Girdwood #define HDA_DSP_REG_HIPCCTL_BUSY BIT(0) 235dd96dacaSLiam Girdwood 236dd96dacaSLiam Girdwood /* HIPCT */ 237dd96dacaSLiam Girdwood #define HDA_DSP_REG_HIPCT_BUSY BIT(31) 238dd96dacaSLiam Girdwood #define HDA_DSP_REG_HIPCT_MSG_MASK 0x7FFFFFFF 239dd96dacaSLiam Girdwood 240dd96dacaSLiam Girdwood /* HIPCTE */ 241dd96dacaSLiam Girdwood #define HDA_DSP_REG_HIPCTE_MSG_MASK 0x3FFFFFFF 242dd96dacaSLiam Girdwood 243dd96dacaSLiam Girdwood #define HDA_DSP_ADSPIC_CL_DMA 0x2 244dd96dacaSLiam Girdwood #define HDA_DSP_ADSPIS_CL_DMA 0x2 245dd96dacaSLiam Girdwood 246dd96dacaSLiam Girdwood /* Delay before scheduling D0i3 entry */ 247dd96dacaSLiam Girdwood #define BXT_D0I3_DELAY 5000 248dd96dacaSLiam Girdwood 249dd96dacaSLiam Girdwood #define FW_CL_STREAM_NUMBER 0x1 250dd96dacaSLiam Girdwood 251dd96dacaSLiam Girdwood /* ADSPCS - Audio DSP Control & Status */ 252dd96dacaSLiam Girdwood 253dd96dacaSLiam Girdwood /* 254dd96dacaSLiam Girdwood * Core Reset - asserted high 255dd96dacaSLiam Girdwood * CRST Mask for a given core mask pattern, cm 256dd96dacaSLiam Girdwood */ 257dd96dacaSLiam Girdwood #define HDA_DSP_ADSPCS_CRST_SHIFT 0 258dd96dacaSLiam Girdwood #define HDA_DSP_ADSPCS_CRST_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CRST_SHIFT) 259dd96dacaSLiam Girdwood 260dd96dacaSLiam Girdwood /* 261dd96dacaSLiam Girdwood * Core run/stall - when set to '1' core is stalled 262dd96dacaSLiam Girdwood * CSTALL Mask for a given core mask pattern, cm 263dd96dacaSLiam Girdwood */ 264dd96dacaSLiam Girdwood #define HDA_DSP_ADSPCS_CSTALL_SHIFT 8 265dd96dacaSLiam Girdwood #define HDA_DSP_ADSPCS_CSTALL_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CSTALL_SHIFT) 266dd96dacaSLiam Girdwood 267dd96dacaSLiam Girdwood /* 268dd96dacaSLiam Girdwood * Set Power Active - when set to '1' turn cores on 269dd96dacaSLiam Girdwood * SPA Mask for a given core mask pattern, cm 270dd96dacaSLiam Girdwood */ 271dd96dacaSLiam Girdwood #define HDA_DSP_ADSPCS_SPA_SHIFT 16 272dd96dacaSLiam Girdwood #define HDA_DSP_ADSPCS_SPA_MASK(cm) ((cm) << HDA_DSP_ADSPCS_SPA_SHIFT) 273dd96dacaSLiam Girdwood 274dd96dacaSLiam Girdwood /* 275dd96dacaSLiam Girdwood * Current Power Active - power status of cores, set by hardware 276dd96dacaSLiam Girdwood * CPA Mask for a given core mask pattern, cm 277dd96dacaSLiam Girdwood */ 278dd96dacaSLiam Girdwood #define HDA_DSP_ADSPCS_CPA_SHIFT 24 279dd96dacaSLiam Girdwood #define HDA_DSP_ADSPCS_CPA_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CPA_SHIFT) 280dd96dacaSLiam Girdwood 281dd96dacaSLiam Girdwood /* Mask for a given core index, c = 0.. number of supported cores - 1 */ 282dd96dacaSLiam Girdwood #define HDA_DSP_CORE_MASK(c) BIT(c) 283dd96dacaSLiam Girdwood 284dd96dacaSLiam Girdwood /* 285dd96dacaSLiam Girdwood * Mask for a given number of cores 286dd96dacaSLiam Girdwood * nc = number of supported cores 287dd96dacaSLiam Girdwood */ 288dd96dacaSLiam Girdwood #define SOF_DSP_CORES_MASK(nc) GENMASK(((nc) - 1), 0) 289dd96dacaSLiam Girdwood 290dd96dacaSLiam Girdwood /* Intel HD Audio Inter-Processor Communication Registers for Cannonlake*/ 291dd96dacaSLiam Girdwood #define CNL_DSP_IPC_BASE 0xc0 292dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCTDR (CNL_DSP_IPC_BASE + 0x00) 293dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCTDA (CNL_DSP_IPC_BASE + 0x04) 294dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCTDD (CNL_DSP_IPC_BASE + 0x08) 295dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCIDR (CNL_DSP_IPC_BASE + 0x10) 296dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCIDA (CNL_DSP_IPC_BASE + 0x14) 297dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCCTL (CNL_DSP_IPC_BASE + 0x28) 298dd96dacaSLiam Girdwood 299dd96dacaSLiam Girdwood /* HIPCI */ 300dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCIDR_BUSY BIT(31) 301dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCIDR_MSG_MASK 0x7FFFFFFF 302dd96dacaSLiam Girdwood 303dd96dacaSLiam Girdwood /* HIPCIE */ 304dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCIDA_DONE BIT(31) 305dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCIDA_MSG_MASK 0x7FFFFFFF 306dd96dacaSLiam Girdwood 307dd96dacaSLiam Girdwood /* HIPCCTL */ 308dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCCTL_DONE BIT(1) 309dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCCTL_BUSY BIT(0) 310dd96dacaSLiam Girdwood 311dd96dacaSLiam Girdwood /* HIPCT */ 312dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCTDR_BUSY BIT(31) 313dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCTDR_MSG_MASK 0x7FFFFFFF 314dd96dacaSLiam Girdwood 315dd96dacaSLiam Girdwood /* HIPCTDA */ 316dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCTDA_DONE BIT(31) 317dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCTDA_MSG_MASK 0x7FFFFFFF 318dd96dacaSLiam Girdwood 319dd96dacaSLiam Girdwood /* HIPCTDD */ 320dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCTDD_MSG_MASK 0x7FFFFFFF 321dd96dacaSLiam Girdwood 322dd96dacaSLiam Girdwood /* BDL */ 323dd96dacaSLiam Girdwood #define HDA_DSP_BDL_SIZE 4096 324dd96dacaSLiam Girdwood #define HDA_DSP_MAX_BDL_ENTRIES \ 325dd96dacaSLiam Girdwood (HDA_DSP_BDL_SIZE / sizeof(struct sof_intel_dsp_bdl)) 326dd96dacaSLiam Girdwood 327dd96dacaSLiam Girdwood /* Number of DAIs */ 328dd96dacaSLiam Girdwood #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) 329dd96dacaSLiam Girdwood #define SOF_SKL_NUM_DAIS 14 330dd96dacaSLiam Girdwood #else 331dd96dacaSLiam Girdwood #define SOF_SKL_NUM_DAIS 8 332dd96dacaSLiam Girdwood #endif 333dd96dacaSLiam Girdwood 334dd96dacaSLiam Girdwood /* Intel HD Audio SRAM Window 0*/ 335dd96dacaSLiam Girdwood #define HDA_ADSP_SRAM0_BASE_SKL 0x8000 336dd96dacaSLiam Girdwood 337dd96dacaSLiam Girdwood /* Firmware status window */ 338dd96dacaSLiam Girdwood #define HDA_ADSP_FW_STATUS_SKL HDA_ADSP_SRAM0_BASE_SKL 339dd96dacaSLiam Girdwood #define HDA_ADSP_ERROR_CODE_SKL (HDA_ADSP_FW_STATUS_SKL + 0x4) 340dd96dacaSLiam Girdwood 341df7e0de5SZhu Yingjiang /* Host Device Memory Space */ 342df7e0de5SZhu Yingjiang #define APL_SSP_BASE_OFFSET 0x2000 343df7e0de5SZhu Yingjiang #define CNL_SSP_BASE_OFFSET 0x10000 344df7e0de5SZhu Yingjiang 345df7e0de5SZhu Yingjiang /* Host Device Memory Size of a Single SSP */ 346df7e0de5SZhu Yingjiang #define SSP_DEV_MEM_SIZE 0x1000 347df7e0de5SZhu Yingjiang 348b095fe47SZhu Yingjiang /* SSP Count of the Platform */ 349b095fe47SZhu Yingjiang #define APL_SSP_COUNT 6 350b095fe47SZhu Yingjiang #define CNL_SSP_COUNT 3 351b095fe47SZhu Yingjiang 35274ed4097SZhu Yingjiang /* SSP Registers */ 35374ed4097SZhu Yingjiang #define SSP_SSC1_OFFSET 0x4 35474ed4097SZhu Yingjiang #define SSP_SET_SCLK_SLAVE BIT(25) 35574ed4097SZhu Yingjiang #define SSP_SET_SFRM_SLAVE BIT(24) 35674ed4097SZhu Yingjiang #define SSP_SET_SLAVE (SSP_SET_SCLK_SLAVE | SSP_SET_SFRM_SLAVE) 35774ed4097SZhu Yingjiang 358dd96dacaSLiam Girdwood #define HDA_IDISP_CODEC(x) ((x) & BIT(2)) 359dd96dacaSLiam Girdwood 360dd96dacaSLiam Girdwood struct sof_intel_dsp_bdl { 361dd96dacaSLiam Girdwood __le32 addr_l; 362dd96dacaSLiam Girdwood __le32 addr_h; 363dd96dacaSLiam Girdwood __le32 size; 364dd96dacaSLiam Girdwood __le32 ioc; 365dd96dacaSLiam Girdwood } __attribute((packed)); 366dd96dacaSLiam Girdwood 367dd96dacaSLiam Girdwood #define SOF_HDA_PLAYBACK_STREAMS 16 368dd96dacaSLiam Girdwood #define SOF_HDA_CAPTURE_STREAMS 16 369dd96dacaSLiam Girdwood #define SOF_HDA_PLAYBACK 0 370dd96dacaSLiam Girdwood #define SOF_HDA_CAPTURE 1 371dd96dacaSLiam Girdwood 372dd96dacaSLiam Girdwood /* represents DSP HDA controller frontend - i.e. host facing control */ 373dd96dacaSLiam Girdwood struct sof_intel_hda_dev { 374dd96dacaSLiam Girdwood 375dd96dacaSLiam Girdwood struct hda_bus hbus; 376dd96dacaSLiam Girdwood 377dd96dacaSLiam Girdwood /* hw config */ 378dd96dacaSLiam Girdwood const struct sof_intel_dsp_desc *desc; 379dd96dacaSLiam Girdwood 380dd96dacaSLiam Girdwood /* trace */ 381dd96dacaSLiam Girdwood struct hdac_ext_stream *dtrace_stream; 382dd96dacaSLiam Girdwood 383dd96dacaSLiam Girdwood /* if position update IPC needed */ 384dd96dacaSLiam Girdwood u32 no_ipc_position; 385dd96dacaSLiam Girdwood 386e8e55dbeSKeyon Jie /* the maximum number of streams (playback + capture) supported */ 387e8e55dbeSKeyon Jie u32 stream_max; 388e8e55dbeSKeyon Jie 389dd96dacaSLiam Girdwood int irq; 390dd96dacaSLiam Girdwood 391dd96dacaSLiam Girdwood /* DMIC device */ 392dd96dacaSLiam Girdwood struct platform_device *dmic_dev; 393dd96dacaSLiam Girdwood }; 394dd96dacaSLiam Girdwood 395dd96dacaSLiam Girdwood static inline struct hdac_bus *sof_to_bus(struct snd_sof_dev *s) 396dd96dacaSLiam Girdwood { 397dd96dacaSLiam Girdwood struct sof_intel_hda_dev *hda = s->pdata->hw_pdata; 398dd96dacaSLiam Girdwood 399dd96dacaSLiam Girdwood return &hda->hbus.core; 400dd96dacaSLiam Girdwood } 401dd96dacaSLiam Girdwood 402dd96dacaSLiam Girdwood static inline struct hda_bus *sof_to_hbus(struct snd_sof_dev *s) 403dd96dacaSLiam Girdwood { 404dd96dacaSLiam Girdwood struct sof_intel_hda_dev *hda = s->pdata->hw_pdata; 405dd96dacaSLiam Girdwood 406dd96dacaSLiam Girdwood return &hda->hbus; 407dd96dacaSLiam Girdwood } 408dd96dacaSLiam Girdwood 409dd96dacaSLiam Girdwood struct sof_intel_hda_stream { 410dd96dacaSLiam Girdwood struct hdac_ext_stream hda_stream; 411dd96dacaSLiam Girdwood struct sof_intel_stream stream; 412ed3baacdSRanjani Sridharan int hw_params_upon_resume; /* set up hw_params upon resume */ 413dd96dacaSLiam Girdwood }; 414dd96dacaSLiam Girdwood 415dd96dacaSLiam Girdwood #define bus_to_sof_hda(bus) \ 416dd96dacaSLiam Girdwood container_of(bus, struct sof_intel_hda_dev, hbus.core) 417dd96dacaSLiam Girdwood 418dd96dacaSLiam Girdwood #define SOF_STREAM_SD_OFFSET(s) \ 419dd96dacaSLiam Girdwood (SOF_HDA_ADSP_SD_ENTRY_SIZE * ((s)->index) \ 420dd96dacaSLiam Girdwood + SOF_HDA_ADSP_LOADER_BASE) 421dd96dacaSLiam Girdwood 422dd96dacaSLiam Girdwood /* 423dd96dacaSLiam Girdwood * DSP Core services. 424dd96dacaSLiam Girdwood */ 425dd96dacaSLiam Girdwood int hda_dsp_probe(struct snd_sof_dev *sdev); 426dd96dacaSLiam Girdwood int hda_dsp_remove(struct snd_sof_dev *sdev); 427dd96dacaSLiam Girdwood int hda_dsp_core_reset_enter(struct snd_sof_dev *sdev, 428dd96dacaSLiam Girdwood unsigned int core_mask); 429dd96dacaSLiam Girdwood int hda_dsp_core_reset_leave(struct snd_sof_dev *sdev, 430dd96dacaSLiam Girdwood unsigned int core_mask); 431dd96dacaSLiam Girdwood int hda_dsp_core_stall_reset(struct snd_sof_dev *sdev, unsigned int core_mask); 432dd96dacaSLiam Girdwood int hda_dsp_core_run(struct snd_sof_dev *sdev, unsigned int core_mask); 433dd96dacaSLiam Girdwood int hda_dsp_core_power_up(struct snd_sof_dev *sdev, unsigned int core_mask); 434dd96dacaSLiam Girdwood int hda_dsp_enable_core(struct snd_sof_dev *sdev, unsigned int core_mask); 435dd96dacaSLiam Girdwood int hda_dsp_core_power_down(struct snd_sof_dev *sdev, unsigned int core_mask); 436dd96dacaSLiam Girdwood bool hda_dsp_core_is_enabled(struct snd_sof_dev *sdev, 437dd96dacaSLiam Girdwood unsigned int core_mask); 438dd96dacaSLiam Girdwood int hda_dsp_core_reset_power_down(struct snd_sof_dev *sdev, 439dd96dacaSLiam Girdwood unsigned int core_mask); 440dd96dacaSLiam Girdwood void hda_dsp_ipc_int_enable(struct snd_sof_dev *sdev); 441dd96dacaSLiam Girdwood void hda_dsp_ipc_int_disable(struct snd_sof_dev *sdev); 442dd96dacaSLiam Girdwood 443dd96dacaSLiam Girdwood int hda_dsp_suspend(struct snd_sof_dev *sdev, int state); 444dd96dacaSLiam Girdwood int hda_dsp_resume(struct snd_sof_dev *sdev); 445dd96dacaSLiam Girdwood int hda_dsp_runtime_suspend(struct snd_sof_dev *sdev, int state); 446dd96dacaSLiam Girdwood int hda_dsp_runtime_resume(struct snd_sof_dev *sdev); 447ed3baacdSRanjani Sridharan void hda_dsp_set_hw_params_upon_resume(struct snd_sof_dev *sdev); 448dd96dacaSLiam Girdwood void hda_dsp_dump_skl(struct snd_sof_dev *sdev, u32 flags); 449dd96dacaSLiam Girdwood void hda_dsp_dump(struct snd_sof_dev *sdev, u32 flags); 450dd96dacaSLiam Girdwood 451dd96dacaSLiam Girdwood /* 452dd96dacaSLiam Girdwood * DSP PCM Operations. 453dd96dacaSLiam Girdwood */ 454dd96dacaSLiam Girdwood int hda_dsp_pcm_open(struct snd_sof_dev *sdev, 455dd96dacaSLiam Girdwood struct snd_pcm_substream *substream); 456dd96dacaSLiam Girdwood int hda_dsp_pcm_close(struct snd_sof_dev *sdev, 457dd96dacaSLiam Girdwood struct snd_pcm_substream *substream); 458dd96dacaSLiam Girdwood int hda_dsp_pcm_hw_params(struct snd_sof_dev *sdev, 459dd96dacaSLiam Girdwood struct snd_pcm_substream *substream, 460dd96dacaSLiam Girdwood struct snd_pcm_hw_params *params, 461dd96dacaSLiam Girdwood struct sof_ipc_stream_params *ipc_params); 462dd96dacaSLiam Girdwood int hda_dsp_pcm_trigger(struct snd_sof_dev *sdev, 463dd96dacaSLiam Girdwood struct snd_pcm_substream *substream, int cmd); 464dd96dacaSLiam Girdwood snd_pcm_uframes_t hda_dsp_pcm_pointer(struct snd_sof_dev *sdev, 465dd96dacaSLiam Girdwood struct snd_pcm_substream *substream); 466dd96dacaSLiam Girdwood 467dd96dacaSLiam Girdwood /* 468dd96dacaSLiam Girdwood * DSP Stream Operations. 469dd96dacaSLiam Girdwood */ 470dd96dacaSLiam Girdwood 471dd96dacaSLiam Girdwood int hda_dsp_stream_init(struct snd_sof_dev *sdev); 472dd96dacaSLiam Girdwood void hda_dsp_stream_free(struct snd_sof_dev *sdev); 473dd96dacaSLiam Girdwood int hda_dsp_stream_hw_params(struct snd_sof_dev *sdev, 474dd96dacaSLiam Girdwood struct hdac_ext_stream *stream, 475dd96dacaSLiam Girdwood struct snd_dma_buffer *dmab, 476dd96dacaSLiam Girdwood struct snd_pcm_hw_params *params); 477dd96dacaSLiam Girdwood int hda_dsp_stream_trigger(struct snd_sof_dev *sdev, 478dd96dacaSLiam Girdwood struct hdac_ext_stream *stream, int cmd); 479dd96dacaSLiam Girdwood irqreturn_t hda_dsp_stream_interrupt(int irq, void *context); 480dd96dacaSLiam Girdwood irqreturn_t hda_dsp_stream_threaded_handler(int irq, void *context); 481dd96dacaSLiam Girdwood int hda_dsp_stream_setup_bdl(struct snd_sof_dev *sdev, 482dd96dacaSLiam Girdwood struct snd_dma_buffer *dmab, 483dd96dacaSLiam Girdwood struct hdac_stream *stream); 484dd96dacaSLiam Girdwood 485dd96dacaSLiam Girdwood struct hdac_ext_stream * 486dd96dacaSLiam Girdwood hda_dsp_stream_get(struct snd_sof_dev *sdev, int direction); 487dd96dacaSLiam Girdwood int hda_dsp_stream_put(struct snd_sof_dev *sdev, int direction, int stream_tag); 488dd96dacaSLiam Girdwood int hda_dsp_stream_spib_config(struct snd_sof_dev *sdev, 489dd96dacaSLiam Girdwood struct hdac_ext_stream *stream, 490dd96dacaSLiam Girdwood int enable, u32 size); 491dd96dacaSLiam Girdwood 492dd96dacaSLiam Girdwood void hda_ipc_msg_data(struct snd_sof_dev *sdev, 493dd96dacaSLiam Girdwood struct snd_pcm_substream *substream, 494dd96dacaSLiam Girdwood void *p, size_t sz); 495dd96dacaSLiam Girdwood int hda_ipc_pcm_params(struct snd_sof_dev *sdev, 496dd96dacaSLiam Girdwood struct snd_pcm_substream *substream, 497dd96dacaSLiam Girdwood const struct sof_ipc_pcm_params_reply *reply); 498dd96dacaSLiam Girdwood 499dd96dacaSLiam Girdwood /* 500dd96dacaSLiam Girdwood * DSP IPC Operations. 501dd96dacaSLiam Girdwood */ 502dd96dacaSLiam Girdwood int hda_dsp_ipc_send_msg(struct snd_sof_dev *sdev, 503dd96dacaSLiam Girdwood struct snd_sof_ipc_msg *msg); 504dd96dacaSLiam Girdwood void hda_dsp_ipc_get_reply(struct snd_sof_dev *sdev); 505dd96dacaSLiam Girdwood int hda_dsp_ipc_fw_ready(struct snd_sof_dev *sdev, u32 msg_id); 506dd96dacaSLiam Girdwood irqreturn_t hda_dsp_ipc_irq_handler(int irq, void *context); 507dd96dacaSLiam Girdwood irqreturn_t hda_dsp_ipc_irq_thread(int irq, void *context); 508dd96dacaSLiam Girdwood int hda_dsp_ipc_cmd_done(struct snd_sof_dev *sdev, int dir); 509dd96dacaSLiam Girdwood 510dd96dacaSLiam Girdwood /* 511dd96dacaSLiam Girdwood * DSP Code loader. 512dd96dacaSLiam Girdwood */ 513dd96dacaSLiam Girdwood int hda_dsp_cl_boot_firmware(struct snd_sof_dev *sdev); 514dd96dacaSLiam Girdwood int hda_dsp_cl_boot_firmware_skl(struct snd_sof_dev *sdev); 515dd96dacaSLiam Girdwood 516dd96dacaSLiam Girdwood /* pre and post fw run ops */ 517dd96dacaSLiam Girdwood int hda_dsp_pre_fw_run(struct snd_sof_dev *sdev); 518dd96dacaSLiam Girdwood int hda_dsp_post_fw_run(struct snd_sof_dev *sdev); 519dd96dacaSLiam Girdwood 520dd96dacaSLiam Girdwood /* 521dd96dacaSLiam Girdwood * HDA Controller Operations. 522dd96dacaSLiam Girdwood */ 523dd96dacaSLiam Girdwood int hda_dsp_ctrl_get_caps(struct snd_sof_dev *sdev); 524dd96dacaSLiam Girdwood void hda_dsp_ctrl_ppcap_enable(struct snd_sof_dev *sdev, bool enable); 525dd96dacaSLiam Girdwood void hda_dsp_ctrl_ppcap_int_enable(struct snd_sof_dev *sdev, bool enable); 526dd96dacaSLiam Girdwood int hda_dsp_ctrl_link_reset(struct snd_sof_dev *sdev, bool reset); 527dd96dacaSLiam Girdwood void hda_dsp_ctrl_misc_clock_gating(struct snd_sof_dev *sdev, bool enable); 528dd96dacaSLiam Girdwood int hda_dsp_ctrl_clock_power_gating(struct snd_sof_dev *sdev, bool enable); 529dd96dacaSLiam Girdwood int hda_dsp_ctrl_init_chip(struct snd_sof_dev *sdev, bool full_reset); 530dd96dacaSLiam Girdwood 531dd96dacaSLiam Girdwood /* 532dd96dacaSLiam Girdwood * HDA bus operations. 533dd96dacaSLiam Girdwood */ 534dd96dacaSLiam Girdwood void sof_hda_bus_init(struct hdac_bus *bus, struct device *dev, 535dd96dacaSLiam Girdwood const struct hdac_ext_bus_ops *ext_ops); 536dd96dacaSLiam Girdwood 537dd96dacaSLiam Girdwood #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) 538dd96dacaSLiam Girdwood /* 539dd96dacaSLiam Girdwood * HDA Codec operations. 540dd96dacaSLiam Girdwood */ 541dd96dacaSLiam Girdwood int hda_codec_probe_bus(struct snd_sof_dev *sdev); 542dd96dacaSLiam Girdwood 543dd96dacaSLiam Girdwood #endif /* CONFIG_SND_SOC_SOF_HDA */ 544dd96dacaSLiam Girdwood 545dd96dacaSLiam Girdwood #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) && IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI) 546dd96dacaSLiam Girdwood 547dd96dacaSLiam Girdwood void hda_codec_i915_get(struct snd_sof_dev *sdev); 548dd96dacaSLiam Girdwood void hda_codec_i915_put(struct snd_sof_dev *sdev); 549dd96dacaSLiam Girdwood int hda_codec_i915_init(struct snd_sof_dev *sdev); 550dd96dacaSLiam Girdwood int hda_codec_i915_exit(struct snd_sof_dev *sdev); 551dd96dacaSLiam Girdwood 552dd96dacaSLiam Girdwood #else 553dd96dacaSLiam Girdwood 554dd96dacaSLiam Girdwood static inline void hda_codec_i915_get(struct snd_sof_dev *sdev) { } 555dd96dacaSLiam Girdwood static inline void hda_codec_i915_put(struct snd_sof_dev *sdev) { } 556dd96dacaSLiam Girdwood static inline int hda_codec_i915_init(struct snd_sof_dev *sdev) { return 0; } 557dd96dacaSLiam Girdwood static inline int hda_codec_i915_exit(struct snd_sof_dev *sdev) { return 0; } 558dd96dacaSLiam Girdwood 559dd96dacaSLiam Girdwood #endif /* CONFIG_SND_SOC_SOF_HDA && CONFIG_SND_SOC_HDAC_HDMI */ 560dd96dacaSLiam Girdwood 561dd96dacaSLiam Girdwood /* 562dd96dacaSLiam Girdwood * Trace Control. 563dd96dacaSLiam Girdwood */ 564dd96dacaSLiam Girdwood int hda_dsp_trace_init(struct snd_sof_dev *sdev, u32 *stream_tag); 565dd96dacaSLiam Girdwood int hda_dsp_trace_release(struct snd_sof_dev *sdev); 566dd96dacaSLiam Girdwood int hda_dsp_trace_trigger(struct snd_sof_dev *sdev, int cmd); 567dd96dacaSLiam Girdwood 568dd96dacaSLiam Girdwood /* common dai driver */ 569dd96dacaSLiam Girdwood extern struct snd_soc_dai_driver skl_dai[]; 570dd96dacaSLiam Girdwood 571dd96dacaSLiam Girdwood /* 572dd96dacaSLiam Girdwood * Platform Specific HW abstraction Ops. 573dd96dacaSLiam Girdwood */ 574dd96dacaSLiam Girdwood extern const struct snd_sof_dsp_ops sof_apl_ops; 575dd96dacaSLiam Girdwood extern const struct snd_sof_dsp_ops sof_cnl_ops; 576dd96dacaSLiam Girdwood extern const struct snd_sof_dsp_ops sof_skl_ops; 577dd96dacaSLiam Girdwood 578dd96dacaSLiam Girdwood extern const struct sof_intel_dsp_desc apl_chip_info; 579dd96dacaSLiam Girdwood extern const struct sof_intel_dsp_desc cnl_chip_info; 580dd96dacaSLiam Girdwood extern const struct sof_intel_dsp_desc skl_chip_info; 581dd96dacaSLiam Girdwood 582dd96dacaSLiam Girdwood #endif 583