1e149ca29SPierre-Louis Bossart /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ 2dd96dacaSLiam Girdwood /* 3dd96dacaSLiam Girdwood * This file is provided under a dual BSD/GPLv2 license. When using or 4dd96dacaSLiam Girdwood * redistributing this file, you may do so under either license. 5dd96dacaSLiam Girdwood * 6dd96dacaSLiam Girdwood * Copyright(c) 2017 Intel Corporation. All rights reserved. 7dd96dacaSLiam Girdwood * 8dd96dacaSLiam Girdwood * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com> 9dd96dacaSLiam Girdwood */ 10dd96dacaSLiam Girdwood 11dd96dacaSLiam Girdwood #ifndef __SOF_INTEL_HDA_H 12dd96dacaSLiam Girdwood #define __SOF_INTEL_HDA_H 13dd96dacaSLiam Girdwood 1451dfed1eSPierre-Louis Bossart #include <linux/soundwire/sdw.h> 1551dfed1eSPierre-Louis Bossart #include <linux/soundwire/sdw_intel.h> 164c414da9SCezary Rojewski #include <sound/compress_driver.h> 17dd96dacaSLiam Girdwood #include <sound/hda_codec.h> 18dd96dacaSLiam Girdwood #include <sound/hdaudio_ext.h> 19dd96dacaSLiam Girdwood #include "shim.h" 20dd96dacaSLiam Girdwood 21dd96dacaSLiam Girdwood /* PCI registers */ 22dd96dacaSLiam Girdwood #define PCI_TCSEL 0x44 23dd96dacaSLiam Girdwood #define PCI_PGCTL PCI_TCSEL 24dd96dacaSLiam Girdwood #define PCI_CGCTL 0x48 25dd96dacaSLiam Girdwood 26dd96dacaSLiam Girdwood /* PCI_PGCTL bits */ 27dd96dacaSLiam Girdwood #define PCI_PGCTL_ADSPPGD BIT(2) 28dd96dacaSLiam Girdwood #define PCI_PGCTL_LSRMD_MASK BIT(4) 29dd96dacaSLiam Girdwood 30dd96dacaSLiam Girdwood /* PCI_CGCTL bits */ 31dd96dacaSLiam Girdwood #define PCI_CGCTL_MISCBDCGE_MASK BIT(6) 32dd96dacaSLiam Girdwood #define PCI_CGCTL_ADSPDCGE BIT(1) 33dd96dacaSLiam Girdwood 34dd96dacaSLiam Girdwood /* Legacy HDA registers and bits used - widths are variable */ 35dd96dacaSLiam Girdwood #define SOF_HDA_GCAP 0x0 36dd96dacaSLiam Girdwood #define SOF_HDA_GCTL 0x8 37dd96dacaSLiam Girdwood /* accept unsol. response enable */ 38dd96dacaSLiam Girdwood #define SOF_HDA_GCTL_UNSOL BIT(8) 39dd96dacaSLiam Girdwood #define SOF_HDA_LLCH 0x14 40dd96dacaSLiam Girdwood #define SOF_HDA_INTCTL 0x20 41dd96dacaSLiam Girdwood #define SOF_HDA_INTSTS 0x24 42dd96dacaSLiam Girdwood #define SOF_HDA_WAKESTS 0x0E 43dd96dacaSLiam Girdwood #define SOF_HDA_WAKESTS_INT_MASK ((1 << 8) - 1) 44dd96dacaSLiam Girdwood #define SOF_HDA_RIRBSTS 0x5d 45dd96dacaSLiam Girdwood 46dd96dacaSLiam Girdwood /* SOF_HDA_GCTL register bist */ 47dd96dacaSLiam Girdwood #define SOF_HDA_GCTL_RESET BIT(0) 48dd96dacaSLiam Girdwood 497c11af9fSBard Liao /* SOF_HDA_INCTL regs */ 50dd96dacaSLiam Girdwood #define SOF_HDA_INT_GLOBAL_EN BIT(31) 51dd96dacaSLiam Girdwood #define SOF_HDA_INT_CTRL_EN BIT(30) 52dd96dacaSLiam Girdwood #define SOF_HDA_INT_ALL_STREAM 0xff 53dd96dacaSLiam Girdwood 547c11af9fSBard Liao /* SOF_HDA_INTSTS regs */ 557c11af9fSBard Liao #define SOF_HDA_INTSTS_GIS BIT(31) 567c11af9fSBard Liao 57dd96dacaSLiam Girdwood #define SOF_HDA_MAX_CAPS 10 58dd96dacaSLiam Girdwood #define SOF_HDA_CAP_ID_OFF 16 59dd96dacaSLiam Girdwood #define SOF_HDA_CAP_ID_MASK GENMASK(SOF_HDA_CAP_ID_OFF + 11,\ 60dd96dacaSLiam Girdwood SOF_HDA_CAP_ID_OFF) 61dd96dacaSLiam Girdwood #define SOF_HDA_CAP_NEXT_MASK 0xFFFF 62dd96dacaSLiam Girdwood 63dd96dacaSLiam Girdwood #define SOF_HDA_GTS_CAP_ID 0x1 64dd96dacaSLiam Girdwood #define SOF_HDA_ML_CAP_ID 0x2 65dd96dacaSLiam Girdwood 66dd96dacaSLiam Girdwood #define SOF_HDA_PP_CAP_ID 0x3 67dd96dacaSLiam Girdwood #define SOF_HDA_REG_PP_PPCH 0x10 68dd96dacaSLiam Girdwood #define SOF_HDA_REG_PP_PPCTL 0x04 69f1fd9d0eSKai Vehmanen #define SOF_HDA_REG_PP_PPSTS 0x08 70dd96dacaSLiam Girdwood #define SOF_HDA_PPCTL_PIE BIT(31) 71dd96dacaSLiam Girdwood #define SOF_HDA_PPCTL_GPROCEN BIT(30) 72dd96dacaSLiam Girdwood 7362f8f766SKeyon Jie /*Vendor Specific Registers*/ 7462f8f766SKeyon Jie #define SOF_HDA_VS_D0I3C 0x104A 7562f8f766SKeyon Jie 7662f8f766SKeyon Jie /* D0I3C Register fields */ 7762f8f766SKeyon Jie #define SOF_HDA_VS_D0I3C_CIP BIT(0) /* Command-In-Progress */ 7862f8f766SKeyon Jie #define SOF_HDA_VS_D0I3C_I3 BIT(2) /* D0i3 enable bit */ 7962f8f766SKeyon Jie 80dd96dacaSLiam Girdwood /* DPIB entry size: 8 Bytes = 2 DWords */ 81dd96dacaSLiam Girdwood #define SOF_HDA_DPIB_ENTRY_SIZE 0x8 82dd96dacaSLiam Girdwood 83dd96dacaSLiam Girdwood #define SOF_HDA_SPIB_CAP_ID 0x4 84dd96dacaSLiam Girdwood #define SOF_HDA_DRSM_CAP_ID 0x5 85dd96dacaSLiam Girdwood 86dd96dacaSLiam Girdwood #define SOF_HDA_SPIB_BASE 0x08 87dd96dacaSLiam Girdwood #define SOF_HDA_SPIB_INTERVAL 0x08 88dd96dacaSLiam Girdwood #define SOF_HDA_SPIB_SPIB 0x00 89dd96dacaSLiam Girdwood #define SOF_HDA_SPIB_MAXFIFO 0x04 90dd96dacaSLiam Girdwood 91dd96dacaSLiam Girdwood #define SOF_HDA_PPHC_BASE 0x10 92dd96dacaSLiam Girdwood #define SOF_HDA_PPHC_INTERVAL 0x10 93dd96dacaSLiam Girdwood 94dd96dacaSLiam Girdwood #define SOF_HDA_PPLC_BASE 0x10 95dd96dacaSLiam Girdwood #define SOF_HDA_PPLC_MULTI 0x10 96dd96dacaSLiam Girdwood #define SOF_HDA_PPLC_INTERVAL 0x10 97dd96dacaSLiam Girdwood 98dd96dacaSLiam Girdwood #define SOF_HDA_DRSM_BASE 0x08 99dd96dacaSLiam Girdwood #define SOF_HDA_DRSM_INTERVAL 0x08 100dd96dacaSLiam Girdwood 101dd96dacaSLiam Girdwood /* Descriptor error interrupt */ 102dd96dacaSLiam Girdwood #define SOF_HDA_CL_DMA_SD_INT_DESC_ERR 0x10 103dd96dacaSLiam Girdwood 104dd96dacaSLiam Girdwood /* FIFO error interrupt */ 105dd96dacaSLiam Girdwood #define SOF_HDA_CL_DMA_SD_INT_FIFO_ERR 0x08 106dd96dacaSLiam Girdwood 107dd96dacaSLiam Girdwood /* Buffer completion interrupt */ 108dd96dacaSLiam Girdwood #define SOF_HDA_CL_DMA_SD_INT_COMPLETE 0x04 109dd96dacaSLiam Girdwood 110dd96dacaSLiam Girdwood #define SOF_HDA_CL_DMA_SD_INT_MASK \ 111dd96dacaSLiam Girdwood (SOF_HDA_CL_DMA_SD_INT_DESC_ERR | \ 112dd96dacaSLiam Girdwood SOF_HDA_CL_DMA_SD_INT_FIFO_ERR | \ 113dd96dacaSLiam Girdwood SOF_HDA_CL_DMA_SD_INT_COMPLETE) 114dd96dacaSLiam Girdwood #define SOF_HDA_SD_CTL_DMA_START 0x02 /* Stream DMA start bit */ 115dd96dacaSLiam Girdwood 116dd96dacaSLiam Girdwood /* Intel HD Audio Code Loader DMA Registers */ 117dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_LOADER_BASE 0x80 118dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_DPLBASE 0x70 119dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_DPUBASE 0x74 120dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_DPLBASE_ENABLE 0x01 121dd96dacaSLiam Girdwood 122dd96dacaSLiam Girdwood /* Stream Registers */ 123dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SD_CTL 0x00 124dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SD_STS 0x03 125dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SD_LPIB 0x04 126dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SD_CBL 0x08 127dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SD_LVI 0x0C 128dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SD_FIFOW 0x0E 129dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SD_FIFOSIZE 0x10 130dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SD_FORMAT 0x12 131dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SD_FIFOL 0x14 132dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SD_BDLPL 0x18 133dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SD_BDLPU 0x1C 134dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_SD_ENTRY_SIZE 0x20 135dd96dacaSLiam Girdwood 136dd96dacaSLiam Girdwood /* CL: Software Position Based FIFO Capability Registers */ 137dd96dacaSLiam Girdwood #define SOF_DSP_REG_CL_SPBFIFO \ 138dd96dacaSLiam Girdwood (SOF_HDA_ADSP_LOADER_BASE + 0x20) 139dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCH 0x0 140dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCCTL 0x4 141dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPIB 0x8 142dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SPBFIFO_MAXFIFOS 0xc 143dd96dacaSLiam Girdwood 144dd96dacaSLiam Girdwood /* Stream Number */ 145dd96dacaSLiam Girdwood #define SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT 20 146dd96dacaSLiam Girdwood #define SOF_HDA_CL_SD_CTL_STREAM_TAG_MASK \ 147dd96dacaSLiam Girdwood GENMASK(SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT + 3,\ 148dd96dacaSLiam Girdwood SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT) 149dd96dacaSLiam Girdwood 150dd96dacaSLiam Girdwood #define HDA_DSP_HDA_BAR 0 151dd96dacaSLiam Girdwood #define HDA_DSP_PP_BAR 1 152dd96dacaSLiam Girdwood #define HDA_DSP_SPIB_BAR 2 153dd96dacaSLiam Girdwood #define HDA_DSP_DRSM_BAR 3 154dd96dacaSLiam Girdwood #define HDA_DSP_BAR 4 155dd96dacaSLiam Girdwood 156dd96dacaSLiam Girdwood #define SRAM_WINDOW_OFFSET(x) (0x80000 + (x) * 0x20000) 157dd96dacaSLiam Girdwood 158dd96dacaSLiam Girdwood #define HDA_DSP_MBOX_OFFSET SRAM_WINDOW_OFFSET(0) 159dd96dacaSLiam Girdwood 160dd96dacaSLiam Girdwood #define HDA_DSP_PANIC_OFFSET(x) \ 161dd96dacaSLiam Girdwood (((x) & 0xFFFFFF) + HDA_DSP_MBOX_OFFSET) 162dd96dacaSLiam Girdwood 163dd96dacaSLiam Girdwood /* SRAM window 0 FW "registers" */ 164dd96dacaSLiam Girdwood #define HDA_DSP_SRAM_REG_ROM_STATUS (HDA_DSP_MBOX_OFFSET + 0x0) 165dd96dacaSLiam Girdwood #define HDA_DSP_SRAM_REG_ROM_ERROR (HDA_DSP_MBOX_OFFSET + 0x4) 166dd96dacaSLiam Girdwood /* FW and ROM share offset 4 */ 167dd96dacaSLiam Girdwood #define HDA_DSP_SRAM_REG_FW_STATUS (HDA_DSP_MBOX_OFFSET + 0x4) 168dd96dacaSLiam Girdwood #define HDA_DSP_SRAM_REG_FW_TRACEP (HDA_DSP_MBOX_OFFSET + 0x8) 169dd96dacaSLiam Girdwood #define HDA_DSP_SRAM_REG_FW_END (HDA_DSP_MBOX_OFFSET + 0xc) 170dd96dacaSLiam Girdwood 171dd96dacaSLiam Girdwood #define HDA_DSP_MBOX_UPLINK_OFFSET 0x81000 172dd96dacaSLiam Girdwood 173dd96dacaSLiam Girdwood #define HDA_DSP_STREAM_RESET_TIMEOUT 300 1747bcaf0f2SZhu Yingjiang /* 1757bcaf0f2SZhu Yingjiang * Timeout in us, for setting the stream RUN bit, during 1767bcaf0f2SZhu Yingjiang * start/stop the stream. The timeout expires if new RUN bit 1777bcaf0f2SZhu Yingjiang * value cannot be read back within the specified time. 1787bcaf0f2SZhu Yingjiang */ 1797bcaf0f2SZhu Yingjiang #define HDA_DSP_STREAM_RUN_TIMEOUT 300 180dd96dacaSLiam Girdwood 181dd96dacaSLiam Girdwood #define HDA_DSP_SPIB_ENABLE 1 182dd96dacaSLiam Girdwood #define HDA_DSP_SPIB_DISABLE 0 183dd96dacaSLiam Girdwood 184dd96dacaSLiam Girdwood #define SOF_HDA_MAX_BUFFER_SIZE (32 * PAGE_SIZE) 185dd96dacaSLiam Girdwood 186dd96dacaSLiam Girdwood #define HDA_DSP_STACK_DUMP_SIZE 32 187dd96dacaSLiam Girdwood 188dd96dacaSLiam Girdwood /* ROM status/error values */ 189184fdfcaSKeyon Jie #define HDA_DSP_ROM_STS_MASK GENMASK(23, 0) 190dd96dacaSLiam Girdwood #define HDA_DSP_ROM_INIT 0x1 191dd96dacaSLiam Girdwood #define HDA_DSP_ROM_FW_MANIFEST_LOADED 0x3 192dd96dacaSLiam Girdwood #define HDA_DSP_ROM_FW_FW_LOADED 0x4 193dd96dacaSLiam Girdwood #define HDA_DSP_ROM_FW_ENTERED 0x5 194dd96dacaSLiam Girdwood #define HDA_DSP_ROM_RFW_START 0xf 195dd96dacaSLiam Girdwood #define HDA_DSP_ROM_CSE_ERROR 40 196dd96dacaSLiam Girdwood #define HDA_DSP_ROM_CSE_WRONG_RESPONSE 41 197dd96dacaSLiam Girdwood #define HDA_DSP_ROM_IMR_TO_SMALL 42 198dd96dacaSLiam Girdwood #define HDA_DSP_ROM_BASE_FW_NOT_FOUND 43 199dd96dacaSLiam Girdwood #define HDA_DSP_ROM_CSE_VALIDATION_FAILED 44 200dd96dacaSLiam Girdwood #define HDA_DSP_ROM_IPC_FATAL_ERROR 45 201dd96dacaSLiam Girdwood #define HDA_DSP_ROM_L2_CACHE_ERROR 46 202dd96dacaSLiam Girdwood #define HDA_DSP_ROM_LOAD_OFFSET_TO_SMALL 47 203dd96dacaSLiam Girdwood #define HDA_DSP_ROM_API_PTR_INVALID 50 204dd96dacaSLiam Girdwood #define HDA_DSP_ROM_BASEFW_INCOMPAT 51 205dd96dacaSLiam Girdwood #define HDA_DSP_ROM_UNHANDLED_INTERRUPT 0xBEE00000 206dd96dacaSLiam Girdwood #define HDA_DSP_ROM_MEMORY_HOLE_ECC 0xECC00000 207dd96dacaSLiam Girdwood #define HDA_DSP_ROM_KERNEL_EXCEPTION 0xCAFE0000 208dd96dacaSLiam Girdwood #define HDA_DSP_ROM_USER_EXCEPTION 0xBEEF0000 209dd96dacaSLiam Girdwood #define HDA_DSP_ROM_UNEXPECTED_RESET 0xDECAF000 210dd96dacaSLiam Girdwood #define HDA_DSP_ROM_NULL_FW_ENTRY 0x4c4c4e55 211dd96dacaSLiam Girdwood #define HDA_DSP_IPC_PURGE_FW 0x01004000 212dd96dacaSLiam Girdwood 213dd96dacaSLiam Girdwood /* various timeout values */ 214dd96dacaSLiam Girdwood #define HDA_DSP_PU_TIMEOUT 50 215dd96dacaSLiam Girdwood #define HDA_DSP_PD_TIMEOUT 50 216dd96dacaSLiam Girdwood #define HDA_DSP_RESET_TIMEOUT_US 50000 217dd96dacaSLiam Girdwood #define HDA_DSP_BASEFW_TIMEOUT_US 3000000 218dd96dacaSLiam Girdwood #define HDA_DSP_INIT_TIMEOUT_US 500000 219dd96dacaSLiam Girdwood #define HDA_DSP_CTRL_RESET_TIMEOUT 100 220dd96dacaSLiam Girdwood #define HDA_DSP_WAIT_TIMEOUT 500 /* 500 msec */ 221dd96dacaSLiam Girdwood #define HDA_DSP_REG_POLL_INTERVAL_US 500 /* 0.5 msec */ 22292f4beb7SKeyon Jie #define HDA_DSP_REG_POLL_RETRY_COUNT 50 223dd96dacaSLiam Girdwood 224dd96dacaSLiam Girdwood #define HDA_DSP_ADSPIC_IPC 1 225dd96dacaSLiam Girdwood #define HDA_DSP_ADSPIS_IPC 1 226dd96dacaSLiam Girdwood 227dd96dacaSLiam Girdwood /* Intel HD Audio General DSP Registers */ 228dd96dacaSLiam Girdwood #define HDA_DSP_GEN_BASE 0x0 229dd96dacaSLiam Girdwood #define HDA_DSP_REG_ADSPCS (HDA_DSP_GEN_BASE + 0x04) 230dd96dacaSLiam Girdwood #define HDA_DSP_REG_ADSPIC (HDA_DSP_GEN_BASE + 0x08) 231dd96dacaSLiam Girdwood #define HDA_DSP_REG_ADSPIS (HDA_DSP_GEN_BASE + 0x0C) 232dd96dacaSLiam Girdwood #define HDA_DSP_REG_ADSPIC2 (HDA_DSP_GEN_BASE + 0x10) 233dd96dacaSLiam Girdwood #define HDA_DSP_REG_ADSPIS2 (HDA_DSP_GEN_BASE + 0x14) 234dd96dacaSLiam Girdwood 235722ba5f1SBard Liao #define HDA_DSP_REG_ADSPIS2_SNDW BIT(5) 236722ba5f1SBard Liao 237dd96dacaSLiam Girdwood /* Intel HD Audio Inter-Processor Communication Registers */ 238dd96dacaSLiam Girdwood #define HDA_DSP_IPC_BASE 0x40 239dd96dacaSLiam Girdwood #define HDA_DSP_REG_HIPCT (HDA_DSP_IPC_BASE + 0x00) 240dd96dacaSLiam Girdwood #define HDA_DSP_REG_HIPCTE (HDA_DSP_IPC_BASE + 0x04) 241dd96dacaSLiam Girdwood #define HDA_DSP_REG_HIPCI (HDA_DSP_IPC_BASE + 0x08) 242dd96dacaSLiam Girdwood #define HDA_DSP_REG_HIPCIE (HDA_DSP_IPC_BASE + 0x0C) 243dd96dacaSLiam Girdwood #define HDA_DSP_REG_HIPCCTL (HDA_DSP_IPC_BASE + 0x10) 244dd96dacaSLiam Girdwood 24543b2ab90SRanjani Sridharan /* Intel Vendor Specific Registers */ 24643b2ab90SRanjani Sridharan #define HDA_VS_INTEL_EM2 0x1030 24743b2ab90SRanjani Sridharan #define HDA_VS_INTEL_EM2_L1SEN BIT(13) 248aca961f1SRanjani Sridharan #define HDA_VS_INTEL_LTRP_GB_MASK 0x3F 24943b2ab90SRanjani Sridharan 250dd96dacaSLiam Girdwood /* HIPCI */ 251dd96dacaSLiam Girdwood #define HDA_DSP_REG_HIPCI_BUSY BIT(31) 252dd96dacaSLiam Girdwood #define HDA_DSP_REG_HIPCI_MSG_MASK 0x7FFFFFFF 253dd96dacaSLiam Girdwood 254dd96dacaSLiam Girdwood /* HIPCIE */ 255dd96dacaSLiam Girdwood #define HDA_DSP_REG_HIPCIE_DONE BIT(30) 256dd96dacaSLiam Girdwood #define HDA_DSP_REG_HIPCIE_MSG_MASK 0x3FFFFFFF 257dd96dacaSLiam Girdwood 258dd96dacaSLiam Girdwood /* HIPCCTL */ 259dd96dacaSLiam Girdwood #define HDA_DSP_REG_HIPCCTL_DONE BIT(1) 260dd96dacaSLiam Girdwood #define HDA_DSP_REG_HIPCCTL_BUSY BIT(0) 261dd96dacaSLiam Girdwood 262dd96dacaSLiam Girdwood /* HIPCT */ 263dd96dacaSLiam Girdwood #define HDA_DSP_REG_HIPCT_BUSY BIT(31) 264dd96dacaSLiam Girdwood #define HDA_DSP_REG_HIPCT_MSG_MASK 0x7FFFFFFF 265dd96dacaSLiam Girdwood 266dd96dacaSLiam Girdwood /* HIPCTE */ 267dd96dacaSLiam Girdwood #define HDA_DSP_REG_HIPCTE_MSG_MASK 0x3FFFFFFF 268dd96dacaSLiam Girdwood 269dd96dacaSLiam Girdwood #define HDA_DSP_ADSPIC_CL_DMA 0x2 270dd96dacaSLiam Girdwood #define HDA_DSP_ADSPIS_CL_DMA 0x2 271dd96dacaSLiam Girdwood 272dd96dacaSLiam Girdwood /* Delay before scheduling D0i3 entry */ 273dd96dacaSLiam Girdwood #define BXT_D0I3_DELAY 5000 274dd96dacaSLiam Girdwood 275dd96dacaSLiam Girdwood #define FW_CL_STREAM_NUMBER 0x1 276776100a4SPierre-Louis Bossart #define HDA_FW_BOOT_ATTEMPTS 3 277dd96dacaSLiam Girdwood 278dd96dacaSLiam Girdwood /* ADSPCS - Audio DSP Control & Status */ 279dd96dacaSLiam Girdwood 280dd96dacaSLiam Girdwood /* 281dd96dacaSLiam Girdwood * Core Reset - asserted high 282dd96dacaSLiam Girdwood * CRST Mask for a given core mask pattern, cm 283dd96dacaSLiam Girdwood */ 284dd96dacaSLiam Girdwood #define HDA_DSP_ADSPCS_CRST_SHIFT 0 285dd96dacaSLiam Girdwood #define HDA_DSP_ADSPCS_CRST_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CRST_SHIFT) 286dd96dacaSLiam Girdwood 287dd96dacaSLiam Girdwood /* 288dd96dacaSLiam Girdwood * Core run/stall - when set to '1' core is stalled 289dd96dacaSLiam Girdwood * CSTALL Mask for a given core mask pattern, cm 290dd96dacaSLiam Girdwood */ 291dd96dacaSLiam Girdwood #define HDA_DSP_ADSPCS_CSTALL_SHIFT 8 292dd96dacaSLiam Girdwood #define HDA_DSP_ADSPCS_CSTALL_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CSTALL_SHIFT) 293dd96dacaSLiam Girdwood 294dd96dacaSLiam Girdwood /* 295dd96dacaSLiam Girdwood * Set Power Active - when set to '1' turn cores on 296dd96dacaSLiam Girdwood * SPA Mask for a given core mask pattern, cm 297dd96dacaSLiam Girdwood */ 298dd96dacaSLiam Girdwood #define HDA_DSP_ADSPCS_SPA_SHIFT 16 299dd96dacaSLiam Girdwood #define HDA_DSP_ADSPCS_SPA_MASK(cm) ((cm) << HDA_DSP_ADSPCS_SPA_SHIFT) 300dd96dacaSLiam Girdwood 301dd96dacaSLiam Girdwood /* 302dd96dacaSLiam Girdwood * Current Power Active - power status of cores, set by hardware 303dd96dacaSLiam Girdwood * CPA Mask for a given core mask pattern, cm 304dd96dacaSLiam Girdwood */ 305dd96dacaSLiam Girdwood #define HDA_DSP_ADSPCS_CPA_SHIFT 24 306dd96dacaSLiam Girdwood #define HDA_DSP_ADSPCS_CPA_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CPA_SHIFT) 307dd96dacaSLiam Girdwood 308dd96dacaSLiam Girdwood /* 309dd96dacaSLiam Girdwood * Mask for a given number of cores 310dd96dacaSLiam Girdwood * nc = number of supported cores 311dd96dacaSLiam Girdwood */ 312dd96dacaSLiam Girdwood #define SOF_DSP_CORES_MASK(nc) GENMASK(((nc) - 1), 0) 313dd96dacaSLiam Girdwood 314dd96dacaSLiam Girdwood /* Intel HD Audio Inter-Processor Communication Registers for Cannonlake*/ 315dd96dacaSLiam Girdwood #define CNL_DSP_IPC_BASE 0xc0 316dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCTDR (CNL_DSP_IPC_BASE + 0x00) 317dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCTDA (CNL_DSP_IPC_BASE + 0x04) 318dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCTDD (CNL_DSP_IPC_BASE + 0x08) 319dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCIDR (CNL_DSP_IPC_BASE + 0x10) 320dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCIDA (CNL_DSP_IPC_BASE + 0x14) 3210267de58SKeyon Jie #define CNL_DSP_REG_HIPCIDD (CNL_DSP_IPC_BASE + 0x18) 322dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCCTL (CNL_DSP_IPC_BASE + 0x28) 323dd96dacaSLiam Girdwood 324dd96dacaSLiam Girdwood /* HIPCI */ 325dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCIDR_BUSY BIT(31) 326dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCIDR_MSG_MASK 0x7FFFFFFF 327dd96dacaSLiam Girdwood 328dd96dacaSLiam Girdwood /* HIPCIE */ 329dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCIDA_DONE BIT(31) 330dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCIDA_MSG_MASK 0x7FFFFFFF 331dd96dacaSLiam Girdwood 332dd96dacaSLiam Girdwood /* HIPCCTL */ 333dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCCTL_DONE BIT(1) 334dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCCTL_BUSY BIT(0) 335dd96dacaSLiam Girdwood 336dd96dacaSLiam Girdwood /* HIPCT */ 337dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCTDR_BUSY BIT(31) 338dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCTDR_MSG_MASK 0x7FFFFFFF 339dd96dacaSLiam Girdwood 340dd96dacaSLiam Girdwood /* HIPCTDA */ 341dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCTDA_DONE BIT(31) 342dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCTDA_MSG_MASK 0x7FFFFFFF 343dd96dacaSLiam Girdwood 344dd96dacaSLiam Girdwood /* HIPCTDD */ 345dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCTDD_MSG_MASK 0x7FFFFFFF 346dd96dacaSLiam Girdwood 347dd96dacaSLiam Girdwood /* BDL */ 348dd96dacaSLiam Girdwood #define HDA_DSP_BDL_SIZE 4096 349dd96dacaSLiam Girdwood #define HDA_DSP_MAX_BDL_ENTRIES \ 350dd96dacaSLiam Girdwood (HDA_DSP_BDL_SIZE / sizeof(struct sof_intel_dsp_bdl)) 351dd96dacaSLiam Girdwood 352dd96dacaSLiam Girdwood /* Number of DAIs */ 353dd96dacaSLiam Girdwood #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) 35470368106SCezary Rojewski 35570368106SCezary Rojewski #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_PROBES) 35670368106SCezary Rojewski #define SOF_SKL_NUM_DAIS 16 35770368106SCezary Rojewski #else 358a6947c9dSCezary Rojewski #define SOF_SKL_NUM_DAIS 15 35970368106SCezary Rojewski #endif 36070368106SCezary Rojewski 361dd96dacaSLiam Girdwood #else 362dd96dacaSLiam Girdwood #define SOF_SKL_NUM_DAIS 8 363dd96dacaSLiam Girdwood #endif 364dd96dacaSLiam Girdwood 365dd96dacaSLiam Girdwood /* Intel HD Audio SRAM Window 0*/ 366dd96dacaSLiam Girdwood #define HDA_ADSP_SRAM0_BASE_SKL 0x8000 367dd96dacaSLiam Girdwood 368dd96dacaSLiam Girdwood /* Firmware status window */ 369dd96dacaSLiam Girdwood #define HDA_ADSP_FW_STATUS_SKL HDA_ADSP_SRAM0_BASE_SKL 370dd96dacaSLiam Girdwood #define HDA_ADSP_ERROR_CODE_SKL (HDA_ADSP_FW_STATUS_SKL + 0x4) 371dd96dacaSLiam Girdwood 372df7e0de5SZhu Yingjiang /* Host Device Memory Space */ 373df7e0de5SZhu Yingjiang #define APL_SSP_BASE_OFFSET 0x2000 374df7e0de5SZhu Yingjiang #define CNL_SSP_BASE_OFFSET 0x10000 375df7e0de5SZhu Yingjiang 376df7e0de5SZhu Yingjiang /* Host Device Memory Size of a Single SSP */ 377df7e0de5SZhu Yingjiang #define SSP_DEV_MEM_SIZE 0x1000 378df7e0de5SZhu Yingjiang 379b095fe47SZhu Yingjiang /* SSP Count of the Platform */ 380b095fe47SZhu Yingjiang #define APL_SSP_COUNT 6 381b095fe47SZhu Yingjiang #define CNL_SSP_COUNT 3 382ec836daaSZhu Yingjiang #define ICL_SSP_COUNT 6 383b095fe47SZhu Yingjiang 38474ed4097SZhu Yingjiang /* SSP Registers */ 38574ed4097SZhu Yingjiang #define SSP_SSC1_OFFSET 0x4 386bd586a02SPierre-Louis Bossart #define SSP_SET_SCLK_CONSUMER BIT(25) 387bd586a02SPierre-Louis Bossart #define SSP_SET_SFRM_CONSUMER BIT(24) 388bd586a02SPierre-Louis Bossart #define SSP_SET_CBP_CFP (SSP_SET_SCLK_CONSUMER | SSP_SET_SFRM_CONSUMER) 38974ed4097SZhu Yingjiang 390c99fafdfSKai Vehmanen #define HDA_IDISP_ADDR 2 391c99fafdfSKai Vehmanen #define HDA_IDISP_CODEC(x) ((x) & BIT(HDA_IDISP_ADDR)) 392dd96dacaSLiam Girdwood 393dd96dacaSLiam Girdwood struct sof_intel_dsp_bdl { 394dd96dacaSLiam Girdwood __le32 addr_l; 395dd96dacaSLiam Girdwood __le32 addr_h; 396dd96dacaSLiam Girdwood __le32 size; 397dd96dacaSLiam Girdwood __le32 ioc; 398dd96dacaSLiam Girdwood } __attribute((packed)); 399dd96dacaSLiam Girdwood 400dd96dacaSLiam Girdwood #define SOF_HDA_PLAYBACK_STREAMS 16 401dd96dacaSLiam Girdwood #define SOF_HDA_CAPTURE_STREAMS 16 402dd96dacaSLiam Girdwood #define SOF_HDA_PLAYBACK 0 403dd96dacaSLiam Girdwood #define SOF_HDA_CAPTURE 1 404dd96dacaSLiam Girdwood 40589a400bdSRanjani Sridharan /* stream flags */ 40689a400bdSRanjani Sridharan #define SOF_HDA_STREAM_DMI_L1_COMPATIBLE 1 40789a400bdSRanjani Sridharan 40863e51fd3SRanjani Sridharan /* 40963e51fd3SRanjani Sridharan * Time in ms for opportunistic D0I3 entry delay. 41063e51fd3SRanjani Sridharan * This has been deliberately chosen to be long to avoid race conditions. 41163e51fd3SRanjani Sridharan * Could be optimized in future. 41263e51fd3SRanjani Sridharan */ 41363e51fd3SRanjani Sridharan #define SOF_HDA_D0I3_WORK_DELAY_MS 5000 41463e51fd3SRanjani Sridharan 41561e285caSRanjani Sridharan /* HDA DSP D0 substate */ 41661e285caSRanjani Sridharan enum sof_hda_D0_substate { 41761e285caSRanjani Sridharan SOF_HDA_DSP_PM_D0I0, /* default D0 substate */ 41861e285caSRanjani Sridharan SOF_HDA_DSP_PM_D0I3, /* low power D0 substate */ 41961e285caSRanjani Sridharan }; 42061e285caSRanjani Sridharan 421dd96dacaSLiam Girdwood /* represents DSP HDA controller frontend - i.e. host facing control */ 422dd96dacaSLiam Girdwood struct sof_intel_hda_dev { 423776100a4SPierre-Louis Bossart int boot_iteration; 424dd96dacaSLiam Girdwood 425dd96dacaSLiam Girdwood struct hda_bus hbus; 426dd96dacaSLiam Girdwood 427dd96dacaSLiam Girdwood /* hw config */ 428dd96dacaSLiam Girdwood const struct sof_intel_dsp_desc *desc; 429dd96dacaSLiam Girdwood 430dd96dacaSLiam Girdwood /* trace */ 431dd96dacaSLiam Girdwood struct hdac_ext_stream *dtrace_stream; 432dd96dacaSLiam Girdwood 433dd96dacaSLiam Girdwood /* if position update IPC needed */ 434dd96dacaSLiam Girdwood u32 no_ipc_position; 435dd96dacaSLiam Girdwood 436e8e55dbeSKeyon Jie /* the maximum number of streams (playback + capture) supported */ 437e8e55dbeSKeyon Jie u32 stream_max; 438e8e55dbeSKeyon Jie 43916299326SKeyon Jie /* PM related */ 44016299326SKeyon Jie bool l1_support_changed;/* during suspend, is L1SEN changed or not */ 44116299326SKeyon Jie 442dd96dacaSLiam Girdwood /* DMIC device */ 443dd96dacaSLiam Girdwood struct platform_device *dmic_dev; 44463e51fd3SRanjani Sridharan 44563e51fd3SRanjani Sridharan /* delayed work to enter D0I3 opportunistically */ 44663e51fd3SRanjani Sridharan struct delayed_work d0i3_work; 44751dfed1eSPierre-Louis Bossart 44851dfed1eSPierre-Louis Bossart /* ACPI information stored between scan and probe steps */ 44951dfed1eSPierre-Louis Bossart struct sdw_intel_acpi_info info; 45051dfed1eSPierre-Louis Bossart 45151dfed1eSPierre-Louis Bossart /* sdw context allocated by SoundWire driver */ 45251dfed1eSPierre-Louis Bossart struct sdw_intel_ctx *sdw; 453edbaaadaSFred Oh 454edbaaadaSFred Oh /* FW clock config, 0:HPRO, 1:LPRO */ 455edbaaadaSFred Oh bool clk_config_lpro; 456dd96dacaSLiam Girdwood }; 457dd96dacaSLiam Girdwood 458dd96dacaSLiam Girdwood static inline struct hdac_bus *sof_to_bus(struct snd_sof_dev *s) 459dd96dacaSLiam Girdwood { 460dd96dacaSLiam Girdwood struct sof_intel_hda_dev *hda = s->pdata->hw_pdata; 461dd96dacaSLiam Girdwood 462dd96dacaSLiam Girdwood return &hda->hbus.core; 463dd96dacaSLiam Girdwood } 464dd96dacaSLiam Girdwood 465dd96dacaSLiam Girdwood static inline struct hda_bus *sof_to_hbus(struct snd_sof_dev *s) 466dd96dacaSLiam Girdwood { 467dd96dacaSLiam Girdwood struct sof_intel_hda_dev *hda = s->pdata->hw_pdata; 468dd96dacaSLiam Girdwood 469dd96dacaSLiam Girdwood return &hda->hbus; 470dd96dacaSLiam Girdwood } 471dd96dacaSLiam Girdwood 472dd96dacaSLiam Girdwood struct sof_intel_hda_stream { 4737623ae79SRanjani Sridharan struct snd_sof_dev *sdev; 474dd96dacaSLiam Girdwood struct hdac_ext_stream hda_stream; 475dd96dacaSLiam Girdwood struct sof_intel_stream stream; 4766b2239e3SRanjani Sridharan int host_reserved; /* reserve host DMA channel */ 47789a400bdSRanjani Sridharan u32 flags; 478dd96dacaSLiam Girdwood }; 479dd96dacaSLiam Girdwood 480f5dbba9fSRanjani Sridharan #define hstream_to_sof_hda_stream(hstream) \ 481f5dbba9fSRanjani Sridharan container_of(hstream, struct sof_intel_hda_stream, hda_stream) 482f5dbba9fSRanjani Sridharan 483dd96dacaSLiam Girdwood #define bus_to_sof_hda(bus) \ 484dd96dacaSLiam Girdwood container_of(bus, struct sof_intel_hda_dev, hbus.core) 485dd96dacaSLiam Girdwood 486dd96dacaSLiam Girdwood #define SOF_STREAM_SD_OFFSET(s) \ 487dd96dacaSLiam Girdwood (SOF_HDA_ADSP_SD_ENTRY_SIZE * ((s)->index) \ 488dd96dacaSLiam Girdwood + SOF_HDA_ADSP_LOADER_BASE) 489dd96dacaSLiam Girdwood 4902b1acedcSRanjani Sridharan #define SOF_STREAM_SD_OFFSET_CRST 0x1 4912b1acedcSRanjani Sridharan 492dd96dacaSLiam Girdwood /* 493dd96dacaSLiam Girdwood * DSP Core services. 494dd96dacaSLiam Girdwood */ 495dd96dacaSLiam Girdwood int hda_dsp_probe(struct snd_sof_dev *sdev); 496dd96dacaSLiam Girdwood int hda_dsp_remove(struct snd_sof_dev *sdev); 497dd96dacaSLiam Girdwood int hda_dsp_core_run(struct snd_sof_dev *sdev, unsigned int core_mask); 498dd96dacaSLiam Girdwood int hda_dsp_enable_core(struct snd_sof_dev *sdev, unsigned int core_mask); 499dd96dacaSLiam Girdwood int hda_dsp_core_reset_power_down(struct snd_sof_dev *sdev, 500dd96dacaSLiam Girdwood unsigned int core_mask); 5019cdcbc9fSRanjani Sridharan int hda_dsp_core_get(struct snd_sof_dev *sdev, int core); 502dd96dacaSLiam Girdwood void hda_dsp_ipc_int_enable(struct snd_sof_dev *sdev); 503dd96dacaSLiam Girdwood void hda_dsp_ipc_int_disable(struct snd_sof_dev *sdev); 504dd96dacaSLiam Girdwood 50562f8f766SKeyon Jie int hda_dsp_set_power_state(struct snd_sof_dev *sdev, 50661e285caSRanjani Sridharan const struct sof_dsp_power_state *target_state); 50762f8f766SKeyon Jie 50861e285caSRanjani Sridharan int hda_dsp_suspend(struct snd_sof_dev *sdev, u32 target_state); 509dd96dacaSLiam Girdwood int hda_dsp_resume(struct snd_sof_dev *sdev); 5101c38c922SFred Oh int hda_dsp_runtime_suspend(struct snd_sof_dev *sdev); 511dd96dacaSLiam Girdwood int hda_dsp_runtime_resume(struct snd_sof_dev *sdev); 51262fde977SKai Vehmanen int hda_dsp_runtime_idle(struct snd_sof_dev *sdev); 51322aa9e02SLibin Yang int hda_dsp_shutdown(struct snd_sof_dev *sdev); 5147077a07aSRanjani Sridharan int hda_dsp_set_hw_params_upon_resume(struct snd_sof_dev *sdev); 515dd96dacaSLiam Girdwood void hda_dsp_dump(struct snd_sof_dev *sdev, u32 flags); 516f3da49f0SPan Xiuli void hda_ipc_dump(struct snd_sof_dev *sdev); 517f1fd9d0eSKai Vehmanen void hda_ipc_irq_dump(struct snd_sof_dev *sdev); 51863e51fd3SRanjani Sridharan void hda_dsp_d0i3_work(struct work_struct *work); 519dd96dacaSLiam Girdwood 520dd96dacaSLiam Girdwood /* 521dd96dacaSLiam Girdwood * DSP PCM Operations. 522dd96dacaSLiam Girdwood */ 52349d7948eSCezary Rojewski u32 hda_dsp_get_mult_div(struct snd_sof_dev *sdev, int rate); 52449d7948eSCezary Rojewski u32 hda_dsp_get_bits(struct snd_sof_dev *sdev, int sample_bits); 525dd96dacaSLiam Girdwood int hda_dsp_pcm_open(struct snd_sof_dev *sdev, 526dd96dacaSLiam Girdwood struct snd_pcm_substream *substream); 527dd96dacaSLiam Girdwood int hda_dsp_pcm_close(struct snd_sof_dev *sdev, 528dd96dacaSLiam Girdwood struct snd_pcm_substream *substream); 529dd96dacaSLiam Girdwood int hda_dsp_pcm_hw_params(struct snd_sof_dev *sdev, 530dd96dacaSLiam Girdwood struct snd_pcm_substream *substream, 531dd96dacaSLiam Girdwood struct snd_pcm_hw_params *params, 532dd96dacaSLiam Girdwood struct sof_ipc_stream_params *ipc_params); 53393146bc2SRanjani Sridharan int hda_dsp_stream_hw_free(struct snd_sof_dev *sdev, 53493146bc2SRanjani Sridharan struct snd_pcm_substream *substream); 535dd96dacaSLiam Girdwood int hda_dsp_pcm_trigger(struct snd_sof_dev *sdev, 536dd96dacaSLiam Girdwood struct snd_pcm_substream *substream, int cmd); 537dd96dacaSLiam Girdwood snd_pcm_uframes_t hda_dsp_pcm_pointer(struct snd_sof_dev *sdev, 538dd96dacaSLiam Girdwood struct snd_pcm_substream *substream); 5396c26b505SRanjani Sridharan int hda_dsp_pcm_ack(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream); 540dd96dacaSLiam Girdwood 541dd96dacaSLiam Girdwood /* 542dd96dacaSLiam Girdwood * DSP Stream Operations. 543dd96dacaSLiam Girdwood */ 544dd96dacaSLiam Girdwood 545dd96dacaSLiam Girdwood int hda_dsp_stream_init(struct snd_sof_dev *sdev); 546dd96dacaSLiam Girdwood void hda_dsp_stream_free(struct snd_sof_dev *sdev); 547dd96dacaSLiam Girdwood int hda_dsp_stream_hw_params(struct snd_sof_dev *sdev, 548dd96dacaSLiam Girdwood struct hdac_ext_stream *stream, 549dd96dacaSLiam Girdwood struct snd_dma_buffer *dmab, 550dd96dacaSLiam Girdwood struct snd_pcm_hw_params *params); 551aca961f1SRanjani Sridharan int hda_dsp_iccmax_stream_hw_params(struct snd_sof_dev *sdev, struct hdac_ext_stream *stream, 552aca961f1SRanjani Sridharan struct snd_dma_buffer *dmab, 553aca961f1SRanjani Sridharan struct snd_pcm_hw_params *params); 554dd96dacaSLiam Girdwood int hda_dsp_stream_trigger(struct snd_sof_dev *sdev, 555dd96dacaSLiam Girdwood struct hdac_ext_stream *stream, int cmd); 556dd96dacaSLiam Girdwood irqreturn_t hda_dsp_stream_threaded_handler(int irq, void *context); 557dd96dacaSLiam Girdwood int hda_dsp_stream_setup_bdl(struct snd_sof_dev *sdev, 558dd96dacaSLiam Girdwood struct snd_dma_buffer *dmab, 559dd96dacaSLiam Girdwood struct hdac_stream *stream); 5607c11af9fSBard Liao bool hda_dsp_check_ipc_irq(struct snd_sof_dev *sdev); 5617c11af9fSBard Liao bool hda_dsp_check_stream_irq(struct snd_sof_dev *sdev); 562dd96dacaSLiam Girdwood 563dd96dacaSLiam Girdwood struct hdac_ext_stream * 56489a400bdSRanjani Sridharan hda_dsp_stream_get(struct snd_sof_dev *sdev, int direction, u32 flags); 565dd96dacaSLiam Girdwood int hda_dsp_stream_put(struct snd_sof_dev *sdev, int direction, int stream_tag); 566dd96dacaSLiam Girdwood int hda_dsp_stream_spib_config(struct snd_sof_dev *sdev, 567dd96dacaSLiam Girdwood struct hdac_ext_stream *stream, 568dd96dacaSLiam Girdwood int enable, u32 size); 569dd96dacaSLiam Girdwood 5706a0ba071SGuennadi Liakhovetski int hda_ipc_msg_data(struct snd_sof_dev *sdev, 571dd96dacaSLiam Girdwood struct snd_pcm_substream *substream, 572dd96dacaSLiam Girdwood void *p, size_t sz); 573dd96dacaSLiam Girdwood int hda_ipc_pcm_params(struct snd_sof_dev *sdev, 574dd96dacaSLiam Girdwood struct snd_pcm_substream *substream, 575dd96dacaSLiam Girdwood const struct sof_ipc_pcm_params_reply *reply); 576dd96dacaSLiam Girdwood 5774c414da9SCezary Rojewski #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_PROBES) 5784c414da9SCezary Rojewski /* 5794c414da9SCezary Rojewski * Probe Compress Operations. 5804c414da9SCezary Rojewski */ 5814c414da9SCezary Rojewski int hda_probe_compr_assign(struct snd_sof_dev *sdev, 5824c414da9SCezary Rojewski struct snd_compr_stream *cstream, 5834c414da9SCezary Rojewski struct snd_soc_dai *dai); 5844c414da9SCezary Rojewski int hda_probe_compr_free(struct snd_sof_dev *sdev, 5854c414da9SCezary Rojewski struct snd_compr_stream *cstream, 5864c414da9SCezary Rojewski struct snd_soc_dai *dai); 5874c414da9SCezary Rojewski int hda_probe_compr_set_params(struct snd_sof_dev *sdev, 5884c414da9SCezary Rojewski struct snd_compr_stream *cstream, 5894c414da9SCezary Rojewski struct snd_compr_params *params, 5904c414da9SCezary Rojewski struct snd_soc_dai *dai); 5914c414da9SCezary Rojewski int hda_probe_compr_trigger(struct snd_sof_dev *sdev, 5924c414da9SCezary Rojewski struct snd_compr_stream *cstream, int cmd, 5934c414da9SCezary Rojewski struct snd_soc_dai *dai); 5944c414da9SCezary Rojewski int hda_probe_compr_pointer(struct snd_sof_dev *sdev, 5954c414da9SCezary Rojewski struct snd_compr_stream *cstream, 5964c414da9SCezary Rojewski struct snd_compr_tstamp *tstamp, 5974c414da9SCezary Rojewski struct snd_soc_dai *dai); 5984c414da9SCezary Rojewski #endif 5994c414da9SCezary Rojewski 600dd96dacaSLiam Girdwood /* 601dd96dacaSLiam Girdwood * DSP IPC Operations. 602dd96dacaSLiam Girdwood */ 603dd96dacaSLiam Girdwood int hda_dsp_ipc_send_msg(struct snd_sof_dev *sdev, 604dd96dacaSLiam Girdwood struct snd_sof_ipc_msg *msg); 605dd96dacaSLiam Girdwood void hda_dsp_ipc_get_reply(struct snd_sof_dev *sdev); 6066eebd390SDaniel Baluta int hda_dsp_ipc_get_mailbox_offset(struct snd_sof_dev *sdev); 6076eebd390SDaniel Baluta int hda_dsp_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id); 6086eebd390SDaniel Baluta 609dd96dacaSLiam Girdwood irqreturn_t hda_dsp_ipc_irq_thread(int irq, void *context); 610dd96dacaSLiam Girdwood int hda_dsp_ipc_cmd_done(struct snd_sof_dev *sdev, int dir); 611dd96dacaSLiam Girdwood 612dd96dacaSLiam Girdwood /* 613dd96dacaSLiam Girdwood * DSP Code loader. 614dd96dacaSLiam Girdwood */ 615dd96dacaSLiam Girdwood int hda_dsp_cl_boot_firmware(struct snd_sof_dev *sdev); 616acf705a4SRanjani Sridharan int hda_dsp_cl_boot_firmware_iccmax(struct snd_sof_dev *sdev); 617dd96dacaSLiam Girdwood 618dd96dacaSLiam Girdwood /* pre and post fw run ops */ 619dd96dacaSLiam Girdwood int hda_dsp_pre_fw_run(struct snd_sof_dev *sdev); 620dd96dacaSLiam Girdwood int hda_dsp_post_fw_run(struct snd_sof_dev *sdev); 621dd96dacaSLiam Girdwood 622edbaaadaSFred Oh /* parse platform specific ext manifest ops */ 623edbaaadaSFred Oh int hda_dsp_ext_man_get_cavs_config_data(struct snd_sof_dev *sdev, 624edbaaadaSFred Oh const struct sof_ext_man_elem_header *hdr); 625edbaaadaSFred Oh 626dd96dacaSLiam Girdwood /* 627dd96dacaSLiam Girdwood * HDA Controller Operations. 628dd96dacaSLiam Girdwood */ 629dd96dacaSLiam Girdwood int hda_dsp_ctrl_get_caps(struct snd_sof_dev *sdev); 630dd96dacaSLiam Girdwood void hda_dsp_ctrl_ppcap_enable(struct snd_sof_dev *sdev, bool enable); 631dd96dacaSLiam Girdwood void hda_dsp_ctrl_ppcap_int_enable(struct snd_sof_dev *sdev, bool enable); 632dd96dacaSLiam Girdwood int hda_dsp_ctrl_link_reset(struct snd_sof_dev *sdev, bool reset); 633dd96dacaSLiam Girdwood void hda_dsp_ctrl_misc_clock_gating(struct snd_sof_dev *sdev, bool enable); 634dd96dacaSLiam Girdwood int hda_dsp_ctrl_clock_power_gating(struct snd_sof_dev *sdev, bool enable); 635dd96dacaSLiam Girdwood int hda_dsp_ctrl_init_chip(struct snd_sof_dev *sdev, bool full_reset); 63613063a2cSZhu Yingjiang void hda_dsp_ctrl_stop_chip(struct snd_sof_dev *sdev); 637dd96dacaSLiam Girdwood /* 638dd96dacaSLiam Girdwood * HDA bus operations. 639dd96dacaSLiam Girdwood */ 640d4ff1b39STakashi Iwai void sof_hda_bus_init(struct hdac_bus *bus, struct device *dev); 641dd96dacaSLiam Girdwood 642dd96dacaSLiam Girdwood #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) 643dd96dacaSLiam Girdwood /* 644dd96dacaSLiam Girdwood * HDA Codec operations. 645dd96dacaSLiam Girdwood */ 64691dce767SKai Vehmanen void hda_codec_probe_bus(struct snd_sof_dev *sdev, 64780acdd4fSRanjani Sridharan bool hda_codec_use_common_hdmi); 64831ba0c07SKai-Heng Feng void hda_codec_jack_wake_enable(struct snd_sof_dev *sdev, bool enable); 649fd15f2f5SRander Wang void hda_codec_jack_check(struct snd_sof_dev *sdev); 650dd96dacaSLiam Girdwood 651dd96dacaSLiam Girdwood #endif /* CONFIG_SND_SOC_SOF_HDA */ 652dd96dacaSLiam Girdwood 653139c7febSKai Vehmanen #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) && \ 654139c7febSKai Vehmanen (IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI) || \ 655139c7febSKai Vehmanen IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) 656dd96dacaSLiam Girdwood 65723ee0903SKai Vehmanen void hda_codec_i915_display_power(struct snd_sof_dev *sdev, bool enable); 658dd96dacaSLiam Girdwood int hda_codec_i915_init(struct snd_sof_dev *sdev); 659dd96dacaSLiam Girdwood int hda_codec_i915_exit(struct snd_sof_dev *sdev); 660dd96dacaSLiam Girdwood 661dd96dacaSLiam Girdwood #else 662dd96dacaSLiam Girdwood 66323ee0903SKai Vehmanen static inline void hda_codec_i915_display_power(struct snd_sof_dev *sdev, 66423ee0903SKai Vehmanen bool enable) { } 665dd96dacaSLiam Girdwood static inline int hda_codec_i915_init(struct snd_sof_dev *sdev) { return 0; } 666dd96dacaSLiam Girdwood static inline int hda_codec_i915_exit(struct snd_sof_dev *sdev) { return 0; } 667dd96dacaSLiam Girdwood 668139c7febSKai Vehmanen #endif 669dd96dacaSLiam Girdwood 670dd96dacaSLiam Girdwood /* 671dd96dacaSLiam Girdwood * Trace Control. 672dd96dacaSLiam Girdwood */ 673*bab05b50SPeter Ujfalusi int hda_dsp_trace_init(struct snd_sof_dev *sdev, 674*bab05b50SPeter Ujfalusi struct sof_ipc_dma_trace_params_ext *dtrace_params); 675dd96dacaSLiam Girdwood int hda_dsp_trace_release(struct snd_sof_dev *sdev); 676dd96dacaSLiam Girdwood int hda_dsp_trace_trigger(struct snd_sof_dev *sdev, int cmd); 677dd96dacaSLiam Girdwood 67851dfed1eSPierre-Louis Bossart /* 67951dfed1eSPierre-Louis Bossart * SoundWire support 68051dfed1eSPierre-Louis Bossart */ 68151dfed1eSPierre-Louis Bossart #if IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE) 68251dfed1eSPierre-Louis Bossart 68351dfed1eSPierre-Louis Bossart int hda_sdw_startup(struct snd_sof_dev *sdev); 68451dfed1eSPierre-Louis Bossart void hda_sdw_int_enable(struct snd_sof_dev *sdev, bool enable); 685bbd19cdcSRander Wang void hda_sdw_process_wakeen(struct snd_sof_dev *sdev); 686198fa4bcSBard Liao bool hda_common_check_sdw_irq(struct snd_sof_dev *sdev); 68751dfed1eSPierre-Louis Bossart 68851dfed1eSPierre-Louis Bossart #else 68951dfed1eSPierre-Louis Bossart 69051dfed1eSPierre-Louis Bossart static inline int hda_sdw_startup(struct snd_sof_dev *sdev) 69151dfed1eSPierre-Louis Bossart { 69251dfed1eSPierre-Louis Bossart return 0; 69351dfed1eSPierre-Louis Bossart } 69451dfed1eSPierre-Louis Bossart 69551dfed1eSPierre-Louis Bossart static inline void hda_sdw_int_enable(struct snd_sof_dev *sdev, bool enable) 69651dfed1eSPierre-Louis Bossart { 69751dfed1eSPierre-Louis Bossart } 69851dfed1eSPierre-Louis Bossart 699bbd19cdcSRander Wang static inline void hda_sdw_process_wakeen(struct snd_sof_dev *sdev) 700bbd19cdcSRander Wang { 701bbd19cdcSRander Wang } 702198fa4bcSBard Liao 703198fa4bcSBard Liao static inline bool hda_common_check_sdw_irq(struct snd_sof_dev *sdev) 704198fa4bcSBard Liao { 705198fa4bcSBard Liao return false; 706198fa4bcSBard Liao } 707198fa4bcSBard Liao 70851dfed1eSPierre-Louis Bossart #endif 70951dfed1eSPierre-Louis Bossart 710dd96dacaSLiam Girdwood /* common dai driver */ 711dd96dacaSLiam Girdwood extern struct snd_soc_dai_driver skl_dai[]; 712dd96dacaSLiam Girdwood 713dd96dacaSLiam Girdwood /* 714dd96dacaSLiam Girdwood * Platform Specific HW abstraction Ops. 715dd96dacaSLiam Girdwood */ 716dd96dacaSLiam Girdwood extern const struct snd_sof_dsp_ops sof_apl_ops; 717dd96dacaSLiam Girdwood extern const struct snd_sof_dsp_ops sof_cnl_ops; 7188b98491aSRanjani Sridharan extern const struct snd_sof_dsp_ops sof_tgl_ops; 7190cde3e9fSFred Oh extern const struct snd_sof_dsp_ops sof_icl_ops; 720dd96dacaSLiam Girdwood 721dd96dacaSLiam Girdwood extern const struct sof_intel_dsp_desc apl_chip_info; 722dd96dacaSLiam Girdwood extern const struct sof_intel_dsp_desc cnl_chip_info; 723dd96dacaSLiam Girdwood extern const struct sof_intel_dsp_desc skl_chip_info; 724630be964SZhu Yingjiang extern const struct sof_intel_dsp_desc icl_chip_info; 7251205c81eSPan Xiuli extern const struct sof_intel_dsp_desc tgl_chip_info; 72630ee3738SRander Wang extern const struct sof_intel_dsp_desc tglh_chip_info; 72761732690SPan Xiuli extern const struct sof_intel_dsp_desc ehl_chip_info; 7286fd99035SPan Xiuli extern const struct sof_intel_dsp_desc jsl_chip_info; 7296c2b6bb0SKai Vehmanen extern const struct sof_intel_dsp_desc adls_chip_info; 730dd96dacaSLiam Girdwood 731285880a2SDaniel Baluta /* machine driver select */ 732cb515f10SGuennadi Liakhovetski struct snd_soc_acpi_mach *hda_machine_select(struct snd_sof_dev *sdev); 733cb515f10SGuennadi Liakhovetski void hda_set_mach_params(struct snd_soc_acpi_mach *mach, 73417e9d6b0SPierre-Louis Bossart struct snd_sof_dev *sdev); 735285880a2SDaniel Baluta 736194fe0fcSPierre-Louis Bossart /* PCI driver selection and probe */ 737194fe0fcSPierre-Louis Bossart int hda_pci_intel_probe(struct pci_dev *pci, const struct pci_device_id *pci_id); 738194fe0fcSPierre-Louis Bossart 7390acb48ddSRanjani Sridharan struct snd_sof_dai; 7400acb48ddSRanjani Sridharan struct sof_ipc_dai_config; 741a0f84dfbSRanjani Sridharan int hda_ctrl_dai_widget_setup(struct snd_soc_dapm_widget *w, unsigned int quirk_flags); 742a0f84dfbSRanjani Sridharan int hda_ctrl_dai_widget_free(struct snd_soc_dapm_widget *w, unsigned int quirk_flags); 7430acb48ddSRanjani Sridharan 744288fad2fSPierre-Louis Bossart #define SOF_HDA_POSITION_QUIRK_USE_SKYLAKE_LEGACY (0) /* previous implementation */ 745288fad2fSPierre-Louis Bossart #define SOF_HDA_POSITION_QUIRK_USE_DPIB_REGISTERS (1) /* recommended if VC0 only */ 746288fad2fSPierre-Louis Bossart #define SOF_HDA_POSITION_QUIRK_USE_DPIB_DDR_UPDATE (2) /* recommended with VC0 or VC1 */ 747288fad2fSPierre-Louis Bossart 748288fad2fSPierre-Louis Bossart extern int sof_hda_position_quirk; 749288fad2fSPierre-Louis Bossart 750dd96dacaSLiam Girdwood #endif 751