1e149ca29SPierre-Louis Bossart /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ 2dd96dacaSLiam Girdwood /* 3dd96dacaSLiam Girdwood * This file is provided under a dual BSD/GPLv2 license. When using or 4dd96dacaSLiam Girdwood * redistributing this file, you may do so under either license. 5dd96dacaSLiam Girdwood * 6dd96dacaSLiam Girdwood * Copyright(c) 2017 Intel Corporation. All rights reserved. 7dd96dacaSLiam Girdwood * 8dd96dacaSLiam Girdwood * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com> 9dd96dacaSLiam Girdwood */ 10dd96dacaSLiam Girdwood 11dd96dacaSLiam Girdwood #ifndef __SOF_INTEL_HDA_H 12dd96dacaSLiam Girdwood #define __SOF_INTEL_HDA_H 13dd96dacaSLiam Girdwood 1451dfed1eSPierre-Louis Bossart #include <linux/soundwire/sdw.h> 1551dfed1eSPierre-Louis Bossart #include <linux/soundwire/sdw_intel.h> 164c414da9SCezary Rojewski #include <sound/compress_driver.h> 17dd96dacaSLiam Girdwood #include <sound/hda_codec.h> 18dd96dacaSLiam Girdwood #include <sound/hdaudio_ext.h> 19dd96dacaSLiam Girdwood #include "shim.h" 20dd96dacaSLiam Girdwood 21dd96dacaSLiam Girdwood /* PCI registers */ 22dd96dacaSLiam Girdwood #define PCI_TCSEL 0x44 23dd96dacaSLiam Girdwood #define PCI_PGCTL PCI_TCSEL 24dd96dacaSLiam Girdwood #define PCI_CGCTL 0x48 25dd96dacaSLiam Girdwood 26dd96dacaSLiam Girdwood /* PCI_PGCTL bits */ 27dd96dacaSLiam Girdwood #define PCI_PGCTL_ADSPPGD BIT(2) 28dd96dacaSLiam Girdwood #define PCI_PGCTL_LSRMD_MASK BIT(4) 29dd96dacaSLiam Girdwood 30dd96dacaSLiam Girdwood /* PCI_CGCTL bits */ 31dd96dacaSLiam Girdwood #define PCI_CGCTL_MISCBDCGE_MASK BIT(6) 32dd96dacaSLiam Girdwood #define PCI_CGCTL_ADSPDCGE BIT(1) 33dd96dacaSLiam Girdwood 34dd96dacaSLiam Girdwood /* Legacy HDA registers and bits used - widths are variable */ 35dd96dacaSLiam Girdwood #define SOF_HDA_GCAP 0x0 36dd96dacaSLiam Girdwood #define SOF_HDA_GCTL 0x8 37dd96dacaSLiam Girdwood /* accept unsol. response enable */ 38dd96dacaSLiam Girdwood #define SOF_HDA_GCTL_UNSOL BIT(8) 39dd96dacaSLiam Girdwood #define SOF_HDA_LLCH 0x14 40dd96dacaSLiam Girdwood #define SOF_HDA_INTCTL 0x20 41dd96dacaSLiam Girdwood #define SOF_HDA_INTSTS 0x24 42dd96dacaSLiam Girdwood #define SOF_HDA_WAKESTS 0x0E 43dd96dacaSLiam Girdwood #define SOF_HDA_WAKESTS_INT_MASK ((1 << 8) - 1) 44dd96dacaSLiam Girdwood #define SOF_HDA_RIRBSTS 0x5d 45dd96dacaSLiam Girdwood 46dd96dacaSLiam Girdwood /* SOF_HDA_GCTL register bist */ 47dd96dacaSLiam Girdwood #define SOF_HDA_GCTL_RESET BIT(0) 48dd96dacaSLiam Girdwood 497c11af9fSBard Liao /* SOF_HDA_INCTL regs */ 50dd96dacaSLiam Girdwood #define SOF_HDA_INT_GLOBAL_EN BIT(31) 51dd96dacaSLiam Girdwood #define SOF_HDA_INT_CTRL_EN BIT(30) 52dd96dacaSLiam Girdwood #define SOF_HDA_INT_ALL_STREAM 0xff 53dd96dacaSLiam Girdwood 547c11af9fSBard Liao /* SOF_HDA_INTSTS regs */ 557c11af9fSBard Liao #define SOF_HDA_INTSTS_GIS BIT(31) 567c11af9fSBard Liao 57dd96dacaSLiam Girdwood #define SOF_HDA_MAX_CAPS 10 58dd96dacaSLiam Girdwood #define SOF_HDA_CAP_ID_OFF 16 59dd96dacaSLiam Girdwood #define SOF_HDA_CAP_ID_MASK GENMASK(SOF_HDA_CAP_ID_OFF + 11,\ 60dd96dacaSLiam Girdwood SOF_HDA_CAP_ID_OFF) 61dd96dacaSLiam Girdwood #define SOF_HDA_CAP_NEXT_MASK 0xFFFF 62dd96dacaSLiam Girdwood 63dd96dacaSLiam Girdwood #define SOF_HDA_GTS_CAP_ID 0x1 64dd96dacaSLiam Girdwood #define SOF_HDA_ML_CAP_ID 0x2 65dd96dacaSLiam Girdwood 66dd96dacaSLiam Girdwood #define SOF_HDA_PP_CAP_ID 0x3 67dd96dacaSLiam Girdwood #define SOF_HDA_REG_PP_PPCH 0x10 68dd96dacaSLiam Girdwood #define SOF_HDA_REG_PP_PPCTL 0x04 69f1fd9d0eSKai Vehmanen #define SOF_HDA_REG_PP_PPSTS 0x08 70dd96dacaSLiam Girdwood #define SOF_HDA_PPCTL_PIE BIT(31) 71dd96dacaSLiam Girdwood #define SOF_HDA_PPCTL_GPROCEN BIT(30) 72dd96dacaSLiam Girdwood 7362f8f766SKeyon Jie /*Vendor Specific Registers*/ 7462f8f766SKeyon Jie #define SOF_HDA_VS_D0I3C 0x104A 7562f8f766SKeyon Jie 7662f8f766SKeyon Jie /* D0I3C Register fields */ 7762f8f766SKeyon Jie #define SOF_HDA_VS_D0I3C_CIP BIT(0) /* Command-In-Progress */ 7862f8f766SKeyon Jie #define SOF_HDA_VS_D0I3C_I3 BIT(2) /* D0i3 enable bit */ 7962f8f766SKeyon Jie 80dd96dacaSLiam Girdwood /* DPIB entry size: 8 Bytes = 2 DWords */ 81dd96dacaSLiam Girdwood #define SOF_HDA_DPIB_ENTRY_SIZE 0x8 82dd96dacaSLiam Girdwood 83dd96dacaSLiam Girdwood #define SOF_HDA_SPIB_CAP_ID 0x4 84dd96dacaSLiam Girdwood #define SOF_HDA_DRSM_CAP_ID 0x5 85dd96dacaSLiam Girdwood 86dd96dacaSLiam Girdwood #define SOF_HDA_SPIB_BASE 0x08 87dd96dacaSLiam Girdwood #define SOF_HDA_SPIB_INTERVAL 0x08 88dd96dacaSLiam Girdwood #define SOF_HDA_SPIB_SPIB 0x00 89dd96dacaSLiam Girdwood #define SOF_HDA_SPIB_MAXFIFO 0x04 90dd96dacaSLiam Girdwood 91dd96dacaSLiam Girdwood #define SOF_HDA_PPHC_BASE 0x10 92dd96dacaSLiam Girdwood #define SOF_HDA_PPHC_INTERVAL 0x10 93dd96dacaSLiam Girdwood 94dd96dacaSLiam Girdwood #define SOF_HDA_PPLC_BASE 0x10 95dd96dacaSLiam Girdwood #define SOF_HDA_PPLC_MULTI 0x10 96dd96dacaSLiam Girdwood #define SOF_HDA_PPLC_INTERVAL 0x10 97dd96dacaSLiam Girdwood 98dd96dacaSLiam Girdwood #define SOF_HDA_DRSM_BASE 0x08 99dd96dacaSLiam Girdwood #define SOF_HDA_DRSM_INTERVAL 0x08 100dd96dacaSLiam Girdwood 101dd96dacaSLiam Girdwood /* Descriptor error interrupt */ 102dd96dacaSLiam Girdwood #define SOF_HDA_CL_DMA_SD_INT_DESC_ERR 0x10 103dd96dacaSLiam Girdwood 104dd96dacaSLiam Girdwood /* FIFO error interrupt */ 105dd96dacaSLiam Girdwood #define SOF_HDA_CL_DMA_SD_INT_FIFO_ERR 0x08 106dd96dacaSLiam Girdwood 107dd96dacaSLiam Girdwood /* Buffer completion interrupt */ 108dd96dacaSLiam Girdwood #define SOF_HDA_CL_DMA_SD_INT_COMPLETE 0x04 109dd96dacaSLiam Girdwood 110dd96dacaSLiam Girdwood #define SOF_HDA_CL_DMA_SD_INT_MASK \ 111dd96dacaSLiam Girdwood (SOF_HDA_CL_DMA_SD_INT_DESC_ERR | \ 112dd96dacaSLiam Girdwood SOF_HDA_CL_DMA_SD_INT_FIFO_ERR | \ 113dd96dacaSLiam Girdwood SOF_HDA_CL_DMA_SD_INT_COMPLETE) 114dd96dacaSLiam Girdwood #define SOF_HDA_SD_CTL_DMA_START 0x02 /* Stream DMA start bit */ 115dd96dacaSLiam Girdwood 116dd96dacaSLiam Girdwood /* Intel HD Audio Code Loader DMA Registers */ 117dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_LOADER_BASE 0x80 118dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_DPLBASE 0x70 119dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_DPUBASE 0x74 120dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_DPLBASE_ENABLE 0x01 121dd96dacaSLiam Girdwood 122dd96dacaSLiam Girdwood /* Stream Registers */ 123dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SD_CTL 0x00 124dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SD_STS 0x03 125dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SD_LPIB 0x04 126dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SD_CBL 0x08 127dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SD_LVI 0x0C 128dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SD_FIFOW 0x0E 129dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SD_FIFOSIZE 0x10 130dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SD_FORMAT 0x12 131dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SD_FIFOL 0x14 132dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SD_BDLPL 0x18 133dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SD_BDLPU 0x1C 134dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_SD_ENTRY_SIZE 0x20 135dd96dacaSLiam Girdwood 136dd96dacaSLiam Girdwood /* CL: Software Position Based FIFO Capability Registers */ 137dd96dacaSLiam Girdwood #define SOF_DSP_REG_CL_SPBFIFO \ 138dd96dacaSLiam Girdwood (SOF_HDA_ADSP_LOADER_BASE + 0x20) 139dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCH 0x0 140dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCCTL 0x4 141dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPIB 0x8 142dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SPBFIFO_MAXFIFOS 0xc 143dd96dacaSLiam Girdwood 144dd96dacaSLiam Girdwood /* Stream Number */ 145dd96dacaSLiam Girdwood #define SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT 20 146dd96dacaSLiam Girdwood #define SOF_HDA_CL_SD_CTL_STREAM_TAG_MASK \ 147dd96dacaSLiam Girdwood GENMASK(SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT + 3,\ 148dd96dacaSLiam Girdwood SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT) 149dd96dacaSLiam Girdwood 150dd96dacaSLiam Girdwood #define HDA_DSP_HDA_BAR 0 151dd96dacaSLiam Girdwood #define HDA_DSP_PP_BAR 1 152dd96dacaSLiam Girdwood #define HDA_DSP_SPIB_BAR 2 153dd96dacaSLiam Girdwood #define HDA_DSP_DRSM_BAR 3 154dd96dacaSLiam Girdwood #define HDA_DSP_BAR 4 155dd96dacaSLiam Girdwood 156dd96dacaSLiam Girdwood #define SRAM_WINDOW_OFFSET(x) (0x80000 + (x) * 0x20000) 157dd96dacaSLiam Girdwood 158dd96dacaSLiam Girdwood #define HDA_DSP_MBOX_OFFSET SRAM_WINDOW_OFFSET(0) 159dd96dacaSLiam Girdwood 160dd96dacaSLiam Girdwood #define HDA_DSP_PANIC_OFFSET(x) \ 161dd96dacaSLiam Girdwood (((x) & 0xFFFFFF) + HDA_DSP_MBOX_OFFSET) 162dd96dacaSLiam Girdwood 163dd96dacaSLiam Girdwood /* SRAM window 0 FW "registers" */ 164dd96dacaSLiam Girdwood #define HDA_DSP_SRAM_REG_ROM_STATUS (HDA_DSP_MBOX_OFFSET + 0x0) 165dd96dacaSLiam Girdwood #define HDA_DSP_SRAM_REG_ROM_ERROR (HDA_DSP_MBOX_OFFSET + 0x4) 166dd96dacaSLiam Girdwood /* FW and ROM share offset 4 */ 167dd96dacaSLiam Girdwood #define HDA_DSP_SRAM_REG_FW_STATUS (HDA_DSP_MBOX_OFFSET + 0x4) 168dd96dacaSLiam Girdwood #define HDA_DSP_SRAM_REG_FW_TRACEP (HDA_DSP_MBOX_OFFSET + 0x8) 169dd96dacaSLiam Girdwood #define HDA_DSP_SRAM_REG_FW_END (HDA_DSP_MBOX_OFFSET + 0xc) 170dd96dacaSLiam Girdwood 171dd96dacaSLiam Girdwood #define HDA_DSP_MBOX_UPLINK_OFFSET 0x81000 172dd96dacaSLiam Girdwood 173dd96dacaSLiam Girdwood #define HDA_DSP_STREAM_RESET_TIMEOUT 300 1747bcaf0f2SZhu Yingjiang /* 1757bcaf0f2SZhu Yingjiang * Timeout in us, for setting the stream RUN bit, during 1767bcaf0f2SZhu Yingjiang * start/stop the stream. The timeout expires if new RUN bit 1777bcaf0f2SZhu Yingjiang * value cannot be read back within the specified time. 1787bcaf0f2SZhu Yingjiang */ 1797bcaf0f2SZhu Yingjiang #define HDA_DSP_STREAM_RUN_TIMEOUT 300 180dd96dacaSLiam Girdwood 181dd96dacaSLiam Girdwood #define HDA_DSP_SPIB_ENABLE 1 182dd96dacaSLiam Girdwood #define HDA_DSP_SPIB_DISABLE 0 183dd96dacaSLiam Girdwood 184dd96dacaSLiam Girdwood #define SOF_HDA_MAX_BUFFER_SIZE (32 * PAGE_SIZE) 185dd96dacaSLiam Girdwood 186dd96dacaSLiam Girdwood #define HDA_DSP_STACK_DUMP_SIZE 32 187dd96dacaSLiam Girdwood 188dd96dacaSLiam Girdwood /* ROM status/error values */ 189184fdfcaSKeyon Jie #define HDA_DSP_ROM_STS_MASK GENMASK(23, 0) 190dd96dacaSLiam Girdwood #define HDA_DSP_ROM_INIT 0x1 191dd96dacaSLiam Girdwood #define HDA_DSP_ROM_FW_MANIFEST_LOADED 0x3 192dd96dacaSLiam Girdwood #define HDA_DSP_ROM_FW_FW_LOADED 0x4 193dd96dacaSLiam Girdwood #define HDA_DSP_ROM_FW_ENTERED 0x5 194dd96dacaSLiam Girdwood #define HDA_DSP_ROM_RFW_START 0xf 195dd96dacaSLiam Girdwood #define HDA_DSP_ROM_CSE_ERROR 40 196dd96dacaSLiam Girdwood #define HDA_DSP_ROM_CSE_WRONG_RESPONSE 41 197dd96dacaSLiam Girdwood #define HDA_DSP_ROM_IMR_TO_SMALL 42 198dd96dacaSLiam Girdwood #define HDA_DSP_ROM_BASE_FW_NOT_FOUND 43 199dd96dacaSLiam Girdwood #define HDA_DSP_ROM_CSE_VALIDATION_FAILED 44 200dd96dacaSLiam Girdwood #define HDA_DSP_ROM_IPC_FATAL_ERROR 45 201dd96dacaSLiam Girdwood #define HDA_DSP_ROM_L2_CACHE_ERROR 46 202dd96dacaSLiam Girdwood #define HDA_DSP_ROM_LOAD_OFFSET_TO_SMALL 47 203dd96dacaSLiam Girdwood #define HDA_DSP_ROM_API_PTR_INVALID 50 204dd96dacaSLiam Girdwood #define HDA_DSP_ROM_BASEFW_INCOMPAT 51 205dd96dacaSLiam Girdwood #define HDA_DSP_ROM_UNHANDLED_INTERRUPT 0xBEE00000 206dd96dacaSLiam Girdwood #define HDA_DSP_ROM_MEMORY_HOLE_ECC 0xECC00000 207dd96dacaSLiam Girdwood #define HDA_DSP_ROM_KERNEL_EXCEPTION 0xCAFE0000 208dd96dacaSLiam Girdwood #define HDA_DSP_ROM_USER_EXCEPTION 0xBEEF0000 209dd96dacaSLiam Girdwood #define HDA_DSP_ROM_UNEXPECTED_RESET 0xDECAF000 210dd96dacaSLiam Girdwood #define HDA_DSP_ROM_NULL_FW_ENTRY 0x4c4c4e55 211dd96dacaSLiam Girdwood #define HDA_DSP_IPC_PURGE_FW 0x01004000 212dd96dacaSLiam Girdwood 213dd96dacaSLiam Girdwood /* various timeout values */ 214dd96dacaSLiam Girdwood #define HDA_DSP_PU_TIMEOUT 50 215dd96dacaSLiam Girdwood #define HDA_DSP_PD_TIMEOUT 50 216dd96dacaSLiam Girdwood #define HDA_DSP_RESET_TIMEOUT_US 50000 217dd96dacaSLiam Girdwood #define HDA_DSP_BASEFW_TIMEOUT_US 3000000 218dd96dacaSLiam Girdwood #define HDA_DSP_INIT_TIMEOUT_US 500000 219dd96dacaSLiam Girdwood #define HDA_DSP_CTRL_RESET_TIMEOUT 100 220dd96dacaSLiam Girdwood #define HDA_DSP_WAIT_TIMEOUT 500 /* 500 msec */ 221dd96dacaSLiam Girdwood #define HDA_DSP_REG_POLL_INTERVAL_US 500 /* 0.5 msec */ 22292f4beb7SKeyon Jie #define HDA_DSP_REG_POLL_RETRY_COUNT 50 223dd96dacaSLiam Girdwood 224dd96dacaSLiam Girdwood #define HDA_DSP_ADSPIC_IPC 1 225dd96dacaSLiam Girdwood #define HDA_DSP_ADSPIS_IPC 1 226dd96dacaSLiam Girdwood 227dd96dacaSLiam Girdwood /* Intel HD Audio General DSP Registers */ 228dd96dacaSLiam Girdwood #define HDA_DSP_GEN_BASE 0x0 229dd96dacaSLiam Girdwood #define HDA_DSP_REG_ADSPCS (HDA_DSP_GEN_BASE + 0x04) 230dd96dacaSLiam Girdwood #define HDA_DSP_REG_ADSPIC (HDA_DSP_GEN_BASE + 0x08) 231dd96dacaSLiam Girdwood #define HDA_DSP_REG_ADSPIS (HDA_DSP_GEN_BASE + 0x0C) 232dd96dacaSLiam Girdwood #define HDA_DSP_REG_ADSPIC2 (HDA_DSP_GEN_BASE + 0x10) 233dd96dacaSLiam Girdwood #define HDA_DSP_REG_ADSPIS2 (HDA_DSP_GEN_BASE + 0x14) 234dd96dacaSLiam Girdwood 235722ba5f1SBard Liao #define HDA_DSP_REG_ADSPIS2_SNDW BIT(5) 23690de3281SRander Wang #define HDA_DSP_REG_SNDW_WAKE_STS 0x2C192 237722ba5f1SBard Liao 238dd96dacaSLiam Girdwood /* Intel HD Audio Inter-Processor Communication Registers */ 239dd96dacaSLiam Girdwood #define HDA_DSP_IPC_BASE 0x40 240dd96dacaSLiam Girdwood #define HDA_DSP_REG_HIPCT (HDA_DSP_IPC_BASE + 0x00) 241dd96dacaSLiam Girdwood #define HDA_DSP_REG_HIPCTE (HDA_DSP_IPC_BASE + 0x04) 242dd96dacaSLiam Girdwood #define HDA_DSP_REG_HIPCI (HDA_DSP_IPC_BASE + 0x08) 243dd96dacaSLiam Girdwood #define HDA_DSP_REG_HIPCIE (HDA_DSP_IPC_BASE + 0x0C) 244dd96dacaSLiam Girdwood #define HDA_DSP_REG_HIPCCTL (HDA_DSP_IPC_BASE + 0x10) 245dd96dacaSLiam Girdwood 24643b2ab90SRanjani Sridharan /* Intel Vendor Specific Registers */ 24743b2ab90SRanjani Sridharan #define HDA_VS_INTEL_EM2 0x1030 24843b2ab90SRanjani Sridharan #define HDA_VS_INTEL_EM2_L1SEN BIT(13) 249aca961f1SRanjani Sridharan #define HDA_VS_INTEL_LTRP_GB_MASK 0x3F 25043b2ab90SRanjani Sridharan 251dd96dacaSLiam Girdwood /* HIPCI */ 252dd96dacaSLiam Girdwood #define HDA_DSP_REG_HIPCI_BUSY BIT(31) 253dd96dacaSLiam Girdwood #define HDA_DSP_REG_HIPCI_MSG_MASK 0x7FFFFFFF 254dd96dacaSLiam Girdwood 255dd96dacaSLiam Girdwood /* HIPCIE */ 256dd96dacaSLiam Girdwood #define HDA_DSP_REG_HIPCIE_DONE BIT(30) 257dd96dacaSLiam Girdwood #define HDA_DSP_REG_HIPCIE_MSG_MASK 0x3FFFFFFF 258dd96dacaSLiam Girdwood 259dd96dacaSLiam Girdwood /* HIPCCTL */ 260dd96dacaSLiam Girdwood #define HDA_DSP_REG_HIPCCTL_DONE BIT(1) 261dd96dacaSLiam Girdwood #define HDA_DSP_REG_HIPCCTL_BUSY BIT(0) 262dd96dacaSLiam Girdwood 263dd96dacaSLiam Girdwood /* HIPCT */ 264dd96dacaSLiam Girdwood #define HDA_DSP_REG_HIPCT_BUSY BIT(31) 265dd96dacaSLiam Girdwood #define HDA_DSP_REG_HIPCT_MSG_MASK 0x7FFFFFFF 266dd96dacaSLiam Girdwood 267dd96dacaSLiam Girdwood /* HIPCTE */ 268dd96dacaSLiam Girdwood #define HDA_DSP_REG_HIPCTE_MSG_MASK 0x3FFFFFFF 269dd96dacaSLiam Girdwood 270dd96dacaSLiam Girdwood #define HDA_DSP_ADSPIC_CL_DMA 0x2 271dd96dacaSLiam Girdwood #define HDA_DSP_ADSPIS_CL_DMA 0x2 272dd96dacaSLiam Girdwood 273dd96dacaSLiam Girdwood /* Delay before scheduling D0i3 entry */ 274dd96dacaSLiam Girdwood #define BXT_D0I3_DELAY 5000 275dd96dacaSLiam Girdwood 276dd96dacaSLiam Girdwood #define FW_CL_STREAM_NUMBER 0x1 277dd96dacaSLiam Girdwood 278dd96dacaSLiam Girdwood /* ADSPCS - Audio DSP Control & Status */ 279dd96dacaSLiam Girdwood 280dd96dacaSLiam Girdwood /* 281dd96dacaSLiam Girdwood * Core Reset - asserted high 282dd96dacaSLiam Girdwood * CRST Mask for a given core mask pattern, cm 283dd96dacaSLiam Girdwood */ 284dd96dacaSLiam Girdwood #define HDA_DSP_ADSPCS_CRST_SHIFT 0 285dd96dacaSLiam Girdwood #define HDA_DSP_ADSPCS_CRST_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CRST_SHIFT) 286dd96dacaSLiam Girdwood 287dd96dacaSLiam Girdwood /* 288dd96dacaSLiam Girdwood * Core run/stall - when set to '1' core is stalled 289dd96dacaSLiam Girdwood * CSTALL Mask for a given core mask pattern, cm 290dd96dacaSLiam Girdwood */ 291dd96dacaSLiam Girdwood #define HDA_DSP_ADSPCS_CSTALL_SHIFT 8 292dd96dacaSLiam Girdwood #define HDA_DSP_ADSPCS_CSTALL_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CSTALL_SHIFT) 293dd96dacaSLiam Girdwood 294dd96dacaSLiam Girdwood /* 295dd96dacaSLiam Girdwood * Set Power Active - when set to '1' turn cores on 296dd96dacaSLiam Girdwood * SPA Mask for a given core mask pattern, cm 297dd96dacaSLiam Girdwood */ 298dd96dacaSLiam Girdwood #define HDA_DSP_ADSPCS_SPA_SHIFT 16 299dd96dacaSLiam Girdwood #define HDA_DSP_ADSPCS_SPA_MASK(cm) ((cm) << HDA_DSP_ADSPCS_SPA_SHIFT) 300dd96dacaSLiam Girdwood 301dd96dacaSLiam Girdwood /* 302dd96dacaSLiam Girdwood * Current Power Active - power status of cores, set by hardware 303dd96dacaSLiam Girdwood * CPA Mask for a given core mask pattern, cm 304dd96dacaSLiam Girdwood */ 305dd96dacaSLiam Girdwood #define HDA_DSP_ADSPCS_CPA_SHIFT 24 306dd96dacaSLiam Girdwood #define HDA_DSP_ADSPCS_CPA_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CPA_SHIFT) 307dd96dacaSLiam Girdwood 308dd96dacaSLiam Girdwood /* Mask for a given core index, c = 0.. number of supported cores - 1 */ 309dd96dacaSLiam Girdwood #define HDA_DSP_CORE_MASK(c) BIT(c) 310dd96dacaSLiam Girdwood 311dd96dacaSLiam Girdwood /* 312dd96dacaSLiam Girdwood * Mask for a given number of cores 313dd96dacaSLiam Girdwood * nc = number of supported cores 314dd96dacaSLiam Girdwood */ 315dd96dacaSLiam Girdwood #define SOF_DSP_CORES_MASK(nc) GENMASK(((nc) - 1), 0) 316dd96dacaSLiam Girdwood 317dd96dacaSLiam Girdwood /* Intel HD Audio Inter-Processor Communication Registers for Cannonlake*/ 318dd96dacaSLiam Girdwood #define CNL_DSP_IPC_BASE 0xc0 319dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCTDR (CNL_DSP_IPC_BASE + 0x00) 320dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCTDA (CNL_DSP_IPC_BASE + 0x04) 321dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCTDD (CNL_DSP_IPC_BASE + 0x08) 322dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCIDR (CNL_DSP_IPC_BASE + 0x10) 323dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCIDA (CNL_DSP_IPC_BASE + 0x14) 3240267de58SKeyon Jie #define CNL_DSP_REG_HIPCIDD (CNL_DSP_IPC_BASE + 0x18) 325dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCCTL (CNL_DSP_IPC_BASE + 0x28) 326dd96dacaSLiam Girdwood 327dd96dacaSLiam Girdwood /* HIPCI */ 328dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCIDR_BUSY BIT(31) 329dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCIDR_MSG_MASK 0x7FFFFFFF 330dd96dacaSLiam Girdwood 331dd96dacaSLiam Girdwood /* HIPCIE */ 332dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCIDA_DONE BIT(31) 333dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCIDA_MSG_MASK 0x7FFFFFFF 334dd96dacaSLiam Girdwood 335dd96dacaSLiam Girdwood /* HIPCCTL */ 336dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCCTL_DONE BIT(1) 337dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCCTL_BUSY BIT(0) 338dd96dacaSLiam Girdwood 339dd96dacaSLiam Girdwood /* HIPCT */ 340dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCTDR_BUSY BIT(31) 341dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCTDR_MSG_MASK 0x7FFFFFFF 342dd96dacaSLiam Girdwood 343dd96dacaSLiam Girdwood /* HIPCTDA */ 344dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCTDA_DONE BIT(31) 345dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCTDA_MSG_MASK 0x7FFFFFFF 346dd96dacaSLiam Girdwood 347dd96dacaSLiam Girdwood /* HIPCTDD */ 348dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCTDD_MSG_MASK 0x7FFFFFFF 349dd96dacaSLiam Girdwood 350dd96dacaSLiam Girdwood /* BDL */ 351dd96dacaSLiam Girdwood #define HDA_DSP_BDL_SIZE 4096 352dd96dacaSLiam Girdwood #define HDA_DSP_MAX_BDL_ENTRIES \ 353dd96dacaSLiam Girdwood (HDA_DSP_BDL_SIZE / sizeof(struct sof_intel_dsp_bdl)) 354dd96dacaSLiam Girdwood 355dd96dacaSLiam Girdwood /* Number of DAIs */ 356dd96dacaSLiam Girdwood #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) 35770368106SCezary Rojewski 35870368106SCezary Rojewski #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_PROBES) 35970368106SCezary Rojewski #define SOF_SKL_NUM_DAIS 16 36070368106SCezary Rojewski #else 361a6947c9dSCezary Rojewski #define SOF_SKL_NUM_DAIS 15 36270368106SCezary Rojewski #endif 36370368106SCezary Rojewski 364dd96dacaSLiam Girdwood #else 365dd96dacaSLiam Girdwood #define SOF_SKL_NUM_DAIS 8 366dd96dacaSLiam Girdwood #endif 367dd96dacaSLiam Girdwood 368dd96dacaSLiam Girdwood /* Intel HD Audio SRAM Window 0*/ 369dd96dacaSLiam Girdwood #define HDA_ADSP_SRAM0_BASE_SKL 0x8000 370dd96dacaSLiam Girdwood 371dd96dacaSLiam Girdwood /* Firmware status window */ 372dd96dacaSLiam Girdwood #define HDA_ADSP_FW_STATUS_SKL HDA_ADSP_SRAM0_BASE_SKL 373dd96dacaSLiam Girdwood #define HDA_ADSP_ERROR_CODE_SKL (HDA_ADSP_FW_STATUS_SKL + 0x4) 374dd96dacaSLiam Girdwood 375df7e0de5SZhu Yingjiang /* Host Device Memory Space */ 376df7e0de5SZhu Yingjiang #define APL_SSP_BASE_OFFSET 0x2000 377df7e0de5SZhu Yingjiang #define CNL_SSP_BASE_OFFSET 0x10000 378df7e0de5SZhu Yingjiang 379df7e0de5SZhu Yingjiang /* Host Device Memory Size of a Single SSP */ 380df7e0de5SZhu Yingjiang #define SSP_DEV_MEM_SIZE 0x1000 381df7e0de5SZhu Yingjiang 382b095fe47SZhu Yingjiang /* SSP Count of the Platform */ 383b095fe47SZhu Yingjiang #define APL_SSP_COUNT 6 384b095fe47SZhu Yingjiang #define CNL_SSP_COUNT 3 385ec836daaSZhu Yingjiang #define ICL_SSP_COUNT 6 386b095fe47SZhu Yingjiang 38774ed4097SZhu Yingjiang /* SSP Registers */ 38874ed4097SZhu Yingjiang #define SSP_SSC1_OFFSET 0x4 38974ed4097SZhu Yingjiang #define SSP_SET_SCLK_SLAVE BIT(25) 39074ed4097SZhu Yingjiang #define SSP_SET_SFRM_SLAVE BIT(24) 39174ed4097SZhu Yingjiang #define SSP_SET_SLAVE (SSP_SET_SCLK_SLAVE | SSP_SET_SFRM_SLAVE) 39274ed4097SZhu Yingjiang 393dd96dacaSLiam Girdwood #define HDA_IDISP_CODEC(x) ((x) & BIT(2)) 394dd96dacaSLiam Girdwood 395dd96dacaSLiam Girdwood struct sof_intel_dsp_bdl { 396dd96dacaSLiam Girdwood __le32 addr_l; 397dd96dacaSLiam Girdwood __le32 addr_h; 398dd96dacaSLiam Girdwood __le32 size; 399dd96dacaSLiam Girdwood __le32 ioc; 400dd96dacaSLiam Girdwood } __attribute((packed)); 401dd96dacaSLiam Girdwood 402dd96dacaSLiam Girdwood #define SOF_HDA_PLAYBACK_STREAMS 16 403dd96dacaSLiam Girdwood #define SOF_HDA_CAPTURE_STREAMS 16 404dd96dacaSLiam Girdwood #define SOF_HDA_PLAYBACK 0 405dd96dacaSLiam Girdwood #define SOF_HDA_CAPTURE 1 406dd96dacaSLiam Girdwood 40763e51fd3SRanjani Sridharan /* 40863e51fd3SRanjani Sridharan * Time in ms for opportunistic D0I3 entry delay. 40963e51fd3SRanjani Sridharan * This has been deliberately chosen to be long to avoid race conditions. 41063e51fd3SRanjani Sridharan * Could be optimized in future. 41163e51fd3SRanjani Sridharan */ 41263e51fd3SRanjani Sridharan #define SOF_HDA_D0I3_WORK_DELAY_MS 5000 41363e51fd3SRanjani Sridharan 41461e285caSRanjani Sridharan /* HDA DSP D0 substate */ 41561e285caSRanjani Sridharan enum sof_hda_D0_substate { 41661e285caSRanjani Sridharan SOF_HDA_DSP_PM_D0I0, /* default D0 substate */ 41761e285caSRanjani Sridharan SOF_HDA_DSP_PM_D0I3, /* low power D0 substate */ 41861e285caSRanjani Sridharan }; 41961e285caSRanjani Sridharan 420dd96dacaSLiam Girdwood /* represents DSP HDA controller frontend - i.e. host facing control */ 421dd96dacaSLiam Girdwood struct sof_intel_hda_dev { 422dd96dacaSLiam Girdwood 423dd96dacaSLiam Girdwood struct hda_bus hbus; 424dd96dacaSLiam Girdwood 425dd96dacaSLiam Girdwood /* hw config */ 426dd96dacaSLiam Girdwood const struct sof_intel_dsp_desc *desc; 427dd96dacaSLiam Girdwood 428dd96dacaSLiam Girdwood /* trace */ 429dd96dacaSLiam Girdwood struct hdac_ext_stream *dtrace_stream; 430dd96dacaSLiam Girdwood 431dd96dacaSLiam Girdwood /* if position update IPC needed */ 432dd96dacaSLiam Girdwood u32 no_ipc_position; 433dd96dacaSLiam Girdwood 434e8e55dbeSKeyon Jie /* the maximum number of streams (playback + capture) supported */ 435e8e55dbeSKeyon Jie u32 stream_max; 436e8e55dbeSKeyon Jie 43716299326SKeyon Jie /* PM related */ 43816299326SKeyon Jie bool l1_support_changed;/* during suspend, is L1SEN changed or not */ 43916299326SKeyon Jie 440dd96dacaSLiam Girdwood /* DMIC device */ 441dd96dacaSLiam Girdwood struct platform_device *dmic_dev; 44263e51fd3SRanjani Sridharan 44363e51fd3SRanjani Sridharan /* delayed work to enter D0I3 opportunistically */ 44463e51fd3SRanjani Sridharan struct delayed_work d0i3_work; 44551dfed1eSPierre-Louis Bossart 44651dfed1eSPierre-Louis Bossart /* ACPI information stored between scan and probe steps */ 44751dfed1eSPierre-Louis Bossart struct sdw_intel_acpi_info info; 44851dfed1eSPierre-Louis Bossart 44951dfed1eSPierre-Louis Bossart /* sdw context allocated by SoundWire driver */ 45051dfed1eSPierre-Louis Bossart struct sdw_intel_ctx *sdw; 451dd96dacaSLiam Girdwood }; 452dd96dacaSLiam Girdwood 453dd96dacaSLiam Girdwood static inline struct hdac_bus *sof_to_bus(struct snd_sof_dev *s) 454dd96dacaSLiam Girdwood { 455dd96dacaSLiam Girdwood struct sof_intel_hda_dev *hda = s->pdata->hw_pdata; 456dd96dacaSLiam Girdwood 457dd96dacaSLiam Girdwood return &hda->hbus.core; 458dd96dacaSLiam Girdwood } 459dd96dacaSLiam Girdwood 460dd96dacaSLiam Girdwood static inline struct hda_bus *sof_to_hbus(struct snd_sof_dev *s) 461dd96dacaSLiam Girdwood { 462dd96dacaSLiam Girdwood struct sof_intel_hda_dev *hda = s->pdata->hw_pdata; 463dd96dacaSLiam Girdwood 464dd96dacaSLiam Girdwood return &hda->hbus; 465dd96dacaSLiam Girdwood } 466dd96dacaSLiam Girdwood 467dd96dacaSLiam Girdwood struct sof_intel_hda_stream { 4687623ae79SRanjani Sridharan struct snd_sof_dev *sdev; 469dd96dacaSLiam Girdwood struct hdac_ext_stream hda_stream; 470dd96dacaSLiam Girdwood struct sof_intel_stream stream; 4716b2239e3SRanjani Sridharan int host_reserved; /* reserve host DMA channel */ 472dd96dacaSLiam Girdwood }; 473dd96dacaSLiam Girdwood 474f5dbba9fSRanjani Sridharan #define hstream_to_sof_hda_stream(hstream) \ 475f5dbba9fSRanjani Sridharan container_of(hstream, struct sof_intel_hda_stream, hda_stream) 476f5dbba9fSRanjani Sridharan 477dd96dacaSLiam Girdwood #define bus_to_sof_hda(bus) \ 478dd96dacaSLiam Girdwood container_of(bus, struct sof_intel_hda_dev, hbus.core) 479dd96dacaSLiam Girdwood 480dd96dacaSLiam Girdwood #define SOF_STREAM_SD_OFFSET(s) \ 481dd96dacaSLiam Girdwood (SOF_HDA_ADSP_SD_ENTRY_SIZE * ((s)->index) \ 482dd96dacaSLiam Girdwood + SOF_HDA_ADSP_LOADER_BASE) 483dd96dacaSLiam Girdwood 484dd96dacaSLiam Girdwood /* 485dd96dacaSLiam Girdwood * DSP Core services. 486dd96dacaSLiam Girdwood */ 487dd96dacaSLiam Girdwood int hda_dsp_probe(struct snd_sof_dev *sdev); 488dd96dacaSLiam Girdwood int hda_dsp_remove(struct snd_sof_dev *sdev); 489dd96dacaSLiam Girdwood int hda_dsp_core_reset_enter(struct snd_sof_dev *sdev, 490dd96dacaSLiam Girdwood unsigned int core_mask); 491dd96dacaSLiam Girdwood int hda_dsp_core_reset_leave(struct snd_sof_dev *sdev, 492dd96dacaSLiam Girdwood unsigned int core_mask); 493dd96dacaSLiam Girdwood int hda_dsp_core_stall_reset(struct snd_sof_dev *sdev, unsigned int core_mask); 494dd96dacaSLiam Girdwood int hda_dsp_core_run(struct snd_sof_dev *sdev, unsigned int core_mask); 495dd96dacaSLiam Girdwood int hda_dsp_core_power_up(struct snd_sof_dev *sdev, unsigned int core_mask); 496dd96dacaSLiam Girdwood int hda_dsp_enable_core(struct snd_sof_dev *sdev, unsigned int core_mask); 497dd96dacaSLiam Girdwood int hda_dsp_core_power_down(struct snd_sof_dev *sdev, unsigned int core_mask); 498dd96dacaSLiam Girdwood bool hda_dsp_core_is_enabled(struct snd_sof_dev *sdev, 499dd96dacaSLiam Girdwood unsigned int core_mask); 500dd96dacaSLiam Girdwood int hda_dsp_core_reset_power_down(struct snd_sof_dev *sdev, 501dd96dacaSLiam Girdwood unsigned int core_mask); 502dd96dacaSLiam Girdwood void hda_dsp_ipc_int_enable(struct snd_sof_dev *sdev); 503dd96dacaSLiam Girdwood void hda_dsp_ipc_int_disable(struct snd_sof_dev *sdev); 504dd96dacaSLiam Girdwood 50562f8f766SKeyon Jie int hda_dsp_set_power_state(struct snd_sof_dev *sdev, 50661e285caSRanjani Sridharan const struct sof_dsp_power_state *target_state); 50762f8f766SKeyon Jie 50861e285caSRanjani Sridharan int hda_dsp_suspend(struct snd_sof_dev *sdev, u32 target_state); 509dd96dacaSLiam Girdwood int hda_dsp_resume(struct snd_sof_dev *sdev); 5101c38c922SFred Oh int hda_dsp_runtime_suspend(struct snd_sof_dev *sdev); 511dd96dacaSLiam Girdwood int hda_dsp_runtime_resume(struct snd_sof_dev *sdev); 51262fde977SKai Vehmanen int hda_dsp_runtime_idle(struct snd_sof_dev *sdev); 5137077a07aSRanjani Sridharan int hda_dsp_set_hw_params_upon_resume(struct snd_sof_dev *sdev); 514dd96dacaSLiam Girdwood void hda_dsp_dump_skl(struct snd_sof_dev *sdev, u32 flags); 515dd96dacaSLiam Girdwood void hda_dsp_dump(struct snd_sof_dev *sdev, u32 flags); 516f3da49f0SPan Xiuli void hda_ipc_dump(struct snd_sof_dev *sdev); 517f1fd9d0eSKai Vehmanen void hda_ipc_irq_dump(struct snd_sof_dev *sdev); 51863e51fd3SRanjani Sridharan void hda_dsp_d0i3_work(struct work_struct *work); 519dd96dacaSLiam Girdwood 520dd96dacaSLiam Girdwood /* 521dd96dacaSLiam Girdwood * DSP PCM Operations. 522dd96dacaSLiam Girdwood */ 52349d7948eSCezary Rojewski u32 hda_dsp_get_mult_div(struct snd_sof_dev *sdev, int rate); 52449d7948eSCezary Rojewski u32 hda_dsp_get_bits(struct snd_sof_dev *sdev, int sample_bits); 525dd96dacaSLiam Girdwood int hda_dsp_pcm_open(struct snd_sof_dev *sdev, 526dd96dacaSLiam Girdwood struct snd_pcm_substream *substream); 527dd96dacaSLiam Girdwood int hda_dsp_pcm_close(struct snd_sof_dev *sdev, 528dd96dacaSLiam Girdwood struct snd_pcm_substream *substream); 529dd96dacaSLiam Girdwood int hda_dsp_pcm_hw_params(struct snd_sof_dev *sdev, 530dd96dacaSLiam Girdwood struct snd_pcm_substream *substream, 531dd96dacaSLiam Girdwood struct snd_pcm_hw_params *params, 532dd96dacaSLiam Girdwood struct sof_ipc_stream_params *ipc_params); 53393146bc2SRanjani Sridharan int hda_dsp_stream_hw_free(struct snd_sof_dev *sdev, 53493146bc2SRanjani Sridharan struct snd_pcm_substream *substream); 535dd96dacaSLiam Girdwood int hda_dsp_pcm_trigger(struct snd_sof_dev *sdev, 536dd96dacaSLiam Girdwood struct snd_pcm_substream *substream, int cmd); 537dd96dacaSLiam Girdwood snd_pcm_uframes_t hda_dsp_pcm_pointer(struct snd_sof_dev *sdev, 538dd96dacaSLiam Girdwood struct snd_pcm_substream *substream); 539dd96dacaSLiam Girdwood 540dd96dacaSLiam Girdwood /* 541dd96dacaSLiam Girdwood * DSP Stream Operations. 542dd96dacaSLiam Girdwood */ 543dd96dacaSLiam Girdwood 544dd96dacaSLiam Girdwood int hda_dsp_stream_init(struct snd_sof_dev *sdev); 545dd96dacaSLiam Girdwood void hda_dsp_stream_free(struct snd_sof_dev *sdev); 546dd96dacaSLiam Girdwood int hda_dsp_stream_hw_params(struct snd_sof_dev *sdev, 547dd96dacaSLiam Girdwood struct hdac_ext_stream *stream, 548dd96dacaSLiam Girdwood struct snd_dma_buffer *dmab, 549dd96dacaSLiam Girdwood struct snd_pcm_hw_params *params); 550aca961f1SRanjani Sridharan int hda_dsp_iccmax_stream_hw_params(struct snd_sof_dev *sdev, struct hdac_ext_stream *stream, 551aca961f1SRanjani Sridharan struct snd_dma_buffer *dmab, 552aca961f1SRanjani Sridharan struct snd_pcm_hw_params *params); 553dd96dacaSLiam Girdwood int hda_dsp_stream_trigger(struct snd_sof_dev *sdev, 554dd96dacaSLiam Girdwood struct hdac_ext_stream *stream, int cmd); 555dd96dacaSLiam Girdwood irqreturn_t hda_dsp_stream_threaded_handler(int irq, void *context); 556dd96dacaSLiam Girdwood int hda_dsp_stream_setup_bdl(struct snd_sof_dev *sdev, 557dd96dacaSLiam Girdwood struct snd_dma_buffer *dmab, 558dd96dacaSLiam Girdwood struct hdac_stream *stream); 5597c11af9fSBard Liao bool hda_dsp_check_ipc_irq(struct snd_sof_dev *sdev); 5607c11af9fSBard Liao bool hda_dsp_check_stream_irq(struct snd_sof_dev *sdev); 561dd96dacaSLiam Girdwood 562dd96dacaSLiam Girdwood struct hdac_ext_stream * 563dd96dacaSLiam Girdwood hda_dsp_stream_get(struct snd_sof_dev *sdev, int direction); 564dd96dacaSLiam Girdwood int hda_dsp_stream_put(struct snd_sof_dev *sdev, int direction, int stream_tag); 565dd96dacaSLiam Girdwood int hda_dsp_stream_spib_config(struct snd_sof_dev *sdev, 566dd96dacaSLiam Girdwood struct hdac_ext_stream *stream, 567dd96dacaSLiam Girdwood int enable, u32 size); 568dd96dacaSLiam Girdwood 569dd96dacaSLiam Girdwood void hda_ipc_msg_data(struct snd_sof_dev *sdev, 570dd96dacaSLiam Girdwood struct snd_pcm_substream *substream, 571dd96dacaSLiam Girdwood void *p, size_t sz); 572dd96dacaSLiam Girdwood int hda_ipc_pcm_params(struct snd_sof_dev *sdev, 573dd96dacaSLiam Girdwood struct snd_pcm_substream *substream, 574dd96dacaSLiam Girdwood const struct sof_ipc_pcm_params_reply *reply); 575dd96dacaSLiam Girdwood 5764c414da9SCezary Rojewski #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_PROBES) 5774c414da9SCezary Rojewski /* 5784c414da9SCezary Rojewski * Probe Compress Operations. 5794c414da9SCezary Rojewski */ 5804c414da9SCezary Rojewski int hda_probe_compr_assign(struct snd_sof_dev *sdev, 5814c414da9SCezary Rojewski struct snd_compr_stream *cstream, 5824c414da9SCezary Rojewski struct snd_soc_dai *dai); 5834c414da9SCezary Rojewski int hda_probe_compr_free(struct snd_sof_dev *sdev, 5844c414da9SCezary Rojewski struct snd_compr_stream *cstream, 5854c414da9SCezary Rojewski struct snd_soc_dai *dai); 5864c414da9SCezary Rojewski int hda_probe_compr_set_params(struct snd_sof_dev *sdev, 5874c414da9SCezary Rojewski struct snd_compr_stream *cstream, 5884c414da9SCezary Rojewski struct snd_compr_params *params, 5894c414da9SCezary Rojewski struct snd_soc_dai *dai); 5904c414da9SCezary Rojewski int hda_probe_compr_trigger(struct snd_sof_dev *sdev, 5914c414da9SCezary Rojewski struct snd_compr_stream *cstream, int cmd, 5924c414da9SCezary Rojewski struct snd_soc_dai *dai); 5934c414da9SCezary Rojewski int hda_probe_compr_pointer(struct snd_sof_dev *sdev, 5944c414da9SCezary Rojewski struct snd_compr_stream *cstream, 5954c414da9SCezary Rojewski struct snd_compr_tstamp *tstamp, 5964c414da9SCezary Rojewski struct snd_soc_dai *dai); 5974c414da9SCezary Rojewski #endif 5984c414da9SCezary Rojewski 599dd96dacaSLiam Girdwood /* 600dd96dacaSLiam Girdwood * DSP IPC Operations. 601dd96dacaSLiam Girdwood */ 602dd96dacaSLiam Girdwood int hda_dsp_ipc_send_msg(struct snd_sof_dev *sdev, 603dd96dacaSLiam Girdwood struct snd_sof_ipc_msg *msg); 604dd96dacaSLiam Girdwood void hda_dsp_ipc_get_reply(struct snd_sof_dev *sdev); 6056eebd390SDaniel Baluta int hda_dsp_ipc_get_mailbox_offset(struct snd_sof_dev *sdev); 6066eebd390SDaniel Baluta int hda_dsp_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id); 6076eebd390SDaniel Baluta 608dd96dacaSLiam Girdwood irqreturn_t hda_dsp_ipc_irq_thread(int irq, void *context); 609dd96dacaSLiam Girdwood int hda_dsp_ipc_cmd_done(struct snd_sof_dev *sdev, int dir); 610dd96dacaSLiam Girdwood 611dd96dacaSLiam Girdwood /* 612dd96dacaSLiam Girdwood * DSP Code loader. 613dd96dacaSLiam Girdwood */ 614dd96dacaSLiam Girdwood int hda_dsp_cl_boot_firmware(struct snd_sof_dev *sdev); 615dd96dacaSLiam Girdwood int hda_dsp_cl_boot_firmware_skl(struct snd_sof_dev *sdev); 616dd96dacaSLiam Girdwood 617dd96dacaSLiam Girdwood /* pre and post fw run ops */ 618dd96dacaSLiam Girdwood int hda_dsp_pre_fw_run(struct snd_sof_dev *sdev); 619dd96dacaSLiam Girdwood int hda_dsp_post_fw_run(struct snd_sof_dev *sdev); 620dd96dacaSLiam Girdwood 621dd96dacaSLiam Girdwood /* 622dd96dacaSLiam Girdwood * HDA Controller Operations. 623dd96dacaSLiam Girdwood */ 624dd96dacaSLiam Girdwood int hda_dsp_ctrl_get_caps(struct snd_sof_dev *sdev); 625dd96dacaSLiam Girdwood void hda_dsp_ctrl_ppcap_enable(struct snd_sof_dev *sdev, bool enable); 626dd96dacaSLiam Girdwood void hda_dsp_ctrl_ppcap_int_enable(struct snd_sof_dev *sdev, bool enable); 627dd96dacaSLiam Girdwood int hda_dsp_ctrl_link_reset(struct snd_sof_dev *sdev, bool reset); 628dd96dacaSLiam Girdwood void hda_dsp_ctrl_misc_clock_gating(struct snd_sof_dev *sdev, bool enable); 629dd96dacaSLiam Girdwood int hda_dsp_ctrl_clock_power_gating(struct snd_sof_dev *sdev, bool enable); 630dd96dacaSLiam Girdwood int hda_dsp_ctrl_init_chip(struct snd_sof_dev *sdev, bool full_reset); 63113063a2cSZhu Yingjiang void hda_dsp_ctrl_stop_chip(struct snd_sof_dev *sdev); 632dd96dacaSLiam Girdwood /* 633dd96dacaSLiam Girdwood * HDA bus operations. 634dd96dacaSLiam Girdwood */ 635d4ff1b39STakashi Iwai void sof_hda_bus_init(struct hdac_bus *bus, struct device *dev); 636dd96dacaSLiam Girdwood 637dd96dacaSLiam Girdwood #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) 638dd96dacaSLiam Girdwood /* 639dd96dacaSLiam Girdwood * HDA Codec operations. 640dd96dacaSLiam Girdwood */ 64191dce767SKai Vehmanen void hda_codec_probe_bus(struct snd_sof_dev *sdev, 64280acdd4fSRanjani Sridharan bool hda_codec_use_common_hdmi); 643fd15f2f5SRander Wang void hda_codec_jack_wake_enable(struct snd_sof_dev *sdev); 644fd15f2f5SRander Wang void hda_codec_jack_check(struct snd_sof_dev *sdev); 645dd96dacaSLiam Girdwood 646dd96dacaSLiam Girdwood #endif /* CONFIG_SND_SOC_SOF_HDA */ 647dd96dacaSLiam Girdwood 648139c7febSKai Vehmanen #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) && \ 649139c7febSKai Vehmanen (IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI) || \ 650139c7febSKai Vehmanen IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) 651dd96dacaSLiam Girdwood 65223ee0903SKai Vehmanen void hda_codec_i915_display_power(struct snd_sof_dev *sdev, bool enable); 653dd96dacaSLiam Girdwood int hda_codec_i915_init(struct snd_sof_dev *sdev); 654dd96dacaSLiam Girdwood int hda_codec_i915_exit(struct snd_sof_dev *sdev); 655dd96dacaSLiam Girdwood 656dd96dacaSLiam Girdwood #else 657dd96dacaSLiam Girdwood 65823ee0903SKai Vehmanen static inline void hda_codec_i915_display_power(struct snd_sof_dev *sdev, 65923ee0903SKai Vehmanen bool enable) { } 660dd96dacaSLiam Girdwood static inline int hda_codec_i915_init(struct snd_sof_dev *sdev) { return 0; } 661dd96dacaSLiam Girdwood static inline int hda_codec_i915_exit(struct snd_sof_dev *sdev) { return 0; } 662dd96dacaSLiam Girdwood 663139c7febSKai Vehmanen #endif 664dd96dacaSLiam Girdwood 665dd96dacaSLiam Girdwood /* 666dd96dacaSLiam Girdwood * Trace Control. 667dd96dacaSLiam Girdwood */ 668dd96dacaSLiam Girdwood int hda_dsp_trace_init(struct snd_sof_dev *sdev, u32 *stream_tag); 669dd96dacaSLiam Girdwood int hda_dsp_trace_release(struct snd_sof_dev *sdev); 670dd96dacaSLiam Girdwood int hda_dsp_trace_trigger(struct snd_sof_dev *sdev, int cmd); 671dd96dacaSLiam Girdwood 67251dfed1eSPierre-Louis Bossart /* 67351dfed1eSPierre-Louis Bossart * SoundWire support 67451dfed1eSPierre-Louis Bossart */ 67551dfed1eSPierre-Louis Bossart #if IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE) 67651dfed1eSPierre-Louis Bossart 67751dfed1eSPierre-Louis Bossart int hda_sdw_startup(struct snd_sof_dev *sdev); 67851dfed1eSPierre-Louis Bossart void hda_sdw_int_enable(struct snd_sof_dev *sdev, bool enable); 679bbd19cdcSRander Wang void hda_sdw_process_wakeen(struct snd_sof_dev *sdev); 68051dfed1eSPierre-Louis Bossart 68151dfed1eSPierre-Louis Bossart #else 68251dfed1eSPierre-Louis Bossart 68351dfed1eSPierre-Louis Bossart static inline int hda_sdw_acpi_scan(struct snd_sof_dev *sdev) 68451dfed1eSPierre-Louis Bossart { 68551dfed1eSPierre-Louis Bossart return 0; 68651dfed1eSPierre-Louis Bossart } 68751dfed1eSPierre-Louis Bossart 68851dfed1eSPierre-Louis Bossart static inline int hda_sdw_probe(struct snd_sof_dev *sdev) 68951dfed1eSPierre-Louis Bossart { 69051dfed1eSPierre-Louis Bossart return 0; 69151dfed1eSPierre-Louis Bossart } 69251dfed1eSPierre-Louis Bossart 69351dfed1eSPierre-Louis Bossart static inline int hda_sdw_startup(struct snd_sof_dev *sdev) 69451dfed1eSPierre-Louis Bossart { 69551dfed1eSPierre-Louis Bossart return 0; 69651dfed1eSPierre-Louis Bossart } 69751dfed1eSPierre-Louis Bossart 69851dfed1eSPierre-Louis Bossart static inline int hda_sdw_exit(struct snd_sof_dev *sdev) 69951dfed1eSPierre-Louis Bossart { 70051dfed1eSPierre-Louis Bossart return 0; 70151dfed1eSPierre-Louis Bossart } 70251dfed1eSPierre-Louis Bossart 70351dfed1eSPierre-Louis Bossart static inline void hda_sdw_int_enable(struct snd_sof_dev *sdev, bool enable) 70451dfed1eSPierre-Louis Bossart { 70551dfed1eSPierre-Louis Bossart } 70651dfed1eSPierre-Louis Bossart 707722ba5f1SBard Liao static inline bool hda_dsp_check_sdw_irq(struct snd_sof_dev *sdev) 708722ba5f1SBard Liao { 709722ba5f1SBard Liao return false; 710722ba5f1SBard Liao } 711722ba5f1SBard Liao 712722ba5f1SBard Liao static inline irqreturn_t hda_dsp_sdw_thread(int irq, void *context) 713722ba5f1SBard Liao { 714722ba5f1SBard Liao return IRQ_HANDLED; 715722ba5f1SBard Liao } 716bbd19cdcSRander Wang 71790de3281SRander Wang static inline bool hda_sdw_check_wakeen_irq(struct snd_sof_dev *sdev) 71890de3281SRander Wang { 71990de3281SRander Wang return false; 72090de3281SRander Wang } 72190de3281SRander Wang 722bbd19cdcSRander Wang static inline void hda_sdw_process_wakeen(struct snd_sof_dev *sdev) 723bbd19cdcSRander Wang { 724bbd19cdcSRander Wang } 72551dfed1eSPierre-Louis Bossart #endif 72651dfed1eSPierre-Louis Bossart 727dd96dacaSLiam Girdwood /* common dai driver */ 728dd96dacaSLiam Girdwood extern struct snd_soc_dai_driver skl_dai[]; 729dd96dacaSLiam Girdwood 730dd96dacaSLiam Girdwood /* 731dd96dacaSLiam Girdwood * Platform Specific HW abstraction Ops. 732dd96dacaSLiam Girdwood */ 733dd96dacaSLiam Girdwood extern const struct snd_sof_dsp_ops sof_apl_ops; 734dd96dacaSLiam Girdwood extern const struct snd_sof_dsp_ops sof_cnl_ops; 735dd96dacaSLiam Girdwood 736dd96dacaSLiam Girdwood extern const struct sof_intel_dsp_desc apl_chip_info; 737dd96dacaSLiam Girdwood extern const struct sof_intel_dsp_desc cnl_chip_info; 738dd96dacaSLiam Girdwood extern const struct sof_intel_dsp_desc skl_chip_info; 739630be964SZhu Yingjiang extern const struct sof_intel_dsp_desc icl_chip_info; 7401205c81eSPan Xiuli extern const struct sof_intel_dsp_desc tgl_chip_info; 74161732690SPan Xiuli extern const struct sof_intel_dsp_desc ehl_chip_info; 7426fd99035SPan Xiuli extern const struct sof_intel_dsp_desc jsl_chip_info; 743dd96dacaSLiam Girdwood 744285880a2SDaniel Baluta /* machine driver select */ 745285880a2SDaniel Baluta void hda_machine_select(struct snd_sof_dev *sdev); 746285880a2SDaniel Baluta void hda_set_mach_params(const struct snd_soc_acpi_mach *mach, 747285880a2SDaniel Baluta struct device *dev); 748285880a2SDaniel Baluta 749dd96dacaSLiam Girdwood #endif 750