1dd96dacaSLiam Girdwood /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */ 2dd96dacaSLiam Girdwood /* 3dd96dacaSLiam Girdwood * This file is provided under a dual BSD/GPLv2 license. When using or 4dd96dacaSLiam Girdwood * redistributing this file, you may do so under either license. 5dd96dacaSLiam Girdwood * 6dd96dacaSLiam Girdwood * Copyright(c) 2017 Intel Corporation. All rights reserved. 7dd96dacaSLiam Girdwood * 8dd96dacaSLiam Girdwood * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com> 9dd96dacaSLiam Girdwood */ 10dd96dacaSLiam Girdwood 11dd96dacaSLiam Girdwood #ifndef __SOF_INTEL_HDA_H 12dd96dacaSLiam Girdwood #define __SOF_INTEL_HDA_H 13dd96dacaSLiam Girdwood 14dd96dacaSLiam Girdwood #include <sound/hda_codec.h> 15dd96dacaSLiam Girdwood #include <sound/hdaudio_ext.h> 16dd96dacaSLiam Girdwood #include "shim.h" 17dd96dacaSLiam Girdwood 18dd96dacaSLiam Girdwood /* PCI registers */ 19dd96dacaSLiam Girdwood #define PCI_TCSEL 0x44 20dd96dacaSLiam Girdwood #define PCI_PGCTL PCI_TCSEL 21dd96dacaSLiam Girdwood #define PCI_CGCTL 0x48 22dd96dacaSLiam Girdwood 23dd96dacaSLiam Girdwood /* PCI_PGCTL bits */ 24dd96dacaSLiam Girdwood #define PCI_PGCTL_ADSPPGD BIT(2) 25dd96dacaSLiam Girdwood #define PCI_PGCTL_LSRMD_MASK BIT(4) 26dd96dacaSLiam Girdwood 27dd96dacaSLiam Girdwood /* PCI_CGCTL bits */ 28dd96dacaSLiam Girdwood #define PCI_CGCTL_MISCBDCGE_MASK BIT(6) 29dd96dacaSLiam Girdwood #define PCI_CGCTL_ADSPDCGE BIT(1) 30dd96dacaSLiam Girdwood 31dd96dacaSLiam Girdwood /* Legacy HDA registers and bits used - widths are variable */ 32dd96dacaSLiam Girdwood #define SOF_HDA_GCAP 0x0 33dd96dacaSLiam Girdwood #define SOF_HDA_GCTL 0x8 34dd96dacaSLiam Girdwood /* accept unsol. response enable */ 35dd96dacaSLiam Girdwood #define SOF_HDA_GCTL_UNSOL BIT(8) 36dd96dacaSLiam Girdwood #define SOF_HDA_LLCH 0x14 37dd96dacaSLiam Girdwood #define SOF_HDA_INTCTL 0x20 38dd96dacaSLiam Girdwood #define SOF_HDA_INTSTS 0x24 39dd96dacaSLiam Girdwood #define SOF_HDA_WAKESTS 0x0E 40dd96dacaSLiam Girdwood #define SOF_HDA_WAKESTS_INT_MASK ((1 << 8) - 1) 41dd96dacaSLiam Girdwood #define SOF_HDA_RIRBSTS 0x5d 42dd96dacaSLiam Girdwood 43dd96dacaSLiam Girdwood /* SOF_HDA_GCTL register bist */ 44dd96dacaSLiam Girdwood #define SOF_HDA_GCTL_RESET BIT(0) 45dd96dacaSLiam Girdwood 467c11af9fSBard Liao /* SOF_HDA_INCTL regs */ 47dd96dacaSLiam Girdwood #define SOF_HDA_INT_GLOBAL_EN BIT(31) 48dd96dacaSLiam Girdwood #define SOF_HDA_INT_CTRL_EN BIT(30) 49dd96dacaSLiam Girdwood #define SOF_HDA_INT_ALL_STREAM 0xff 50dd96dacaSLiam Girdwood 517c11af9fSBard Liao /* SOF_HDA_INTSTS regs */ 527c11af9fSBard Liao #define SOF_HDA_INTSTS_GIS BIT(31) 537c11af9fSBard Liao 54dd96dacaSLiam Girdwood #define SOF_HDA_MAX_CAPS 10 55dd96dacaSLiam Girdwood #define SOF_HDA_CAP_ID_OFF 16 56dd96dacaSLiam Girdwood #define SOF_HDA_CAP_ID_MASK GENMASK(SOF_HDA_CAP_ID_OFF + 11,\ 57dd96dacaSLiam Girdwood SOF_HDA_CAP_ID_OFF) 58dd96dacaSLiam Girdwood #define SOF_HDA_CAP_NEXT_MASK 0xFFFF 59dd96dacaSLiam Girdwood 60dd96dacaSLiam Girdwood #define SOF_HDA_GTS_CAP_ID 0x1 61dd96dacaSLiam Girdwood #define SOF_HDA_ML_CAP_ID 0x2 62dd96dacaSLiam Girdwood 63dd96dacaSLiam Girdwood #define SOF_HDA_PP_CAP_ID 0x3 64dd96dacaSLiam Girdwood #define SOF_HDA_REG_PP_PPCH 0x10 65dd96dacaSLiam Girdwood #define SOF_HDA_REG_PP_PPCTL 0x04 66f1fd9d0eSKai Vehmanen #define SOF_HDA_REG_PP_PPSTS 0x08 67dd96dacaSLiam Girdwood #define SOF_HDA_PPCTL_PIE BIT(31) 68dd96dacaSLiam Girdwood #define SOF_HDA_PPCTL_GPROCEN BIT(30) 69dd96dacaSLiam Girdwood 7062f8f766SKeyon Jie /*Vendor Specific Registers*/ 7162f8f766SKeyon Jie #define SOF_HDA_VS_D0I3C 0x104A 7262f8f766SKeyon Jie 7362f8f766SKeyon Jie /* D0I3C Register fields */ 7462f8f766SKeyon Jie #define SOF_HDA_VS_D0I3C_CIP BIT(0) /* Command-In-Progress */ 7562f8f766SKeyon Jie #define SOF_HDA_VS_D0I3C_I3 BIT(2) /* D0i3 enable bit */ 7662f8f766SKeyon Jie 77dd96dacaSLiam Girdwood /* DPIB entry size: 8 Bytes = 2 DWords */ 78dd96dacaSLiam Girdwood #define SOF_HDA_DPIB_ENTRY_SIZE 0x8 79dd96dacaSLiam Girdwood 80dd96dacaSLiam Girdwood #define SOF_HDA_SPIB_CAP_ID 0x4 81dd96dacaSLiam Girdwood #define SOF_HDA_DRSM_CAP_ID 0x5 82dd96dacaSLiam Girdwood 83dd96dacaSLiam Girdwood #define SOF_HDA_SPIB_BASE 0x08 84dd96dacaSLiam Girdwood #define SOF_HDA_SPIB_INTERVAL 0x08 85dd96dacaSLiam Girdwood #define SOF_HDA_SPIB_SPIB 0x00 86dd96dacaSLiam Girdwood #define SOF_HDA_SPIB_MAXFIFO 0x04 87dd96dacaSLiam Girdwood 88dd96dacaSLiam Girdwood #define SOF_HDA_PPHC_BASE 0x10 89dd96dacaSLiam Girdwood #define SOF_HDA_PPHC_INTERVAL 0x10 90dd96dacaSLiam Girdwood 91dd96dacaSLiam Girdwood #define SOF_HDA_PPLC_BASE 0x10 92dd96dacaSLiam Girdwood #define SOF_HDA_PPLC_MULTI 0x10 93dd96dacaSLiam Girdwood #define SOF_HDA_PPLC_INTERVAL 0x10 94dd96dacaSLiam Girdwood 95dd96dacaSLiam Girdwood #define SOF_HDA_DRSM_BASE 0x08 96dd96dacaSLiam Girdwood #define SOF_HDA_DRSM_INTERVAL 0x08 97dd96dacaSLiam Girdwood 98dd96dacaSLiam Girdwood /* Descriptor error interrupt */ 99dd96dacaSLiam Girdwood #define SOF_HDA_CL_DMA_SD_INT_DESC_ERR 0x10 100dd96dacaSLiam Girdwood 101dd96dacaSLiam Girdwood /* FIFO error interrupt */ 102dd96dacaSLiam Girdwood #define SOF_HDA_CL_DMA_SD_INT_FIFO_ERR 0x08 103dd96dacaSLiam Girdwood 104dd96dacaSLiam Girdwood /* Buffer completion interrupt */ 105dd96dacaSLiam Girdwood #define SOF_HDA_CL_DMA_SD_INT_COMPLETE 0x04 106dd96dacaSLiam Girdwood 107dd96dacaSLiam Girdwood #define SOF_HDA_CL_DMA_SD_INT_MASK \ 108dd96dacaSLiam Girdwood (SOF_HDA_CL_DMA_SD_INT_DESC_ERR | \ 109dd96dacaSLiam Girdwood SOF_HDA_CL_DMA_SD_INT_FIFO_ERR | \ 110dd96dacaSLiam Girdwood SOF_HDA_CL_DMA_SD_INT_COMPLETE) 111dd96dacaSLiam Girdwood #define SOF_HDA_SD_CTL_DMA_START 0x02 /* Stream DMA start bit */ 112dd96dacaSLiam Girdwood 113dd96dacaSLiam Girdwood /* Intel HD Audio Code Loader DMA Registers */ 114dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_LOADER_BASE 0x80 115dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_DPLBASE 0x70 116dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_DPUBASE 0x74 117dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_DPLBASE_ENABLE 0x01 118dd96dacaSLiam Girdwood 119dd96dacaSLiam Girdwood /* Stream Registers */ 120dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SD_CTL 0x00 121dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SD_STS 0x03 122dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SD_LPIB 0x04 123dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SD_CBL 0x08 124dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SD_LVI 0x0C 125dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SD_FIFOW 0x0E 126dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SD_FIFOSIZE 0x10 127dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SD_FORMAT 0x12 128dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SD_FIFOL 0x14 129dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SD_BDLPL 0x18 130dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SD_BDLPU 0x1C 131dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_SD_ENTRY_SIZE 0x20 132dd96dacaSLiam Girdwood 133dd96dacaSLiam Girdwood /* CL: Software Position Based FIFO Capability Registers */ 134dd96dacaSLiam Girdwood #define SOF_DSP_REG_CL_SPBFIFO \ 135dd96dacaSLiam Girdwood (SOF_HDA_ADSP_LOADER_BASE + 0x20) 136dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCH 0x0 137dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCCTL 0x4 138dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPIB 0x8 139dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SPBFIFO_MAXFIFOS 0xc 140dd96dacaSLiam Girdwood 141dd96dacaSLiam Girdwood /* Stream Number */ 142dd96dacaSLiam Girdwood #define SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT 20 143dd96dacaSLiam Girdwood #define SOF_HDA_CL_SD_CTL_STREAM_TAG_MASK \ 144dd96dacaSLiam Girdwood GENMASK(SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT + 3,\ 145dd96dacaSLiam Girdwood SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT) 146dd96dacaSLiam Girdwood 147dd96dacaSLiam Girdwood #define HDA_DSP_HDA_BAR 0 148dd96dacaSLiam Girdwood #define HDA_DSP_PP_BAR 1 149dd96dacaSLiam Girdwood #define HDA_DSP_SPIB_BAR 2 150dd96dacaSLiam Girdwood #define HDA_DSP_DRSM_BAR 3 151dd96dacaSLiam Girdwood #define HDA_DSP_BAR 4 152dd96dacaSLiam Girdwood 153dd96dacaSLiam Girdwood #define SRAM_WINDOW_OFFSET(x) (0x80000 + (x) * 0x20000) 154dd96dacaSLiam Girdwood 155dd96dacaSLiam Girdwood #define HDA_DSP_MBOX_OFFSET SRAM_WINDOW_OFFSET(0) 156dd96dacaSLiam Girdwood 157dd96dacaSLiam Girdwood #define HDA_DSP_PANIC_OFFSET(x) \ 158dd96dacaSLiam Girdwood (((x) & 0xFFFFFF) + HDA_DSP_MBOX_OFFSET) 159dd96dacaSLiam Girdwood 160dd96dacaSLiam Girdwood /* SRAM window 0 FW "registers" */ 161dd96dacaSLiam Girdwood #define HDA_DSP_SRAM_REG_ROM_STATUS (HDA_DSP_MBOX_OFFSET + 0x0) 162dd96dacaSLiam Girdwood #define HDA_DSP_SRAM_REG_ROM_ERROR (HDA_DSP_MBOX_OFFSET + 0x4) 163dd96dacaSLiam Girdwood /* FW and ROM share offset 4 */ 164dd96dacaSLiam Girdwood #define HDA_DSP_SRAM_REG_FW_STATUS (HDA_DSP_MBOX_OFFSET + 0x4) 165dd96dacaSLiam Girdwood #define HDA_DSP_SRAM_REG_FW_TRACEP (HDA_DSP_MBOX_OFFSET + 0x8) 166dd96dacaSLiam Girdwood #define HDA_DSP_SRAM_REG_FW_END (HDA_DSP_MBOX_OFFSET + 0xc) 167dd96dacaSLiam Girdwood 168dd96dacaSLiam Girdwood #define HDA_DSP_MBOX_UPLINK_OFFSET 0x81000 169dd96dacaSLiam Girdwood 170dd96dacaSLiam Girdwood #define HDA_DSP_STREAM_RESET_TIMEOUT 300 1717bcaf0f2SZhu Yingjiang /* 1727bcaf0f2SZhu Yingjiang * Timeout in us, for setting the stream RUN bit, during 1737bcaf0f2SZhu Yingjiang * start/stop the stream. The timeout expires if new RUN bit 1747bcaf0f2SZhu Yingjiang * value cannot be read back within the specified time. 1757bcaf0f2SZhu Yingjiang */ 1767bcaf0f2SZhu Yingjiang #define HDA_DSP_STREAM_RUN_TIMEOUT 300 177dd96dacaSLiam Girdwood #define HDA_DSP_CL_TRIGGER_TIMEOUT 300 178dd96dacaSLiam Girdwood 179dd96dacaSLiam Girdwood #define HDA_DSP_SPIB_ENABLE 1 180dd96dacaSLiam Girdwood #define HDA_DSP_SPIB_DISABLE 0 181dd96dacaSLiam Girdwood 182dd96dacaSLiam Girdwood #define SOF_HDA_MAX_BUFFER_SIZE (32 * PAGE_SIZE) 183dd96dacaSLiam Girdwood 184dd96dacaSLiam Girdwood #define HDA_DSP_STACK_DUMP_SIZE 32 185dd96dacaSLiam Girdwood 186dd96dacaSLiam Girdwood /* ROM status/error values */ 187184fdfcaSKeyon Jie #define HDA_DSP_ROM_STS_MASK GENMASK(23, 0) 188dd96dacaSLiam Girdwood #define HDA_DSP_ROM_INIT 0x1 189dd96dacaSLiam Girdwood #define HDA_DSP_ROM_FW_MANIFEST_LOADED 0x3 190dd96dacaSLiam Girdwood #define HDA_DSP_ROM_FW_FW_LOADED 0x4 191dd96dacaSLiam Girdwood #define HDA_DSP_ROM_FW_ENTERED 0x5 192dd96dacaSLiam Girdwood #define HDA_DSP_ROM_RFW_START 0xf 193dd96dacaSLiam Girdwood #define HDA_DSP_ROM_CSE_ERROR 40 194dd96dacaSLiam Girdwood #define HDA_DSP_ROM_CSE_WRONG_RESPONSE 41 195dd96dacaSLiam Girdwood #define HDA_DSP_ROM_IMR_TO_SMALL 42 196dd96dacaSLiam Girdwood #define HDA_DSP_ROM_BASE_FW_NOT_FOUND 43 197dd96dacaSLiam Girdwood #define HDA_DSP_ROM_CSE_VALIDATION_FAILED 44 198dd96dacaSLiam Girdwood #define HDA_DSP_ROM_IPC_FATAL_ERROR 45 199dd96dacaSLiam Girdwood #define HDA_DSP_ROM_L2_CACHE_ERROR 46 200dd96dacaSLiam Girdwood #define HDA_DSP_ROM_LOAD_OFFSET_TO_SMALL 47 201dd96dacaSLiam Girdwood #define HDA_DSP_ROM_API_PTR_INVALID 50 202dd96dacaSLiam Girdwood #define HDA_DSP_ROM_BASEFW_INCOMPAT 51 203dd96dacaSLiam Girdwood #define HDA_DSP_ROM_UNHANDLED_INTERRUPT 0xBEE00000 204dd96dacaSLiam Girdwood #define HDA_DSP_ROM_MEMORY_HOLE_ECC 0xECC00000 205dd96dacaSLiam Girdwood #define HDA_DSP_ROM_KERNEL_EXCEPTION 0xCAFE0000 206dd96dacaSLiam Girdwood #define HDA_DSP_ROM_USER_EXCEPTION 0xBEEF0000 207dd96dacaSLiam Girdwood #define HDA_DSP_ROM_UNEXPECTED_RESET 0xDECAF000 208dd96dacaSLiam Girdwood #define HDA_DSP_ROM_NULL_FW_ENTRY 0x4c4c4e55 209dd96dacaSLiam Girdwood #define HDA_DSP_IPC_PURGE_FW 0x01004000 210dd96dacaSLiam Girdwood 211dd96dacaSLiam Girdwood /* various timeout values */ 212dd96dacaSLiam Girdwood #define HDA_DSP_PU_TIMEOUT 50 213dd96dacaSLiam Girdwood #define HDA_DSP_PD_TIMEOUT 50 214dd96dacaSLiam Girdwood #define HDA_DSP_RESET_TIMEOUT_US 50000 215dd96dacaSLiam Girdwood #define HDA_DSP_BASEFW_TIMEOUT_US 3000000 216dd96dacaSLiam Girdwood #define HDA_DSP_INIT_TIMEOUT_US 500000 217dd96dacaSLiam Girdwood #define HDA_DSP_CTRL_RESET_TIMEOUT 100 218dd96dacaSLiam Girdwood #define HDA_DSP_WAIT_TIMEOUT 500 /* 500 msec */ 219dd96dacaSLiam Girdwood #define HDA_DSP_REG_POLL_INTERVAL_US 500 /* 0.5 msec */ 22092f4beb7SKeyon Jie #define HDA_DSP_REG_POLL_RETRY_COUNT 50 221dd96dacaSLiam Girdwood 222dd96dacaSLiam Girdwood #define HDA_DSP_ADSPIC_IPC 1 223dd96dacaSLiam Girdwood #define HDA_DSP_ADSPIS_IPC 1 224dd96dacaSLiam Girdwood 225dd96dacaSLiam Girdwood /* Intel HD Audio General DSP Registers */ 226dd96dacaSLiam Girdwood #define HDA_DSP_GEN_BASE 0x0 227dd96dacaSLiam Girdwood #define HDA_DSP_REG_ADSPCS (HDA_DSP_GEN_BASE + 0x04) 228dd96dacaSLiam Girdwood #define HDA_DSP_REG_ADSPIC (HDA_DSP_GEN_BASE + 0x08) 229dd96dacaSLiam Girdwood #define HDA_DSP_REG_ADSPIS (HDA_DSP_GEN_BASE + 0x0C) 230dd96dacaSLiam Girdwood #define HDA_DSP_REG_ADSPIC2 (HDA_DSP_GEN_BASE + 0x10) 231dd96dacaSLiam Girdwood #define HDA_DSP_REG_ADSPIS2 (HDA_DSP_GEN_BASE + 0x14) 232dd96dacaSLiam Girdwood 233dd96dacaSLiam Girdwood /* Intel HD Audio Inter-Processor Communication Registers */ 234dd96dacaSLiam Girdwood #define HDA_DSP_IPC_BASE 0x40 235dd96dacaSLiam Girdwood #define HDA_DSP_REG_HIPCT (HDA_DSP_IPC_BASE + 0x00) 236dd96dacaSLiam Girdwood #define HDA_DSP_REG_HIPCTE (HDA_DSP_IPC_BASE + 0x04) 237dd96dacaSLiam Girdwood #define HDA_DSP_REG_HIPCI (HDA_DSP_IPC_BASE + 0x08) 238dd96dacaSLiam Girdwood #define HDA_DSP_REG_HIPCIE (HDA_DSP_IPC_BASE + 0x0C) 239dd96dacaSLiam Girdwood #define HDA_DSP_REG_HIPCCTL (HDA_DSP_IPC_BASE + 0x10) 240dd96dacaSLiam Girdwood 24143b2ab90SRanjani Sridharan /* Intel Vendor Specific Registers */ 24243b2ab90SRanjani Sridharan #define HDA_VS_INTEL_EM2 0x1030 24343b2ab90SRanjani Sridharan #define HDA_VS_INTEL_EM2_L1SEN BIT(13) 24443b2ab90SRanjani Sridharan 245dd96dacaSLiam Girdwood /* HIPCI */ 246dd96dacaSLiam Girdwood #define HDA_DSP_REG_HIPCI_BUSY BIT(31) 247dd96dacaSLiam Girdwood #define HDA_DSP_REG_HIPCI_MSG_MASK 0x7FFFFFFF 248dd96dacaSLiam Girdwood 249dd96dacaSLiam Girdwood /* HIPCIE */ 250dd96dacaSLiam Girdwood #define HDA_DSP_REG_HIPCIE_DONE BIT(30) 251dd96dacaSLiam Girdwood #define HDA_DSP_REG_HIPCIE_MSG_MASK 0x3FFFFFFF 252dd96dacaSLiam Girdwood 253dd96dacaSLiam Girdwood /* HIPCCTL */ 254dd96dacaSLiam Girdwood #define HDA_DSP_REG_HIPCCTL_DONE BIT(1) 255dd96dacaSLiam Girdwood #define HDA_DSP_REG_HIPCCTL_BUSY BIT(0) 256dd96dacaSLiam Girdwood 257dd96dacaSLiam Girdwood /* HIPCT */ 258dd96dacaSLiam Girdwood #define HDA_DSP_REG_HIPCT_BUSY BIT(31) 259dd96dacaSLiam Girdwood #define HDA_DSP_REG_HIPCT_MSG_MASK 0x7FFFFFFF 260dd96dacaSLiam Girdwood 261dd96dacaSLiam Girdwood /* HIPCTE */ 262dd96dacaSLiam Girdwood #define HDA_DSP_REG_HIPCTE_MSG_MASK 0x3FFFFFFF 263dd96dacaSLiam Girdwood 264dd96dacaSLiam Girdwood #define HDA_DSP_ADSPIC_CL_DMA 0x2 265dd96dacaSLiam Girdwood #define HDA_DSP_ADSPIS_CL_DMA 0x2 266dd96dacaSLiam Girdwood 267dd96dacaSLiam Girdwood /* Delay before scheduling D0i3 entry */ 268dd96dacaSLiam Girdwood #define BXT_D0I3_DELAY 5000 269dd96dacaSLiam Girdwood 270dd96dacaSLiam Girdwood #define FW_CL_STREAM_NUMBER 0x1 271dd96dacaSLiam Girdwood 272dd96dacaSLiam Girdwood /* ADSPCS - Audio DSP Control & Status */ 273dd96dacaSLiam Girdwood 274dd96dacaSLiam Girdwood /* 275dd96dacaSLiam Girdwood * Core Reset - asserted high 276dd96dacaSLiam Girdwood * CRST Mask for a given core mask pattern, cm 277dd96dacaSLiam Girdwood */ 278dd96dacaSLiam Girdwood #define HDA_DSP_ADSPCS_CRST_SHIFT 0 279dd96dacaSLiam Girdwood #define HDA_DSP_ADSPCS_CRST_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CRST_SHIFT) 280dd96dacaSLiam Girdwood 281dd96dacaSLiam Girdwood /* 282dd96dacaSLiam Girdwood * Core run/stall - when set to '1' core is stalled 283dd96dacaSLiam Girdwood * CSTALL Mask for a given core mask pattern, cm 284dd96dacaSLiam Girdwood */ 285dd96dacaSLiam Girdwood #define HDA_DSP_ADSPCS_CSTALL_SHIFT 8 286dd96dacaSLiam Girdwood #define HDA_DSP_ADSPCS_CSTALL_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CSTALL_SHIFT) 287dd96dacaSLiam Girdwood 288dd96dacaSLiam Girdwood /* 289dd96dacaSLiam Girdwood * Set Power Active - when set to '1' turn cores on 290dd96dacaSLiam Girdwood * SPA Mask for a given core mask pattern, cm 291dd96dacaSLiam Girdwood */ 292dd96dacaSLiam Girdwood #define HDA_DSP_ADSPCS_SPA_SHIFT 16 293dd96dacaSLiam Girdwood #define HDA_DSP_ADSPCS_SPA_MASK(cm) ((cm) << HDA_DSP_ADSPCS_SPA_SHIFT) 294dd96dacaSLiam Girdwood 295dd96dacaSLiam Girdwood /* 296dd96dacaSLiam Girdwood * Current Power Active - power status of cores, set by hardware 297dd96dacaSLiam Girdwood * CPA Mask for a given core mask pattern, cm 298dd96dacaSLiam Girdwood */ 299dd96dacaSLiam Girdwood #define HDA_DSP_ADSPCS_CPA_SHIFT 24 300dd96dacaSLiam Girdwood #define HDA_DSP_ADSPCS_CPA_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CPA_SHIFT) 301dd96dacaSLiam Girdwood 302dd96dacaSLiam Girdwood /* Mask for a given core index, c = 0.. number of supported cores - 1 */ 303dd96dacaSLiam Girdwood #define HDA_DSP_CORE_MASK(c) BIT(c) 304dd96dacaSLiam Girdwood 305dd96dacaSLiam Girdwood /* 306dd96dacaSLiam Girdwood * Mask for a given number of cores 307dd96dacaSLiam Girdwood * nc = number of supported cores 308dd96dacaSLiam Girdwood */ 309dd96dacaSLiam Girdwood #define SOF_DSP_CORES_MASK(nc) GENMASK(((nc) - 1), 0) 310dd96dacaSLiam Girdwood 311dd96dacaSLiam Girdwood /* Intel HD Audio Inter-Processor Communication Registers for Cannonlake*/ 312dd96dacaSLiam Girdwood #define CNL_DSP_IPC_BASE 0xc0 313dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCTDR (CNL_DSP_IPC_BASE + 0x00) 314dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCTDA (CNL_DSP_IPC_BASE + 0x04) 315dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCTDD (CNL_DSP_IPC_BASE + 0x08) 316dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCIDR (CNL_DSP_IPC_BASE + 0x10) 317dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCIDA (CNL_DSP_IPC_BASE + 0x14) 3180267de58SKeyon Jie #define CNL_DSP_REG_HIPCIDD (CNL_DSP_IPC_BASE + 0x18) 319dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCCTL (CNL_DSP_IPC_BASE + 0x28) 320dd96dacaSLiam Girdwood 321dd96dacaSLiam Girdwood /* HIPCI */ 322dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCIDR_BUSY BIT(31) 323dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCIDR_MSG_MASK 0x7FFFFFFF 324dd96dacaSLiam Girdwood 325dd96dacaSLiam Girdwood /* HIPCIE */ 326dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCIDA_DONE BIT(31) 327dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCIDA_MSG_MASK 0x7FFFFFFF 328dd96dacaSLiam Girdwood 329dd96dacaSLiam Girdwood /* HIPCCTL */ 330dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCCTL_DONE BIT(1) 331dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCCTL_BUSY BIT(0) 332dd96dacaSLiam Girdwood 333dd96dacaSLiam Girdwood /* HIPCT */ 334dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCTDR_BUSY BIT(31) 335dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCTDR_MSG_MASK 0x7FFFFFFF 336dd96dacaSLiam Girdwood 337dd96dacaSLiam Girdwood /* HIPCTDA */ 338dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCTDA_DONE BIT(31) 339dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCTDA_MSG_MASK 0x7FFFFFFF 340dd96dacaSLiam Girdwood 341dd96dacaSLiam Girdwood /* HIPCTDD */ 342dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCTDD_MSG_MASK 0x7FFFFFFF 343dd96dacaSLiam Girdwood 344dd96dacaSLiam Girdwood /* BDL */ 345dd96dacaSLiam Girdwood #define HDA_DSP_BDL_SIZE 4096 346dd96dacaSLiam Girdwood #define HDA_DSP_MAX_BDL_ENTRIES \ 347dd96dacaSLiam Girdwood (HDA_DSP_BDL_SIZE / sizeof(struct sof_intel_dsp_bdl)) 348dd96dacaSLiam Girdwood 349dd96dacaSLiam Girdwood /* Number of DAIs */ 350dd96dacaSLiam Girdwood #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) 351dd96dacaSLiam Girdwood #define SOF_SKL_NUM_DAIS 14 352dd96dacaSLiam Girdwood #else 353dd96dacaSLiam Girdwood #define SOF_SKL_NUM_DAIS 8 354dd96dacaSLiam Girdwood #endif 355dd96dacaSLiam Girdwood 356dd96dacaSLiam Girdwood /* Intel HD Audio SRAM Window 0*/ 357dd96dacaSLiam Girdwood #define HDA_ADSP_SRAM0_BASE_SKL 0x8000 358dd96dacaSLiam Girdwood 359dd96dacaSLiam Girdwood /* Firmware status window */ 360dd96dacaSLiam Girdwood #define HDA_ADSP_FW_STATUS_SKL HDA_ADSP_SRAM0_BASE_SKL 361dd96dacaSLiam Girdwood #define HDA_ADSP_ERROR_CODE_SKL (HDA_ADSP_FW_STATUS_SKL + 0x4) 362dd96dacaSLiam Girdwood 363df7e0de5SZhu Yingjiang /* Host Device Memory Space */ 364df7e0de5SZhu Yingjiang #define APL_SSP_BASE_OFFSET 0x2000 365df7e0de5SZhu Yingjiang #define CNL_SSP_BASE_OFFSET 0x10000 366df7e0de5SZhu Yingjiang 367df7e0de5SZhu Yingjiang /* Host Device Memory Size of a Single SSP */ 368df7e0de5SZhu Yingjiang #define SSP_DEV_MEM_SIZE 0x1000 369df7e0de5SZhu Yingjiang 370b095fe47SZhu Yingjiang /* SSP Count of the Platform */ 371b095fe47SZhu Yingjiang #define APL_SSP_COUNT 6 372b095fe47SZhu Yingjiang #define CNL_SSP_COUNT 3 373ec836daaSZhu Yingjiang #define ICL_SSP_COUNT 6 374b095fe47SZhu Yingjiang 37574ed4097SZhu Yingjiang /* SSP Registers */ 37674ed4097SZhu Yingjiang #define SSP_SSC1_OFFSET 0x4 37774ed4097SZhu Yingjiang #define SSP_SET_SCLK_SLAVE BIT(25) 37874ed4097SZhu Yingjiang #define SSP_SET_SFRM_SLAVE BIT(24) 37974ed4097SZhu Yingjiang #define SSP_SET_SLAVE (SSP_SET_SCLK_SLAVE | SSP_SET_SFRM_SLAVE) 38074ed4097SZhu Yingjiang 381dd96dacaSLiam Girdwood #define HDA_IDISP_CODEC(x) ((x) & BIT(2)) 382dd96dacaSLiam Girdwood 383dd96dacaSLiam Girdwood struct sof_intel_dsp_bdl { 384dd96dacaSLiam Girdwood __le32 addr_l; 385dd96dacaSLiam Girdwood __le32 addr_h; 386dd96dacaSLiam Girdwood __le32 size; 387dd96dacaSLiam Girdwood __le32 ioc; 388dd96dacaSLiam Girdwood } __attribute((packed)); 389dd96dacaSLiam Girdwood 390dd96dacaSLiam Girdwood #define SOF_HDA_PLAYBACK_STREAMS 16 391dd96dacaSLiam Girdwood #define SOF_HDA_CAPTURE_STREAMS 16 392dd96dacaSLiam Girdwood #define SOF_HDA_PLAYBACK 0 393dd96dacaSLiam Girdwood #define SOF_HDA_CAPTURE 1 394dd96dacaSLiam Girdwood 395dd96dacaSLiam Girdwood /* represents DSP HDA controller frontend - i.e. host facing control */ 396dd96dacaSLiam Girdwood struct sof_intel_hda_dev { 397dd96dacaSLiam Girdwood 398dd96dacaSLiam Girdwood struct hda_bus hbus; 399dd96dacaSLiam Girdwood 400dd96dacaSLiam Girdwood /* hw config */ 401dd96dacaSLiam Girdwood const struct sof_intel_dsp_desc *desc; 402dd96dacaSLiam Girdwood 403dd96dacaSLiam Girdwood /* trace */ 404dd96dacaSLiam Girdwood struct hdac_ext_stream *dtrace_stream; 405dd96dacaSLiam Girdwood 406dd96dacaSLiam Girdwood /* if position update IPC needed */ 407dd96dacaSLiam Girdwood u32 no_ipc_position; 408dd96dacaSLiam Girdwood 409e8e55dbeSKeyon Jie /* the maximum number of streams (playback + capture) supported */ 410e8e55dbeSKeyon Jie u32 stream_max; 411e8e55dbeSKeyon Jie 41216299326SKeyon Jie /* PM related */ 41316299326SKeyon Jie bool l1_support_changed;/* during suspend, is L1SEN changed or not */ 41416299326SKeyon Jie 415dd96dacaSLiam Girdwood /* DMIC device */ 416dd96dacaSLiam Girdwood struct platform_device *dmic_dev; 417dd96dacaSLiam Girdwood }; 418dd96dacaSLiam Girdwood 419dd96dacaSLiam Girdwood static inline struct hdac_bus *sof_to_bus(struct snd_sof_dev *s) 420dd96dacaSLiam Girdwood { 421dd96dacaSLiam Girdwood struct sof_intel_hda_dev *hda = s->pdata->hw_pdata; 422dd96dacaSLiam Girdwood 423dd96dacaSLiam Girdwood return &hda->hbus.core; 424dd96dacaSLiam Girdwood } 425dd96dacaSLiam Girdwood 426dd96dacaSLiam Girdwood static inline struct hda_bus *sof_to_hbus(struct snd_sof_dev *s) 427dd96dacaSLiam Girdwood { 428dd96dacaSLiam Girdwood struct sof_intel_hda_dev *hda = s->pdata->hw_pdata; 429dd96dacaSLiam Girdwood 430dd96dacaSLiam Girdwood return &hda->hbus; 431dd96dacaSLiam Girdwood } 432dd96dacaSLiam Girdwood 433dd96dacaSLiam Girdwood struct sof_intel_hda_stream { 4347623ae79SRanjani Sridharan struct snd_sof_dev *sdev; 435dd96dacaSLiam Girdwood struct hdac_ext_stream hda_stream; 436dd96dacaSLiam Girdwood struct sof_intel_stream stream; 4376b2239e3SRanjani Sridharan int host_reserved; /* reserve host DMA channel */ 438dd96dacaSLiam Girdwood }; 439dd96dacaSLiam Girdwood 440f5dbba9fSRanjani Sridharan #define hstream_to_sof_hda_stream(hstream) \ 441f5dbba9fSRanjani Sridharan container_of(hstream, struct sof_intel_hda_stream, hda_stream) 442f5dbba9fSRanjani Sridharan 443dd96dacaSLiam Girdwood #define bus_to_sof_hda(bus) \ 444dd96dacaSLiam Girdwood container_of(bus, struct sof_intel_hda_dev, hbus.core) 445dd96dacaSLiam Girdwood 446dd96dacaSLiam Girdwood #define SOF_STREAM_SD_OFFSET(s) \ 447dd96dacaSLiam Girdwood (SOF_HDA_ADSP_SD_ENTRY_SIZE * ((s)->index) \ 448dd96dacaSLiam Girdwood + SOF_HDA_ADSP_LOADER_BASE) 449dd96dacaSLiam Girdwood 450dd96dacaSLiam Girdwood /* 451dd96dacaSLiam Girdwood * DSP Core services. 452dd96dacaSLiam Girdwood */ 453dd96dacaSLiam Girdwood int hda_dsp_probe(struct snd_sof_dev *sdev); 454dd96dacaSLiam Girdwood int hda_dsp_remove(struct snd_sof_dev *sdev); 455dd96dacaSLiam Girdwood int hda_dsp_core_reset_enter(struct snd_sof_dev *sdev, 456dd96dacaSLiam Girdwood unsigned int core_mask); 457dd96dacaSLiam Girdwood int hda_dsp_core_reset_leave(struct snd_sof_dev *sdev, 458dd96dacaSLiam Girdwood unsigned int core_mask); 459dd96dacaSLiam Girdwood int hda_dsp_core_stall_reset(struct snd_sof_dev *sdev, unsigned int core_mask); 460dd96dacaSLiam Girdwood int hda_dsp_core_run(struct snd_sof_dev *sdev, unsigned int core_mask); 461dd96dacaSLiam Girdwood int hda_dsp_core_power_up(struct snd_sof_dev *sdev, unsigned int core_mask); 462dd96dacaSLiam Girdwood int hda_dsp_enable_core(struct snd_sof_dev *sdev, unsigned int core_mask); 463dd96dacaSLiam Girdwood int hda_dsp_core_power_down(struct snd_sof_dev *sdev, unsigned int core_mask); 464dd96dacaSLiam Girdwood bool hda_dsp_core_is_enabled(struct snd_sof_dev *sdev, 465dd96dacaSLiam Girdwood unsigned int core_mask); 466dd96dacaSLiam Girdwood int hda_dsp_core_reset_power_down(struct snd_sof_dev *sdev, 467dd96dacaSLiam Girdwood unsigned int core_mask); 468dd96dacaSLiam Girdwood void hda_dsp_ipc_int_enable(struct snd_sof_dev *sdev); 469dd96dacaSLiam Girdwood void hda_dsp_ipc_int_disable(struct snd_sof_dev *sdev); 470dd96dacaSLiam Girdwood 47162f8f766SKeyon Jie int hda_dsp_set_power_state(struct snd_sof_dev *sdev, 47262f8f766SKeyon Jie enum sof_d0_substate d0_substate); 47362f8f766SKeyon Jie 4741c38c922SFred Oh int hda_dsp_suspend(struct snd_sof_dev *sdev); 475dd96dacaSLiam Girdwood int hda_dsp_resume(struct snd_sof_dev *sdev); 4761c38c922SFred Oh int hda_dsp_runtime_suspend(struct snd_sof_dev *sdev); 477dd96dacaSLiam Girdwood int hda_dsp_runtime_resume(struct snd_sof_dev *sdev); 47862fde977SKai Vehmanen int hda_dsp_runtime_idle(struct snd_sof_dev *sdev); 4797077a07aSRanjani Sridharan int hda_dsp_set_hw_params_upon_resume(struct snd_sof_dev *sdev); 480dd96dacaSLiam Girdwood void hda_dsp_dump_skl(struct snd_sof_dev *sdev, u32 flags); 481dd96dacaSLiam Girdwood void hda_dsp_dump(struct snd_sof_dev *sdev, u32 flags); 482f3da49f0SPan Xiuli void hda_ipc_dump(struct snd_sof_dev *sdev); 483f1fd9d0eSKai Vehmanen void hda_ipc_irq_dump(struct snd_sof_dev *sdev); 484dd96dacaSLiam Girdwood 485dd96dacaSLiam Girdwood /* 486dd96dacaSLiam Girdwood * DSP PCM Operations. 487dd96dacaSLiam Girdwood */ 488dd96dacaSLiam Girdwood int hda_dsp_pcm_open(struct snd_sof_dev *sdev, 489dd96dacaSLiam Girdwood struct snd_pcm_substream *substream); 490dd96dacaSLiam Girdwood int hda_dsp_pcm_close(struct snd_sof_dev *sdev, 491dd96dacaSLiam Girdwood struct snd_pcm_substream *substream); 492dd96dacaSLiam Girdwood int hda_dsp_pcm_hw_params(struct snd_sof_dev *sdev, 493dd96dacaSLiam Girdwood struct snd_pcm_substream *substream, 494dd96dacaSLiam Girdwood struct snd_pcm_hw_params *params, 495dd96dacaSLiam Girdwood struct sof_ipc_stream_params *ipc_params); 49693146bc2SRanjani Sridharan int hda_dsp_stream_hw_free(struct snd_sof_dev *sdev, 49793146bc2SRanjani Sridharan struct snd_pcm_substream *substream); 498dd96dacaSLiam Girdwood int hda_dsp_pcm_trigger(struct snd_sof_dev *sdev, 499dd96dacaSLiam Girdwood struct snd_pcm_substream *substream, int cmd); 500dd96dacaSLiam Girdwood snd_pcm_uframes_t hda_dsp_pcm_pointer(struct snd_sof_dev *sdev, 501dd96dacaSLiam Girdwood struct snd_pcm_substream *substream); 502dd96dacaSLiam Girdwood 503dd96dacaSLiam Girdwood /* 504dd96dacaSLiam Girdwood * DSP Stream Operations. 505dd96dacaSLiam Girdwood */ 506dd96dacaSLiam Girdwood 507dd96dacaSLiam Girdwood int hda_dsp_stream_init(struct snd_sof_dev *sdev); 508dd96dacaSLiam Girdwood void hda_dsp_stream_free(struct snd_sof_dev *sdev); 509dd96dacaSLiam Girdwood int hda_dsp_stream_hw_params(struct snd_sof_dev *sdev, 510dd96dacaSLiam Girdwood struct hdac_ext_stream *stream, 511dd96dacaSLiam Girdwood struct snd_dma_buffer *dmab, 512dd96dacaSLiam Girdwood struct snd_pcm_hw_params *params); 513dd96dacaSLiam Girdwood int hda_dsp_stream_trigger(struct snd_sof_dev *sdev, 514dd96dacaSLiam Girdwood struct hdac_ext_stream *stream, int cmd); 515dd96dacaSLiam Girdwood irqreturn_t hda_dsp_stream_threaded_handler(int irq, void *context); 516dd96dacaSLiam Girdwood int hda_dsp_stream_setup_bdl(struct snd_sof_dev *sdev, 517dd96dacaSLiam Girdwood struct snd_dma_buffer *dmab, 518dd96dacaSLiam Girdwood struct hdac_stream *stream); 5197c11af9fSBard Liao bool hda_dsp_check_ipc_irq(struct snd_sof_dev *sdev); 5207c11af9fSBard Liao bool hda_dsp_check_stream_irq(struct snd_sof_dev *sdev); 521dd96dacaSLiam Girdwood 522dd96dacaSLiam Girdwood struct hdac_ext_stream * 523dd96dacaSLiam Girdwood hda_dsp_stream_get(struct snd_sof_dev *sdev, int direction); 524dd96dacaSLiam Girdwood int hda_dsp_stream_put(struct snd_sof_dev *sdev, int direction, int stream_tag); 525dd96dacaSLiam Girdwood int hda_dsp_stream_spib_config(struct snd_sof_dev *sdev, 526dd96dacaSLiam Girdwood struct hdac_ext_stream *stream, 527dd96dacaSLiam Girdwood int enable, u32 size); 528dd96dacaSLiam Girdwood 529dd96dacaSLiam Girdwood void hda_ipc_msg_data(struct snd_sof_dev *sdev, 530dd96dacaSLiam Girdwood struct snd_pcm_substream *substream, 531dd96dacaSLiam Girdwood void *p, size_t sz); 532dd96dacaSLiam Girdwood int hda_ipc_pcm_params(struct snd_sof_dev *sdev, 533dd96dacaSLiam Girdwood struct snd_pcm_substream *substream, 534dd96dacaSLiam Girdwood const struct sof_ipc_pcm_params_reply *reply); 535dd96dacaSLiam Girdwood 536dd96dacaSLiam Girdwood /* 537dd96dacaSLiam Girdwood * DSP IPC Operations. 538dd96dacaSLiam Girdwood */ 539dd96dacaSLiam Girdwood int hda_dsp_ipc_send_msg(struct snd_sof_dev *sdev, 540dd96dacaSLiam Girdwood struct snd_sof_ipc_msg *msg); 541dd96dacaSLiam Girdwood void hda_dsp_ipc_get_reply(struct snd_sof_dev *sdev); 5426eebd390SDaniel Baluta int hda_dsp_ipc_get_mailbox_offset(struct snd_sof_dev *sdev); 5436eebd390SDaniel Baluta int hda_dsp_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id); 5446eebd390SDaniel Baluta 545dd96dacaSLiam Girdwood irqreturn_t hda_dsp_ipc_irq_thread(int irq, void *context); 546dd96dacaSLiam Girdwood int hda_dsp_ipc_cmd_done(struct snd_sof_dev *sdev, int dir); 547dd96dacaSLiam Girdwood 548dd96dacaSLiam Girdwood /* 549dd96dacaSLiam Girdwood * DSP Code loader. 550dd96dacaSLiam Girdwood */ 551dd96dacaSLiam Girdwood int hda_dsp_cl_boot_firmware(struct snd_sof_dev *sdev); 552dd96dacaSLiam Girdwood int hda_dsp_cl_boot_firmware_skl(struct snd_sof_dev *sdev); 553dd96dacaSLiam Girdwood 554dd96dacaSLiam Girdwood /* pre and post fw run ops */ 555dd96dacaSLiam Girdwood int hda_dsp_pre_fw_run(struct snd_sof_dev *sdev); 556dd96dacaSLiam Girdwood int hda_dsp_post_fw_run(struct snd_sof_dev *sdev); 557dd96dacaSLiam Girdwood 558dd96dacaSLiam Girdwood /* 559dd96dacaSLiam Girdwood * HDA Controller Operations. 560dd96dacaSLiam Girdwood */ 561dd96dacaSLiam Girdwood int hda_dsp_ctrl_get_caps(struct snd_sof_dev *sdev); 562dd96dacaSLiam Girdwood void hda_dsp_ctrl_ppcap_enable(struct snd_sof_dev *sdev, bool enable); 563dd96dacaSLiam Girdwood void hda_dsp_ctrl_ppcap_int_enable(struct snd_sof_dev *sdev, bool enable); 564dd96dacaSLiam Girdwood int hda_dsp_ctrl_link_reset(struct snd_sof_dev *sdev, bool reset); 565dd96dacaSLiam Girdwood void hda_dsp_ctrl_misc_clock_gating(struct snd_sof_dev *sdev, bool enable); 566dd96dacaSLiam Girdwood int hda_dsp_ctrl_clock_power_gating(struct snd_sof_dev *sdev, bool enable); 567dd96dacaSLiam Girdwood int hda_dsp_ctrl_init_chip(struct snd_sof_dev *sdev, bool full_reset); 56813063a2cSZhu Yingjiang void hda_dsp_ctrl_stop_chip(struct snd_sof_dev *sdev); 569dd96dacaSLiam Girdwood /* 570dd96dacaSLiam Girdwood * HDA bus operations. 571dd96dacaSLiam Girdwood */ 572d4ff1b39STakashi Iwai void sof_hda_bus_init(struct hdac_bus *bus, struct device *dev); 573dd96dacaSLiam Girdwood 574dd96dacaSLiam Girdwood #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) 575dd96dacaSLiam Girdwood /* 576dd96dacaSLiam Girdwood * HDA Codec operations. 577dd96dacaSLiam Girdwood */ 57880acdd4fSRanjani Sridharan int hda_codec_probe_bus(struct snd_sof_dev *sdev, 57980acdd4fSRanjani Sridharan bool hda_codec_use_common_hdmi); 580fd15f2f5SRander Wang void hda_codec_jack_wake_enable(struct snd_sof_dev *sdev); 581fd15f2f5SRander Wang void hda_codec_jack_check(struct snd_sof_dev *sdev); 582dd96dacaSLiam Girdwood 583dd96dacaSLiam Girdwood #endif /* CONFIG_SND_SOC_SOF_HDA */ 584dd96dacaSLiam Girdwood 585139c7febSKai Vehmanen #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) && \ 586139c7febSKai Vehmanen (IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI) || \ 587139c7febSKai Vehmanen IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) 588dd96dacaSLiam Girdwood 589dd96dacaSLiam Girdwood void hda_codec_i915_get(struct snd_sof_dev *sdev); 590dd96dacaSLiam Girdwood void hda_codec_i915_put(struct snd_sof_dev *sdev); 591dd96dacaSLiam Girdwood int hda_codec_i915_init(struct snd_sof_dev *sdev); 592dd96dacaSLiam Girdwood int hda_codec_i915_exit(struct snd_sof_dev *sdev); 593dd96dacaSLiam Girdwood 594dd96dacaSLiam Girdwood #else 595dd96dacaSLiam Girdwood 596dd96dacaSLiam Girdwood static inline void hda_codec_i915_get(struct snd_sof_dev *sdev) { } 597dd96dacaSLiam Girdwood static inline void hda_codec_i915_put(struct snd_sof_dev *sdev) { } 598dd96dacaSLiam Girdwood static inline int hda_codec_i915_init(struct snd_sof_dev *sdev) { return 0; } 599dd96dacaSLiam Girdwood static inline int hda_codec_i915_exit(struct snd_sof_dev *sdev) { return 0; } 600dd96dacaSLiam Girdwood 601139c7febSKai Vehmanen #endif 602dd96dacaSLiam Girdwood 603dd96dacaSLiam Girdwood /* 604dd96dacaSLiam Girdwood * Trace Control. 605dd96dacaSLiam Girdwood */ 606dd96dacaSLiam Girdwood int hda_dsp_trace_init(struct snd_sof_dev *sdev, u32 *stream_tag); 607dd96dacaSLiam Girdwood int hda_dsp_trace_release(struct snd_sof_dev *sdev); 608dd96dacaSLiam Girdwood int hda_dsp_trace_trigger(struct snd_sof_dev *sdev, int cmd); 609dd96dacaSLiam Girdwood 610dd96dacaSLiam Girdwood /* common dai driver */ 611dd96dacaSLiam Girdwood extern struct snd_soc_dai_driver skl_dai[]; 612dd96dacaSLiam Girdwood 613dd96dacaSLiam Girdwood /* 614dd96dacaSLiam Girdwood * Platform Specific HW abstraction Ops. 615dd96dacaSLiam Girdwood */ 616dd96dacaSLiam Girdwood extern const struct snd_sof_dsp_ops sof_apl_ops; 617dd96dacaSLiam Girdwood extern const struct snd_sof_dsp_ops sof_cnl_ops; 618dd96dacaSLiam Girdwood 619dd96dacaSLiam Girdwood extern const struct sof_intel_dsp_desc apl_chip_info; 620dd96dacaSLiam Girdwood extern const struct sof_intel_dsp_desc cnl_chip_info; 621dd96dacaSLiam Girdwood extern const struct sof_intel_dsp_desc skl_chip_info; 622630be964SZhu Yingjiang extern const struct sof_intel_dsp_desc icl_chip_info; 6231205c81eSPan Xiuli extern const struct sof_intel_dsp_desc tgl_chip_info; 62461732690SPan Xiuli extern const struct sof_intel_dsp_desc ehl_chip_info; 6256fd99035SPan Xiuli extern const struct sof_intel_dsp_desc jsl_chip_info; 626dd96dacaSLiam Girdwood 627285880a2SDaniel Baluta /* machine driver select */ 628285880a2SDaniel Baluta void hda_machine_select(struct snd_sof_dev *sdev); 629285880a2SDaniel Baluta void hda_set_mach_params(const struct snd_soc_acpi_mach *mach, 630285880a2SDaniel Baluta struct device *dev); 631285880a2SDaniel Baluta 632dd96dacaSLiam Girdwood #endif 633