1dd96dacaSLiam Girdwood /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */ 2dd96dacaSLiam Girdwood /* 3dd96dacaSLiam Girdwood * This file is provided under a dual BSD/GPLv2 license. When using or 4dd96dacaSLiam Girdwood * redistributing this file, you may do so under either license. 5dd96dacaSLiam Girdwood * 6dd96dacaSLiam Girdwood * Copyright(c) 2017 Intel Corporation. All rights reserved. 7dd96dacaSLiam Girdwood * 8dd96dacaSLiam Girdwood * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com> 9dd96dacaSLiam Girdwood */ 10dd96dacaSLiam Girdwood 11dd96dacaSLiam Girdwood #ifndef __SOF_INTEL_HDA_H 12dd96dacaSLiam Girdwood #define __SOF_INTEL_HDA_H 13dd96dacaSLiam Girdwood 14dd96dacaSLiam Girdwood #include <sound/hda_codec.h> 15dd96dacaSLiam Girdwood #include <sound/hdaudio_ext.h> 16dd96dacaSLiam Girdwood #include "shim.h" 17dd96dacaSLiam Girdwood 18dd96dacaSLiam Girdwood /* PCI registers */ 19dd96dacaSLiam Girdwood #define PCI_TCSEL 0x44 20dd96dacaSLiam Girdwood #define PCI_PGCTL PCI_TCSEL 21dd96dacaSLiam Girdwood #define PCI_CGCTL 0x48 22dd96dacaSLiam Girdwood 23dd96dacaSLiam Girdwood /* PCI_PGCTL bits */ 24dd96dacaSLiam Girdwood #define PCI_PGCTL_ADSPPGD BIT(2) 25dd96dacaSLiam Girdwood #define PCI_PGCTL_LSRMD_MASK BIT(4) 26dd96dacaSLiam Girdwood 27dd96dacaSLiam Girdwood /* PCI_CGCTL bits */ 28dd96dacaSLiam Girdwood #define PCI_CGCTL_MISCBDCGE_MASK BIT(6) 29dd96dacaSLiam Girdwood #define PCI_CGCTL_ADSPDCGE BIT(1) 30dd96dacaSLiam Girdwood 31dd96dacaSLiam Girdwood /* Legacy HDA registers and bits used - widths are variable */ 32dd96dacaSLiam Girdwood #define SOF_HDA_GCAP 0x0 33dd96dacaSLiam Girdwood #define SOF_HDA_GCTL 0x8 34dd96dacaSLiam Girdwood /* accept unsol. response enable */ 35dd96dacaSLiam Girdwood #define SOF_HDA_GCTL_UNSOL BIT(8) 36dd96dacaSLiam Girdwood #define SOF_HDA_LLCH 0x14 37dd96dacaSLiam Girdwood #define SOF_HDA_INTCTL 0x20 38dd96dacaSLiam Girdwood #define SOF_HDA_INTSTS 0x24 39dd96dacaSLiam Girdwood #define SOF_HDA_WAKESTS 0x0E 40dd96dacaSLiam Girdwood #define SOF_HDA_WAKESTS_INT_MASK ((1 << 8) - 1) 41dd96dacaSLiam Girdwood #define SOF_HDA_RIRBSTS 0x5d 42dd96dacaSLiam Girdwood #define SOF_HDA_VS_EM2_L1SEN BIT(13) 43dd96dacaSLiam Girdwood 44dd96dacaSLiam Girdwood /* SOF_HDA_GCTL register bist */ 45dd96dacaSLiam Girdwood #define SOF_HDA_GCTL_RESET BIT(0) 46dd96dacaSLiam Girdwood 47dd96dacaSLiam Girdwood /* SOF_HDA_INCTL and SOF_HDA_INTSTS regs */ 48dd96dacaSLiam Girdwood #define SOF_HDA_INT_GLOBAL_EN BIT(31) 49dd96dacaSLiam Girdwood #define SOF_HDA_INT_CTRL_EN BIT(30) 50dd96dacaSLiam Girdwood #define SOF_HDA_INT_ALL_STREAM 0xff 51dd96dacaSLiam Girdwood 52dd96dacaSLiam Girdwood #define SOF_HDA_MAX_CAPS 10 53dd96dacaSLiam Girdwood #define SOF_HDA_CAP_ID_OFF 16 54dd96dacaSLiam Girdwood #define SOF_HDA_CAP_ID_MASK GENMASK(SOF_HDA_CAP_ID_OFF + 11,\ 55dd96dacaSLiam Girdwood SOF_HDA_CAP_ID_OFF) 56dd96dacaSLiam Girdwood #define SOF_HDA_CAP_NEXT_MASK 0xFFFF 57dd96dacaSLiam Girdwood 58dd96dacaSLiam Girdwood #define SOF_HDA_GTS_CAP_ID 0x1 59dd96dacaSLiam Girdwood #define SOF_HDA_ML_CAP_ID 0x2 60dd96dacaSLiam Girdwood 61dd96dacaSLiam Girdwood #define SOF_HDA_PP_CAP_ID 0x3 62dd96dacaSLiam Girdwood #define SOF_HDA_REG_PP_PPCH 0x10 63dd96dacaSLiam Girdwood #define SOF_HDA_REG_PP_PPCTL 0x04 64f1fd9d0eSKai Vehmanen #define SOF_HDA_REG_PP_PPSTS 0x08 65dd96dacaSLiam Girdwood #define SOF_HDA_PPCTL_PIE BIT(31) 66dd96dacaSLiam Girdwood #define SOF_HDA_PPCTL_GPROCEN BIT(30) 67dd96dacaSLiam Girdwood 68dd96dacaSLiam Girdwood /* DPIB entry size: 8 Bytes = 2 DWords */ 69dd96dacaSLiam Girdwood #define SOF_HDA_DPIB_ENTRY_SIZE 0x8 70dd96dacaSLiam Girdwood 71dd96dacaSLiam Girdwood #define SOF_HDA_SPIB_CAP_ID 0x4 72dd96dacaSLiam Girdwood #define SOF_HDA_DRSM_CAP_ID 0x5 73dd96dacaSLiam Girdwood 74dd96dacaSLiam Girdwood #define SOF_HDA_SPIB_BASE 0x08 75dd96dacaSLiam Girdwood #define SOF_HDA_SPIB_INTERVAL 0x08 76dd96dacaSLiam Girdwood #define SOF_HDA_SPIB_SPIB 0x00 77dd96dacaSLiam Girdwood #define SOF_HDA_SPIB_MAXFIFO 0x04 78dd96dacaSLiam Girdwood 79dd96dacaSLiam Girdwood #define SOF_HDA_PPHC_BASE 0x10 80dd96dacaSLiam Girdwood #define SOF_HDA_PPHC_INTERVAL 0x10 81dd96dacaSLiam Girdwood 82dd96dacaSLiam Girdwood #define SOF_HDA_PPLC_BASE 0x10 83dd96dacaSLiam Girdwood #define SOF_HDA_PPLC_MULTI 0x10 84dd96dacaSLiam Girdwood #define SOF_HDA_PPLC_INTERVAL 0x10 85dd96dacaSLiam Girdwood 86dd96dacaSLiam Girdwood #define SOF_HDA_DRSM_BASE 0x08 87dd96dacaSLiam Girdwood #define SOF_HDA_DRSM_INTERVAL 0x08 88dd96dacaSLiam Girdwood 89dd96dacaSLiam Girdwood /* Descriptor error interrupt */ 90dd96dacaSLiam Girdwood #define SOF_HDA_CL_DMA_SD_INT_DESC_ERR 0x10 91dd96dacaSLiam Girdwood 92dd96dacaSLiam Girdwood /* FIFO error interrupt */ 93dd96dacaSLiam Girdwood #define SOF_HDA_CL_DMA_SD_INT_FIFO_ERR 0x08 94dd96dacaSLiam Girdwood 95dd96dacaSLiam Girdwood /* Buffer completion interrupt */ 96dd96dacaSLiam Girdwood #define SOF_HDA_CL_DMA_SD_INT_COMPLETE 0x04 97dd96dacaSLiam Girdwood 98dd96dacaSLiam Girdwood #define SOF_HDA_CL_DMA_SD_INT_MASK \ 99dd96dacaSLiam Girdwood (SOF_HDA_CL_DMA_SD_INT_DESC_ERR | \ 100dd96dacaSLiam Girdwood SOF_HDA_CL_DMA_SD_INT_FIFO_ERR | \ 101dd96dacaSLiam Girdwood SOF_HDA_CL_DMA_SD_INT_COMPLETE) 102dd96dacaSLiam Girdwood #define SOF_HDA_SD_CTL_DMA_START 0x02 /* Stream DMA start bit */ 103dd96dacaSLiam Girdwood 104dd96dacaSLiam Girdwood /* Intel HD Audio Code Loader DMA Registers */ 105dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_LOADER_BASE 0x80 106dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_DPLBASE 0x70 107dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_DPUBASE 0x74 108dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_DPLBASE_ENABLE 0x01 109dd96dacaSLiam Girdwood 110dd96dacaSLiam Girdwood /* Stream Registers */ 111dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SD_CTL 0x00 112dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SD_STS 0x03 113dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SD_LPIB 0x04 114dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SD_CBL 0x08 115dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SD_LVI 0x0C 116dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SD_FIFOW 0x0E 117dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SD_FIFOSIZE 0x10 118dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SD_FORMAT 0x12 119dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SD_FIFOL 0x14 120dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SD_BDLPL 0x18 121dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SD_BDLPU 0x1C 122dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_SD_ENTRY_SIZE 0x20 123dd96dacaSLiam Girdwood 124dd96dacaSLiam Girdwood /* CL: Software Position Based FIFO Capability Registers */ 125dd96dacaSLiam Girdwood #define SOF_DSP_REG_CL_SPBFIFO \ 126dd96dacaSLiam Girdwood (SOF_HDA_ADSP_LOADER_BASE + 0x20) 127dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCH 0x0 128dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCCTL 0x4 129dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPIB 0x8 130dd96dacaSLiam Girdwood #define SOF_HDA_ADSP_REG_CL_SPBFIFO_MAXFIFOS 0xc 131dd96dacaSLiam Girdwood 132dd96dacaSLiam Girdwood /* Stream Number */ 133dd96dacaSLiam Girdwood #define SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT 20 134dd96dacaSLiam Girdwood #define SOF_HDA_CL_SD_CTL_STREAM_TAG_MASK \ 135dd96dacaSLiam Girdwood GENMASK(SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT + 3,\ 136dd96dacaSLiam Girdwood SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT) 137dd96dacaSLiam Girdwood 138dd96dacaSLiam Girdwood #define HDA_DSP_HDA_BAR 0 139dd96dacaSLiam Girdwood #define HDA_DSP_PP_BAR 1 140dd96dacaSLiam Girdwood #define HDA_DSP_SPIB_BAR 2 141dd96dacaSLiam Girdwood #define HDA_DSP_DRSM_BAR 3 142dd96dacaSLiam Girdwood #define HDA_DSP_BAR 4 143dd96dacaSLiam Girdwood 144dd96dacaSLiam Girdwood #define SRAM_WINDOW_OFFSET(x) (0x80000 + (x) * 0x20000) 145dd96dacaSLiam Girdwood 146dd96dacaSLiam Girdwood #define HDA_DSP_MBOX_OFFSET SRAM_WINDOW_OFFSET(0) 147dd96dacaSLiam Girdwood 148dd96dacaSLiam Girdwood #define HDA_DSP_PANIC_OFFSET(x) \ 149dd96dacaSLiam Girdwood (((x) & 0xFFFFFF) + HDA_DSP_MBOX_OFFSET) 150dd96dacaSLiam Girdwood 151dd96dacaSLiam Girdwood /* SRAM window 0 FW "registers" */ 152dd96dacaSLiam Girdwood #define HDA_DSP_SRAM_REG_ROM_STATUS (HDA_DSP_MBOX_OFFSET + 0x0) 153dd96dacaSLiam Girdwood #define HDA_DSP_SRAM_REG_ROM_ERROR (HDA_DSP_MBOX_OFFSET + 0x4) 154dd96dacaSLiam Girdwood /* FW and ROM share offset 4 */ 155dd96dacaSLiam Girdwood #define HDA_DSP_SRAM_REG_FW_STATUS (HDA_DSP_MBOX_OFFSET + 0x4) 156dd96dacaSLiam Girdwood #define HDA_DSP_SRAM_REG_FW_TRACEP (HDA_DSP_MBOX_OFFSET + 0x8) 157dd96dacaSLiam Girdwood #define HDA_DSP_SRAM_REG_FW_END (HDA_DSP_MBOX_OFFSET + 0xc) 158dd96dacaSLiam Girdwood 159dd96dacaSLiam Girdwood #define HDA_DSP_MBOX_UPLINK_OFFSET 0x81000 160dd96dacaSLiam Girdwood 161dd96dacaSLiam Girdwood #define HDA_DSP_STREAM_RESET_TIMEOUT 300 1627bcaf0f2SZhu Yingjiang /* 1637bcaf0f2SZhu Yingjiang * Timeout in us, for setting the stream RUN bit, during 1647bcaf0f2SZhu Yingjiang * start/stop the stream. The timeout expires if new RUN bit 1657bcaf0f2SZhu Yingjiang * value cannot be read back within the specified time. 1667bcaf0f2SZhu Yingjiang */ 1677bcaf0f2SZhu Yingjiang #define HDA_DSP_STREAM_RUN_TIMEOUT 300 168dd96dacaSLiam Girdwood #define HDA_DSP_CL_TRIGGER_TIMEOUT 300 169dd96dacaSLiam Girdwood 170dd96dacaSLiam Girdwood #define HDA_DSP_SPIB_ENABLE 1 171dd96dacaSLiam Girdwood #define HDA_DSP_SPIB_DISABLE 0 172dd96dacaSLiam Girdwood 173dd96dacaSLiam Girdwood #define SOF_HDA_MAX_BUFFER_SIZE (32 * PAGE_SIZE) 174dd96dacaSLiam Girdwood 175dd96dacaSLiam Girdwood #define HDA_DSP_STACK_DUMP_SIZE 32 176dd96dacaSLiam Girdwood 177dd96dacaSLiam Girdwood /* ROM status/error values */ 178dd96dacaSLiam Girdwood #define HDA_DSP_ROM_STS_MASK 0xf 179dd96dacaSLiam Girdwood #define HDA_DSP_ROM_INIT 0x1 180dd96dacaSLiam Girdwood #define HDA_DSP_ROM_FW_MANIFEST_LOADED 0x3 181dd96dacaSLiam Girdwood #define HDA_DSP_ROM_FW_FW_LOADED 0x4 182dd96dacaSLiam Girdwood #define HDA_DSP_ROM_FW_ENTERED 0x5 183dd96dacaSLiam Girdwood #define HDA_DSP_ROM_RFW_START 0xf 184dd96dacaSLiam Girdwood #define HDA_DSP_ROM_CSE_ERROR 40 185dd96dacaSLiam Girdwood #define HDA_DSP_ROM_CSE_WRONG_RESPONSE 41 186dd96dacaSLiam Girdwood #define HDA_DSP_ROM_IMR_TO_SMALL 42 187dd96dacaSLiam Girdwood #define HDA_DSP_ROM_BASE_FW_NOT_FOUND 43 188dd96dacaSLiam Girdwood #define HDA_DSP_ROM_CSE_VALIDATION_FAILED 44 189dd96dacaSLiam Girdwood #define HDA_DSP_ROM_IPC_FATAL_ERROR 45 190dd96dacaSLiam Girdwood #define HDA_DSP_ROM_L2_CACHE_ERROR 46 191dd96dacaSLiam Girdwood #define HDA_DSP_ROM_LOAD_OFFSET_TO_SMALL 47 192dd96dacaSLiam Girdwood #define HDA_DSP_ROM_API_PTR_INVALID 50 193dd96dacaSLiam Girdwood #define HDA_DSP_ROM_BASEFW_INCOMPAT 51 194dd96dacaSLiam Girdwood #define HDA_DSP_ROM_UNHANDLED_INTERRUPT 0xBEE00000 195dd96dacaSLiam Girdwood #define HDA_DSP_ROM_MEMORY_HOLE_ECC 0xECC00000 196dd96dacaSLiam Girdwood #define HDA_DSP_ROM_KERNEL_EXCEPTION 0xCAFE0000 197dd96dacaSLiam Girdwood #define HDA_DSP_ROM_USER_EXCEPTION 0xBEEF0000 198dd96dacaSLiam Girdwood #define HDA_DSP_ROM_UNEXPECTED_RESET 0xDECAF000 199dd96dacaSLiam Girdwood #define HDA_DSP_ROM_NULL_FW_ENTRY 0x4c4c4e55 200dd96dacaSLiam Girdwood #define HDA_DSP_IPC_PURGE_FW 0x01004000 201dd96dacaSLiam Girdwood 202dd96dacaSLiam Girdwood /* various timeout values */ 203dd96dacaSLiam Girdwood #define HDA_DSP_PU_TIMEOUT 50 204dd96dacaSLiam Girdwood #define HDA_DSP_PD_TIMEOUT 50 205dd96dacaSLiam Girdwood #define HDA_DSP_RESET_TIMEOUT_US 50000 206dd96dacaSLiam Girdwood #define HDA_DSP_BASEFW_TIMEOUT_US 3000000 207dd96dacaSLiam Girdwood #define HDA_DSP_INIT_TIMEOUT_US 500000 208dd96dacaSLiam Girdwood #define HDA_DSP_CTRL_RESET_TIMEOUT 100 209dd96dacaSLiam Girdwood #define HDA_DSP_WAIT_TIMEOUT 500 /* 500 msec */ 210dd96dacaSLiam Girdwood #define HDA_DSP_REG_POLL_INTERVAL_US 500 /* 0.5 msec */ 211dd96dacaSLiam Girdwood 212dd96dacaSLiam Girdwood #define HDA_DSP_ADSPIC_IPC 1 213dd96dacaSLiam Girdwood #define HDA_DSP_ADSPIS_IPC 1 214dd96dacaSLiam Girdwood 215dd96dacaSLiam Girdwood /* Intel HD Audio General DSP Registers */ 216dd96dacaSLiam Girdwood #define HDA_DSP_GEN_BASE 0x0 217dd96dacaSLiam Girdwood #define HDA_DSP_REG_ADSPCS (HDA_DSP_GEN_BASE + 0x04) 218dd96dacaSLiam Girdwood #define HDA_DSP_REG_ADSPIC (HDA_DSP_GEN_BASE + 0x08) 219dd96dacaSLiam Girdwood #define HDA_DSP_REG_ADSPIS (HDA_DSP_GEN_BASE + 0x0C) 220dd96dacaSLiam Girdwood #define HDA_DSP_REG_ADSPIC2 (HDA_DSP_GEN_BASE + 0x10) 221dd96dacaSLiam Girdwood #define HDA_DSP_REG_ADSPIS2 (HDA_DSP_GEN_BASE + 0x14) 222dd96dacaSLiam Girdwood 223dd96dacaSLiam Girdwood /* Intel HD Audio Inter-Processor Communication Registers */ 224dd96dacaSLiam Girdwood #define HDA_DSP_IPC_BASE 0x40 225dd96dacaSLiam Girdwood #define HDA_DSP_REG_HIPCT (HDA_DSP_IPC_BASE + 0x00) 226dd96dacaSLiam Girdwood #define HDA_DSP_REG_HIPCTE (HDA_DSP_IPC_BASE + 0x04) 227dd96dacaSLiam Girdwood #define HDA_DSP_REG_HIPCI (HDA_DSP_IPC_BASE + 0x08) 228dd96dacaSLiam Girdwood #define HDA_DSP_REG_HIPCIE (HDA_DSP_IPC_BASE + 0x0C) 229dd96dacaSLiam Girdwood #define HDA_DSP_REG_HIPCCTL (HDA_DSP_IPC_BASE + 0x10) 230dd96dacaSLiam Girdwood 231dd96dacaSLiam Girdwood /* HIPCI */ 232dd96dacaSLiam Girdwood #define HDA_DSP_REG_HIPCI_BUSY BIT(31) 233dd96dacaSLiam Girdwood #define HDA_DSP_REG_HIPCI_MSG_MASK 0x7FFFFFFF 234dd96dacaSLiam Girdwood 235dd96dacaSLiam Girdwood /* HIPCIE */ 236dd96dacaSLiam Girdwood #define HDA_DSP_REG_HIPCIE_DONE BIT(30) 237dd96dacaSLiam Girdwood #define HDA_DSP_REG_HIPCIE_MSG_MASK 0x3FFFFFFF 238dd96dacaSLiam Girdwood 239dd96dacaSLiam Girdwood /* HIPCCTL */ 240dd96dacaSLiam Girdwood #define HDA_DSP_REG_HIPCCTL_DONE BIT(1) 241dd96dacaSLiam Girdwood #define HDA_DSP_REG_HIPCCTL_BUSY BIT(0) 242dd96dacaSLiam Girdwood 243dd96dacaSLiam Girdwood /* HIPCT */ 244dd96dacaSLiam Girdwood #define HDA_DSP_REG_HIPCT_BUSY BIT(31) 245dd96dacaSLiam Girdwood #define HDA_DSP_REG_HIPCT_MSG_MASK 0x7FFFFFFF 246dd96dacaSLiam Girdwood 247dd96dacaSLiam Girdwood /* HIPCTE */ 248dd96dacaSLiam Girdwood #define HDA_DSP_REG_HIPCTE_MSG_MASK 0x3FFFFFFF 249dd96dacaSLiam Girdwood 250dd96dacaSLiam Girdwood #define HDA_DSP_ADSPIC_CL_DMA 0x2 251dd96dacaSLiam Girdwood #define HDA_DSP_ADSPIS_CL_DMA 0x2 252dd96dacaSLiam Girdwood 253dd96dacaSLiam Girdwood /* Delay before scheduling D0i3 entry */ 254dd96dacaSLiam Girdwood #define BXT_D0I3_DELAY 5000 255dd96dacaSLiam Girdwood 256dd96dacaSLiam Girdwood #define FW_CL_STREAM_NUMBER 0x1 257dd96dacaSLiam Girdwood 258dd96dacaSLiam Girdwood /* ADSPCS - Audio DSP Control & Status */ 259dd96dacaSLiam Girdwood 260dd96dacaSLiam Girdwood /* 261dd96dacaSLiam Girdwood * Core Reset - asserted high 262dd96dacaSLiam Girdwood * CRST Mask for a given core mask pattern, cm 263dd96dacaSLiam Girdwood */ 264dd96dacaSLiam Girdwood #define HDA_DSP_ADSPCS_CRST_SHIFT 0 265dd96dacaSLiam Girdwood #define HDA_DSP_ADSPCS_CRST_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CRST_SHIFT) 266dd96dacaSLiam Girdwood 267dd96dacaSLiam Girdwood /* 268dd96dacaSLiam Girdwood * Core run/stall - when set to '1' core is stalled 269dd96dacaSLiam Girdwood * CSTALL Mask for a given core mask pattern, cm 270dd96dacaSLiam Girdwood */ 271dd96dacaSLiam Girdwood #define HDA_DSP_ADSPCS_CSTALL_SHIFT 8 272dd96dacaSLiam Girdwood #define HDA_DSP_ADSPCS_CSTALL_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CSTALL_SHIFT) 273dd96dacaSLiam Girdwood 274dd96dacaSLiam Girdwood /* 275dd96dacaSLiam Girdwood * Set Power Active - when set to '1' turn cores on 276dd96dacaSLiam Girdwood * SPA Mask for a given core mask pattern, cm 277dd96dacaSLiam Girdwood */ 278dd96dacaSLiam Girdwood #define HDA_DSP_ADSPCS_SPA_SHIFT 16 279dd96dacaSLiam Girdwood #define HDA_DSP_ADSPCS_SPA_MASK(cm) ((cm) << HDA_DSP_ADSPCS_SPA_SHIFT) 280dd96dacaSLiam Girdwood 281dd96dacaSLiam Girdwood /* 282dd96dacaSLiam Girdwood * Current Power Active - power status of cores, set by hardware 283dd96dacaSLiam Girdwood * CPA Mask for a given core mask pattern, cm 284dd96dacaSLiam Girdwood */ 285dd96dacaSLiam Girdwood #define HDA_DSP_ADSPCS_CPA_SHIFT 24 286dd96dacaSLiam Girdwood #define HDA_DSP_ADSPCS_CPA_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CPA_SHIFT) 287dd96dacaSLiam Girdwood 288dd96dacaSLiam Girdwood /* Mask for a given core index, c = 0.. number of supported cores - 1 */ 289dd96dacaSLiam Girdwood #define HDA_DSP_CORE_MASK(c) BIT(c) 290dd96dacaSLiam Girdwood 291dd96dacaSLiam Girdwood /* 292dd96dacaSLiam Girdwood * Mask for a given number of cores 293dd96dacaSLiam Girdwood * nc = number of supported cores 294dd96dacaSLiam Girdwood */ 295dd96dacaSLiam Girdwood #define SOF_DSP_CORES_MASK(nc) GENMASK(((nc) - 1), 0) 296dd96dacaSLiam Girdwood 297dd96dacaSLiam Girdwood /* Intel HD Audio Inter-Processor Communication Registers for Cannonlake*/ 298dd96dacaSLiam Girdwood #define CNL_DSP_IPC_BASE 0xc0 299dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCTDR (CNL_DSP_IPC_BASE + 0x00) 300dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCTDA (CNL_DSP_IPC_BASE + 0x04) 301dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCTDD (CNL_DSP_IPC_BASE + 0x08) 302dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCIDR (CNL_DSP_IPC_BASE + 0x10) 303dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCIDA (CNL_DSP_IPC_BASE + 0x14) 304dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCCTL (CNL_DSP_IPC_BASE + 0x28) 305dd96dacaSLiam Girdwood 306dd96dacaSLiam Girdwood /* HIPCI */ 307dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCIDR_BUSY BIT(31) 308dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCIDR_MSG_MASK 0x7FFFFFFF 309dd96dacaSLiam Girdwood 310dd96dacaSLiam Girdwood /* HIPCIE */ 311dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCIDA_DONE BIT(31) 312dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCIDA_MSG_MASK 0x7FFFFFFF 313dd96dacaSLiam Girdwood 314dd96dacaSLiam Girdwood /* HIPCCTL */ 315dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCCTL_DONE BIT(1) 316dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCCTL_BUSY BIT(0) 317dd96dacaSLiam Girdwood 318dd96dacaSLiam Girdwood /* HIPCT */ 319dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCTDR_BUSY BIT(31) 320dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCTDR_MSG_MASK 0x7FFFFFFF 321dd96dacaSLiam Girdwood 322dd96dacaSLiam Girdwood /* HIPCTDA */ 323dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCTDA_DONE BIT(31) 324dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCTDA_MSG_MASK 0x7FFFFFFF 325dd96dacaSLiam Girdwood 326dd96dacaSLiam Girdwood /* HIPCTDD */ 327dd96dacaSLiam Girdwood #define CNL_DSP_REG_HIPCTDD_MSG_MASK 0x7FFFFFFF 328dd96dacaSLiam Girdwood 329dd96dacaSLiam Girdwood /* BDL */ 330dd96dacaSLiam Girdwood #define HDA_DSP_BDL_SIZE 4096 331dd96dacaSLiam Girdwood #define HDA_DSP_MAX_BDL_ENTRIES \ 332dd96dacaSLiam Girdwood (HDA_DSP_BDL_SIZE / sizeof(struct sof_intel_dsp_bdl)) 333dd96dacaSLiam Girdwood 334dd96dacaSLiam Girdwood /* Number of DAIs */ 335dd96dacaSLiam Girdwood #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) 336dd96dacaSLiam Girdwood #define SOF_SKL_NUM_DAIS 14 337dd96dacaSLiam Girdwood #else 338dd96dacaSLiam Girdwood #define SOF_SKL_NUM_DAIS 8 339dd96dacaSLiam Girdwood #endif 340dd96dacaSLiam Girdwood 341dd96dacaSLiam Girdwood /* Intel HD Audio SRAM Window 0*/ 342dd96dacaSLiam Girdwood #define HDA_ADSP_SRAM0_BASE_SKL 0x8000 343dd96dacaSLiam Girdwood 344dd96dacaSLiam Girdwood /* Firmware status window */ 345dd96dacaSLiam Girdwood #define HDA_ADSP_FW_STATUS_SKL HDA_ADSP_SRAM0_BASE_SKL 346dd96dacaSLiam Girdwood #define HDA_ADSP_ERROR_CODE_SKL (HDA_ADSP_FW_STATUS_SKL + 0x4) 347dd96dacaSLiam Girdwood 348df7e0de5SZhu Yingjiang /* Host Device Memory Space */ 349df7e0de5SZhu Yingjiang #define APL_SSP_BASE_OFFSET 0x2000 350df7e0de5SZhu Yingjiang #define CNL_SSP_BASE_OFFSET 0x10000 351df7e0de5SZhu Yingjiang 352df7e0de5SZhu Yingjiang /* Host Device Memory Size of a Single SSP */ 353df7e0de5SZhu Yingjiang #define SSP_DEV_MEM_SIZE 0x1000 354df7e0de5SZhu Yingjiang 355b095fe47SZhu Yingjiang /* SSP Count of the Platform */ 356b095fe47SZhu Yingjiang #define APL_SSP_COUNT 6 357b095fe47SZhu Yingjiang #define CNL_SSP_COUNT 3 358ec836daaSZhu Yingjiang #define ICL_SSP_COUNT 6 359b095fe47SZhu Yingjiang 36074ed4097SZhu Yingjiang /* SSP Registers */ 36174ed4097SZhu Yingjiang #define SSP_SSC1_OFFSET 0x4 36274ed4097SZhu Yingjiang #define SSP_SET_SCLK_SLAVE BIT(25) 36374ed4097SZhu Yingjiang #define SSP_SET_SFRM_SLAVE BIT(24) 36474ed4097SZhu Yingjiang #define SSP_SET_SLAVE (SSP_SET_SCLK_SLAVE | SSP_SET_SFRM_SLAVE) 36574ed4097SZhu Yingjiang 366dd96dacaSLiam Girdwood #define HDA_IDISP_CODEC(x) ((x) & BIT(2)) 367dd96dacaSLiam Girdwood 368dd96dacaSLiam Girdwood struct sof_intel_dsp_bdl { 369dd96dacaSLiam Girdwood __le32 addr_l; 370dd96dacaSLiam Girdwood __le32 addr_h; 371dd96dacaSLiam Girdwood __le32 size; 372dd96dacaSLiam Girdwood __le32 ioc; 373dd96dacaSLiam Girdwood } __attribute((packed)); 374dd96dacaSLiam Girdwood 375dd96dacaSLiam Girdwood #define SOF_HDA_PLAYBACK_STREAMS 16 376dd96dacaSLiam Girdwood #define SOF_HDA_CAPTURE_STREAMS 16 377dd96dacaSLiam Girdwood #define SOF_HDA_PLAYBACK 0 378dd96dacaSLiam Girdwood #define SOF_HDA_CAPTURE 1 379dd96dacaSLiam Girdwood 380dd96dacaSLiam Girdwood /* represents DSP HDA controller frontend - i.e. host facing control */ 381dd96dacaSLiam Girdwood struct sof_intel_hda_dev { 382dd96dacaSLiam Girdwood 383dd96dacaSLiam Girdwood struct hda_bus hbus; 384dd96dacaSLiam Girdwood 385dd96dacaSLiam Girdwood /* hw config */ 386dd96dacaSLiam Girdwood const struct sof_intel_dsp_desc *desc; 387dd96dacaSLiam Girdwood 388dd96dacaSLiam Girdwood /* trace */ 389dd96dacaSLiam Girdwood struct hdac_ext_stream *dtrace_stream; 390dd96dacaSLiam Girdwood 391dd96dacaSLiam Girdwood /* if position update IPC needed */ 392dd96dacaSLiam Girdwood u32 no_ipc_position; 393dd96dacaSLiam Girdwood 394e8e55dbeSKeyon Jie /* the maximum number of streams (playback + capture) supported */ 395e8e55dbeSKeyon Jie u32 stream_max; 396e8e55dbeSKeyon Jie 397dd96dacaSLiam Girdwood int irq; 398dd96dacaSLiam Girdwood 399dd96dacaSLiam Girdwood /* DMIC device */ 400dd96dacaSLiam Girdwood struct platform_device *dmic_dev; 401dd96dacaSLiam Girdwood }; 402dd96dacaSLiam Girdwood 403dd96dacaSLiam Girdwood static inline struct hdac_bus *sof_to_bus(struct snd_sof_dev *s) 404dd96dacaSLiam Girdwood { 405dd96dacaSLiam Girdwood struct sof_intel_hda_dev *hda = s->pdata->hw_pdata; 406dd96dacaSLiam Girdwood 407dd96dacaSLiam Girdwood return &hda->hbus.core; 408dd96dacaSLiam Girdwood } 409dd96dacaSLiam Girdwood 410dd96dacaSLiam Girdwood static inline struct hda_bus *sof_to_hbus(struct snd_sof_dev *s) 411dd96dacaSLiam Girdwood { 412dd96dacaSLiam Girdwood struct sof_intel_hda_dev *hda = s->pdata->hw_pdata; 413dd96dacaSLiam Girdwood 414dd96dacaSLiam Girdwood return &hda->hbus; 415dd96dacaSLiam Girdwood } 416dd96dacaSLiam Girdwood 417dd96dacaSLiam Girdwood struct sof_intel_hda_stream { 4187623ae79SRanjani Sridharan struct snd_sof_dev *sdev; 419dd96dacaSLiam Girdwood struct hdac_ext_stream hda_stream; 420dd96dacaSLiam Girdwood struct sof_intel_stream stream; 421ed3baacdSRanjani Sridharan int hw_params_upon_resume; /* set up hw_params upon resume */ 4226b2239e3SRanjani Sridharan int host_reserved; /* reserve host DMA channel */ 423dd96dacaSLiam Girdwood }; 424dd96dacaSLiam Girdwood 425f5dbba9fSRanjani Sridharan #define hstream_to_sof_hda_stream(hstream) \ 426f5dbba9fSRanjani Sridharan container_of(hstream, struct sof_intel_hda_stream, hda_stream) 427f5dbba9fSRanjani Sridharan 428dd96dacaSLiam Girdwood #define bus_to_sof_hda(bus) \ 429dd96dacaSLiam Girdwood container_of(bus, struct sof_intel_hda_dev, hbus.core) 430dd96dacaSLiam Girdwood 431dd96dacaSLiam Girdwood #define SOF_STREAM_SD_OFFSET(s) \ 432dd96dacaSLiam Girdwood (SOF_HDA_ADSP_SD_ENTRY_SIZE * ((s)->index) \ 433dd96dacaSLiam Girdwood + SOF_HDA_ADSP_LOADER_BASE) 434dd96dacaSLiam Girdwood 435dd96dacaSLiam Girdwood /* 436dd96dacaSLiam Girdwood * DSP Core services. 437dd96dacaSLiam Girdwood */ 438dd96dacaSLiam Girdwood int hda_dsp_probe(struct snd_sof_dev *sdev); 439dd96dacaSLiam Girdwood int hda_dsp_remove(struct snd_sof_dev *sdev); 440dd96dacaSLiam Girdwood int hda_dsp_core_reset_enter(struct snd_sof_dev *sdev, 441dd96dacaSLiam Girdwood unsigned int core_mask); 442dd96dacaSLiam Girdwood int hda_dsp_core_reset_leave(struct snd_sof_dev *sdev, 443dd96dacaSLiam Girdwood unsigned int core_mask); 444dd96dacaSLiam Girdwood int hda_dsp_core_stall_reset(struct snd_sof_dev *sdev, unsigned int core_mask); 445dd96dacaSLiam Girdwood int hda_dsp_core_run(struct snd_sof_dev *sdev, unsigned int core_mask); 446dd96dacaSLiam Girdwood int hda_dsp_core_power_up(struct snd_sof_dev *sdev, unsigned int core_mask); 447dd96dacaSLiam Girdwood int hda_dsp_enable_core(struct snd_sof_dev *sdev, unsigned int core_mask); 448dd96dacaSLiam Girdwood int hda_dsp_core_power_down(struct snd_sof_dev *sdev, unsigned int core_mask); 449dd96dacaSLiam Girdwood bool hda_dsp_core_is_enabled(struct snd_sof_dev *sdev, 450dd96dacaSLiam Girdwood unsigned int core_mask); 451dd96dacaSLiam Girdwood int hda_dsp_core_reset_power_down(struct snd_sof_dev *sdev, 452dd96dacaSLiam Girdwood unsigned int core_mask); 453dd96dacaSLiam Girdwood void hda_dsp_ipc_int_enable(struct snd_sof_dev *sdev); 454dd96dacaSLiam Girdwood void hda_dsp_ipc_int_disable(struct snd_sof_dev *sdev); 455dd96dacaSLiam Girdwood 4561c38c922SFred Oh int hda_dsp_suspend(struct snd_sof_dev *sdev); 457dd96dacaSLiam Girdwood int hda_dsp_resume(struct snd_sof_dev *sdev); 4581c38c922SFred Oh int hda_dsp_runtime_suspend(struct snd_sof_dev *sdev); 459dd96dacaSLiam Girdwood int hda_dsp_runtime_resume(struct snd_sof_dev *sdev); 46062fde977SKai Vehmanen int hda_dsp_runtime_idle(struct snd_sof_dev *sdev); 4617077a07aSRanjani Sridharan int hda_dsp_set_hw_params_upon_resume(struct snd_sof_dev *sdev); 462dd96dacaSLiam Girdwood void hda_dsp_dump_skl(struct snd_sof_dev *sdev, u32 flags); 463dd96dacaSLiam Girdwood void hda_dsp_dump(struct snd_sof_dev *sdev, u32 flags); 464f3da49f0SPan Xiuli void hda_ipc_dump(struct snd_sof_dev *sdev); 465f1fd9d0eSKai Vehmanen void hda_ipc_irq_dump(struct snd_sof_dev *sdev); 466dd96dacaSLiam Girdwood 467dd96dacaSLiam Girdwood /* 468dd96dacaSLiam Girdwood * DSP PCM Operations. 469dd96dacaSLiam Girdwood */ 470dd96dacaSLiam Girdwood int hda_dsp_pcm_open(struct snd_sof_dev *sdev, 471dd96dacaSLiam Girdwood struct snd_pcm_substream *substream); 472dd96dacaSLiam Girdwood int hda_dsp_pcm_close(struct snd_sof_dev *sdev, 473dd96dacaSLiam Girdwood struct snd_pcm_substream *substream); 474dd96dacaSLiam Girdwood int hda_dsp_pcm_hw_params(struct snd_sof_dev *sdev, 475dd96dacaSLiam Girdwood struct snd_pcm_substream *substream, 476dd96dacaSLiam Girdwood struct snd_pcm_hw_params *params, 477dd96dacaSLiam Girdwood struct sof_ipc_stream_params *ipc_params); 47893146bc2SRanjani Sridharan int hda_dsp_stream_hw_free(struct snd_sof_dev *sdev, 47993146bc2SRanjani Sridharan struct snd_pcm_substream *substream); 480dd96dacaSLiam Girdwood int hda_dsp_pcm_trigger(struct snd_sof_dev *sdev, 481dd96dacaSLiam Girdwood struct snd_pcm_substream *substream, int cmd); 482dd96dacaSLiam Girdwood snd_pcm_uframes_t hda_dsp_pcm_pointer(struct snd_sof_dev *sdev, 483dd96dacaSLiam Girdwood struct snd_pcm_substream *substream); 484dd96dacaSLiam Girdwood 485dd96dacaSLiam Girdwood /* 486dd96dacaSLiam Girdwood * DSP Stream Operations. 487dd96dacaSLiam Girdwood */ 488dd96dacaSLiam Girdwood 489dd96dacaSLiam Girdwood int hda_dsp_stream_init(struct snd_sof_dev *sdev); 490dd96dacaSLiam Girdwood void hda_dsp_stream_free(struct snd_sof_dev *sdev); 491dd96dacaSLiam Girdwood int hda_dsp_stream_hw_params(struct snd_sof_dev *sdev, 492dd96dacaSLiam Girdwood struct hdac_ext_stream *stream, 493dd96dacaSLiam Girdwood struct snd_dma_buffer *dmab, 494dd96dacaSLiam Girdwood struct snd_pcm_hw_params *params); 495dd96dacaSLiam Girdwood int hda_dsp_stream_trigger(struct snd_sof_dev *sdev, 496dd96dacaSLiam Girdwood struct hdac_ext_stream *stream, int cmd); 497dd96dacaSLiam Girdwood irqreturn_t hda_dsp_stream_interrupt(int irq, void *context); 498dd96dacaSLiam Girdwood irqreturn_t hda_dsp_stream_threaded_handler(int irq, void *context); 499dd96dacaSLiam Girdwood int hda_dsp_stream_setup_bdl(struct snd_sof_dev *sdev, 500dd96dacaSLiam Girdwood struct snd_dma_buffer *dmab, 501dd96dacaSLiam Girdwood struct hdac_stream *stream); 502dd96dacaSLiam Girdwood 503dd96dacaSLiam Girdwood struct hdac_ext_stream * 504dd96dacaSLiam Girdwood hda_dsp_stream_get(struct snd_sof_dev *sdev, int direction); 505dd96dacaSLiam Girdwood int hda_dsp_stream_put(struct snd_sof_dev *sdev, int direction, int stream_tag); 506dd96dacaSLiam Girdwood int hda_dsp_stream_spib_config(struct snd_sof_dev *sdev, 507dd96dacaSLiam Girdwood struct hdac_ext_stream *stream, 508dd96dacaSLiam Girdwood int enable, u32 size); 509dd96dacaSLiam Girdwood 510dd96dacaSLiam Girdwood void hda_ipc_msg_data(struct snd_sof_dev *sdev, 511dd96dacaSLiam Girdwood struct snd_pcm_substream *substream, 512dd96dacaSLiam Girdwood void *p, size_t sz); 513dd96dacaSLiam Girdwood int hda_ipc_pcm_params(struct snd_sof_dev *sdev, 514dd96dacaSLiam Girdwood struct snd_pcm_substream *substream, 515dd96dacaSLiam Girdwood const struct sof_ipc_pcm_params_reply *reply); 516dd96dacaSLiam Girdwood 517dd96dacaSLiam Girdwood /* 518dd96dacaSLiam Girdwood * DSP IPC Operations. 519dd96dacaSLiam Girdwood */ 520dd96dacaSLiam Girdwood int hda_dsp_ipc_send_msg(struct snd_sof_dev *sdev, 521dd96dacaSLiam Girdwood struct snd_sof_ipc_msg *msg); 522dd96dacaSLiam Girdwood void hda_dsp_ipc_get_reply(struct snd_sof_dev *sdev); 523dd96dacaSLiam Girdwood int hda_dsp_ipc_fw_ready(struct snd_sof_dev *sdev, u32 msg_id); 524dd96dacaSLiam Girdwood irqreturn_t hda_dsp_ipc_irq_handler(int irq, void *context); 525dd96dacaSLiam Girdwood irqreturn_t hda_dsp_ipc_irq_thread(int irq, void *context); 526dd96dacaSLiam Girdwood int hda_dsp_ipc_cmd_done(struct snd_sof_dev *sdev, int dir); 527dd96dacaSLiam Girdwood 528dd96dacaSLiam Girdwood /* 529dd96dacaSLiam Girdwood * DSP Code loader. 530dd96dacaSLiam Girdwood */ 531dd96dacaSLiam Girdwood int hda_dsp_cl_boot_firmware(struct snd_sof_dev *sdev); 532dd96dacaSLiam Girdwood int hda_dsp_cl_boot_firmware_skl(struct snd_sof_dev *sdev); 533dd96dacaSLiam Girdwood 534dd96dacaSLiam Girdwood /* pre and post fw run ops */ 535dd96dacaSLiam Girdwood int hda_dsp_pre_fw_run(struct snd_sof_dev *sdev); 536dd96dacaSLiam Girdwood int hda_dsp_post_fw_run(struct snd_sof_dev *sdev); 537dd96dacaSLiam Girdwood 538dd96dacaSLiam Girdwood /* 539dd96dacaSLiam Girdwood * HDA Controller Operations. 540dd96dacaSLiam Girdwood */ 541dd96dacaSLiam Girdwood int hda_dsp_ctrl_get_caps(struct snd_sof_dev *sdev); 542dd96dacaSLiam Girdwood void hda_dsp_ctrl_ppcap_enable(struct snd_sof_dev *sdev, bool enable); 543dd96dacaSLiam Girdwood void hda_dsp_ctrl_ppcap_int_enable(struct snd_sof_dev *sdev, bool enable); 544dd96dacaSLiam Girdwood int hda_dsp_ctrl_link_reset(struct snd_sof_dev *sdev, bool reset); 545dd96dacaSLiam Girdwood void hda_dsp_ctrl_misc_clock_gating(struct snd_sof_dev *sdev, bool enable); 546dd96dacaSLiam Girdwood int hda_dsp_ctrl_clock_power_gating(struct snd_sof_dev *sdev, bool enable); 547dd96dacaSLiam Girdwood int hda_dsp_ctrl_init_chip(struct snd_sof_dev *sdev, bool full_reset); 54813063a2cSZhu Yingjiang void hda_dsp_ctrl_stop_chip(struct snd_sof_dev *sdev); 549dd96dacaSLiam Girdwood /* 550dd96dacaSLiam Girdwood * HDA bus operations. 551dd96dacaSLiam Girdwood */ 552dd96dacaSLiam Girdwood void sof_hda_bus_init(struct hdac_bus *bus, struct device *dev, 553dd96dacaSLiam Girdwood const struct hdac_ext_bus_ops *ext_ops); 554dd96dacaSLiam Girdwood 555dd96dacaSLiam Girdwood #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) 556dd96dacaSLiam Girdwood /* 557dd96dacaSLiam Girdwood * HDA Codec operations. 558dd96dacaSLiam Girdwood */ 559dd96dacaSLiam Girdwood int hda_codec_probe_bus(struct snd_sof_dev *sdev); 560dd96dacaSLiam Girdwood 561dd96dacaSLiam Girdwood #endif /* CONFIG_SND_SOC_SOF_HDA */ 562dd96dacaSLiam Girdwood 563dd96dacaSLiam Girdwood #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) && IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI) 564dd96dacaSLiam Girdwood 565dd96dacaSLiam Girdwood void hda_codec_i915_get(struct snd_sof_dev *sdev); 566dd96dacaSLiam Girdwood void hda_codec_i915_put(struct snd_sof_dev *sdev); 567dd96dacaSLiam Girdwood int hda_codec_i915_init(struct snd_sof_dev *sdev); 568dd96dacaSLiam Girdwood int hda_codec_i915_exit(struct snd_sof_dev *sdev); 569dd96dacaSLiam Girdwood 570dd96dacaSLiam Girdwood #else 571dd96dacaSLiam Girdwood 572dd96dacaSLiam Girdwood static inline void hda_codec_i915_get(struct snd_sof_dev *sdev) { } 573dd96dacaSLiam Girdwood static inline void hda_codec_i915_put(struct snd_sof_dev *sdev) { } 574dd96dacaSLiam Girdwood static inline int hda_codec_i915_init(struct snd_sof_dev *sdev) { return 0; } 575dd96dacaSLiam Girdwood static inline int hda_codec_i915_exit(struct snd_sof_dev *sdev) { return 0; } 576dd96dacaSLiam Girdwood 577dd96dacaSLiam Girdwood #endif /* CONFIG_SND_SOC_SOF_HDA && CONFIG_SND_SOC_HDAC_HDMI */ 578dd96dacaSLiam Girdwood 579dd96dacaSLiam Girdwood /* 580dd96dacaSLiam Girdwood * Trace Control. 581dd96dacaSLiam Girdwood */ 582dd96dacaSLiam Girdwood int hda_dsp_trace_init(struct snd_sof_dev *sdev, u32 *stream_tag); 583dd96dacaSLiam Girdwood int hda_dsp_trace_release(struct snd_sof_dev *sdev); 584dd96dacaSLiam Girdwood int hda_dsp_trace_trigger(struct snd_sof_dev *sdev, int cmd); 585dd96dacaSLiam Girdwood 586dd96dacaSLiam Girdwood /* common dai driver */ 587dd96dacaSLiam Girdwood extern struct snd_soc_dai_driver skl_dai[]; 588dd96dacaSLiam Girdwood 589dd96dacaSLiam Girdwood /* 590dd96dacaSLiam Girdwood * Platform Specific HW abstraction Ops. 591dd96dacaSLiam Girdwood */ 592dd96dacaSLiam Girdwood extern const struct snd_sof_dsp_ops sof_apl_ops; 593dd96dacaSLiam Girdwood extern const struct snd_sof_dsp_ops sof_cnl_ops; 594dd96dacaSLiam Girdwood extern const struct snd_sof_dsp_ops sof_skl_ops; 595dd96dacaSLiam Girdwood 596dd96dacaSLiam Girdwood extern const struct sof_intel_dsp_desc apl_chip_info; 597dd96dacaSLiam Girdwood extern const struct sof_intel_dsp_desc cnl_chip_info; 598dd96dacaSLiam Girdwood extern const struct sof_intel_dsp_desc skl_chip_info; 599630be964SZhu Yingjiang extern const struct sof_intel_dsp_desc icl_chip_info; 600dd96dacaSLiam Girdwood 601dd96dacaSLiam Girdwood #endif 602