1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 // 3 // This file is provided under a dual BSD/GPLv2 license. When using or 4 // redistributing this file, you may do so under either license. 5 // 6 // Copyright(c) 2018 Intel Corporation. All rights reserved. 7 // 8 // Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com> 9 // Ranjani Sridharan <ranjani.sridharan@linux.intel.com> 10 // Rander Wang <rander.wang@intel.com> 11 // Keyon Jie <yang.jie@linux.intel.com> 12 // 13 14 /* 15 * Hardware interface for generic Intel audio DSP HDA IP 16 */ 17 18 #include <sound/hdaudio_ext.h> 19 #include <sound/hda_register.h> 20 21 #include <linux/acpi.h> 22 #include <linux/module.h> 23 #include <linux/soundwire/sdw.h> 24 #include <linux/soundwire/sdw_intel.h> 25 #include <sound/intel-dsp-config.h> 26 #include <sound/intel-nhlt.h> 27 #include <sound/sof.h> 28 #include <sound/sof/xtensa.h> 29 #include <sound/hda-mlink.h> 30 #include "../sof-audio.h" 31 #include "../sof-pci-dev.h" 32 #include "../ops.h" 33 #include "hda.h" 34 35 #define CREATE_TRACE_POINTS 36 #include <trace/events/sof_intel.h> 37 38 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) 39 #include <sound/soc-acpi-intel-match.h> 40 #endif 41 42 /* platform specific devices */ 43 #include "shim.h" 44 45 #define EXCEPT_MAX_HDR_SIZE 0x400 46 #define HDA_EXT_ROM_STATUS_SIZE 8 47 48 static u32 hda_get_interface_mask(struct snd_sof_dev *sdev) 49 { 50 const struct sof_intel_dsp_desc *chip; 51 u32 interface_mask[2] = { 0 }; 52 53 chip = get_chip_info(sdev->pdata); 54 switch (chip->hw_ip_version) { 55 case SOF_INTEL_TANGIER: 56 case SOF_INTEL_BAYTRAIL: 57 case SOF_INTEL_BROADWELL: 58 interface_mask[0] = BIT(SOF_DAI_INTEL_SSP); 59 break; 60 case SOF_INTEL_CAVS_1_5: 61 case SOF_INTEL_CAVS_1_5_PLUS: 62 interface_mask[0] = BIT(SOF_DAI_INTEL_SSP) | BIT(SOF_DAI_INTEL_DMIC) | 63 BIT(SOF_DAI_INTEL_HDA); 64 interface_mask[1] = BIT(SOF_DAI_INTEL_HDA); 65 break; 66 case SOF_INTEL_CAVS_1_8: 67 case SOF_INTEL_CAVS_2_0: 68 case SOF_INTEL_CAVS_2_5: 69 case SOF_INTEL_ACE_1_0: 70 interface_mask[0] = BIT(SOF_DAI_INTEL_SSP) | BIT(SOF_DAI_INTEL_DMIC) | 71 BIT(SOF_DAI_INTEL_HDA) | BIT(SOF_DAI_INTEL_ALH); 72 interface_mask[1] = BIT(SOF_DAI_INTEL_HDA); 73 break; 74 default: 75 break; 76 } 77 78 return interface_mask[sdev->dspless_mode_selected]; 79 } 80 81 #if IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE) 82 83 /* 84 * The default for SoundWire clock stop quirks is to power gate the IP 85 * and do a Bus Reset, this will need to be modified when the DSP 86 * needs to remain in D0i3 so that the Master does not lose context 87 * and enumeration is not required on clock restart 88 */ 89 static int sdw_clock_stop_quirks = SDW_INTEL_CLK_STOP_BUS_RESET; 90 module_param(sdw_clock_stop_quirks, int, 0444); 91 MODULE_PARM_DESC(sdw_clock_stop_quirks, "SOF SoundWire clock stop quirks"); 92 93 static int sdw_params_stream(struct device *dev, 94 struct sdw_intel_stream_params_data *params_data) 95 { 96 struct snd_soc_dai *d = params_data->dai; 97 struct snd_soc_dapm_widget *w = snd_soc_dai_get_widget(d, params_data->stream); 98 struct snd_sof_dai_config_data data = { 0 }; 99 100 data.dai_index = (params_data->link_id << 8) | d->id; 101 data.dai_data = params_data->alh_stream_id; 102 103 return hda_dai_config(w, SOF_DAI_CONFIG_FLAGS_HW_PARAMS, &data); 104 } 105 106 struct sdw_intel_ops sdw_callback = { 107 .params_stream = sdw_params_stream, 108 }; 109 110 void hda_common_enable_sdw_irq(struct snd_sof_dev *sdev, bool enable) 111 { 112 struct sof_intel_hda_dev *hdev; 113 114 hdev = sdev->pdata->hw_pdata; 115 116 if (!hdev->sdw) 117 return; 118 119 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIC2, 120 HDA_DSP_REG_ADSPIC2_SNDW, 121 enable ? HDA_DSP_REG_ADSPIC2_SNDW : 0); 122 } 123 124 void hda_sdw_int_enable(struct snd_sof_dev *sdev, bool enable) 125 { 126 u32 interface_mask = hda_get_interface_mask(sdev); 127 const struct sof_intel_dsp_desc *chip; 128 129 if (!(interface_mask & BIT(SOF_DAI_INTEL_ALH))) 130 return; 131 132 chip = get_chip_info(sdev->pdata); 133 if (chip && chip->enable_sdw_irq) 134 chip->enable_sdw_irq(sdev, enable); 135 } 136 137 static int hda_sdw_acpi_scan(struct snd_sof_dev *sdev) 138 { 139 u32 interface_mask = hda_get_interface_mask(sdev); 140 struct sof_intel_hda_dev *hdev; 141 acpi_handle handle; 142 int ret; 143 144 if (!(interface_mask & BIT(SOF_DAI_INTEL_ALH))) 145 return -EINVAL; 146 147 handle = ACPI_HANDLE(sdev->dev); 148 149 /* save ACPI info for the probe step */ 150 hdev = sdev->pdata->hw_pdata; 151 152 ret = sdw_intel_acpi_scan(handle, &hdev->info); 153 if (ret < 0) 154 return -EINVAL; 155 156 return 0; 157 } 158 159 static int hda_sdw_probe(struct snd_sof_dev *sdev) 160 { 161 struct sof_intel_hda_dev *hdev; 162 struct sdw_intel_res res; 163 void *sdw; 164 165 hdev = sdev->pdata->hw_pdata; 166 167 memset(&res, 0, sizeof(res)); 168 169 res.hw_ops = &sdw_intel_cnl_hw_ops; 170 res.mmio_base = sdev->bar[HDA_DSP_BAR]; 171 res.shim_base = hdev->desc->sdw_shim_base; 172 res.alh_base = hdev->desc->sdw_alh_base; 173 res.irq = sdev->ipc_irq; 174 res.handle = hdev->info.handle; 175 res.parent = sdev->dev; 176 res.ops = &sdw_callback; 177 res.dev = sdev->dev; 178 res.clock_stop_quirks = sdw_clock_stop_quirks; 179 180 /* 181 * ops and arg fields are not populated for now, 182 * they will be needed when the DAI callbacks are 183 * provided 184 */ 185 186 /* we could filter links here if needed, e.g for quirks */ 187 res.count = hdev->info.count; 188 res.link_mask = hdev->info.link_mask; 189 190 sdw = sdw_intel_probe(&res); 191 if (!sdw) { 192 dev_err(sdev->dev, "error: SoundWire probe failed\n"); 193 return -EINVAL; 194 } 195 196 /* save context */ 197 hdev->sdw = sdw; 198 199 return 0; 200 } 201 202 int hda_sdw_check_lcount_common(struct snd_sof_dev *sdev) 203 { 204 struct sof_intel_hda_dev *hdev; 205 struct sdw_intel_ctx *ctx; 206 u32 caps; 207 208 hdev = sdev->pdata->hw_pdata; 209 ctx = hdev->sdw; 210 211 caps = snd_sof_dsp_read(sdev, HDA_DSP_BAR, ctx->shim_base + SDW_SHIM_LCAP); 212 caps &= SDW_SHIM_LCAP_LCOUNT_MASK; 213 214 /* Check HW supported vs property value */ 215 if (caps < ctx->count) { 216 dev_err(sdev->dev, 217 "%s: BIOS master count %d is larger than hardware capabilities %d\n", 218 __func__, ctx->count, caps); 219 return -EINVAL; 220 } 221 222 return 0; 223 } 224 225 int hda_sdw_check_lcount_ext(struct snd_sof_dev *sdev) 226 { 227 struct sof_intel_hda_dev *hdev; 228 struct sdw_intel_ctx *ctx; 229 struct hdac_bus *bus; 230 u32 slcount; 231 232 bus = sof_to_bus(sdev); 233 234 hdev = sdev->pdata->hw_pdata; 235 ctx = hdev->sdw; 236 237 slcount = hdac_bus_eml_get_count(bus, true, AZX_REG_ML_LEPTR_ID_SDW); 238 239 /* Check HW supported vs property value */ 240 if (slcount < ctx->count) { 241 dev_err(sdev->dev, 242 "%s: BIOS master count %d is larger than hardware capabilities %d\n", 243 __func__, ctx->count, slcount); 244 return -EINVAL; 245 } 246 247 return 0; 248 } 249 250 static int hda_sdw_check_lcount(struct snd_sof_dev *sdev) 251 { 252 const struct sof_intel_dsp_desc *chip; 253 254 chip = get_chip_info(sdev->pdata); 255 if (chip && chip->read_sdw_lcount) 256 return chip->read_sdw_lcount(sdev); 257 258 return 0; 259 } 260 261 int hda_sdw_startup(struct snd_sof_dev *sdev) 262 { 263 struct sof_intel_hda_dev *hdev; 264 struct snd_sof_pdata *pdata = sdev->pdata; 265 int ret; 266 267 hdev = sdev->pdata->hw_pdata; 268 269 if (!hdev->sdw) 270 return 0; 271 272 if (pdata->machine && !pdata->machine->mach_params.link_mask) 273 return 0; 274 275 ret = hda_sdw_check_lcount(sdev); 276 if (ret < 0) 277 return ret; 278 279 return sdw_intel_startup(hdev->sdw); 280 } 281 282 static int hda_sdw_exit(struct snd_sof_dev *sdev) 283 { 284 struct sof_intel_hda_dev *hdev; 285 286 hdev = sdev->pdata->hw_pdata; 287 288 hda_sdw_int_enable(sdev, false); 289 290 if (hdev->sdw) 291 sdw_intel_exit(hdev->sdw); 292 hdev->sdw = NULL; 293 294 return 0; 295 } 296 297 bool hda_common_check_sdw_irq(struct snd_sof_dev *sdev) 298 { 299 struct sof_intel_hda_dev *hdev; 300 bool ret = false; 301 u32 irq_status; 302 303 hdev = sdev->pdata->hw_pdata; 304 305 if (!hdev->sdw) 306 return ret; 307 308 /* store status */ 309 irq_status = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIS2); 310 311 /* invalid message ? */ 312 if (irq_status == 0xffffffff) 313 goto out; 314 315 /* SDW message ? */ 316 if (irq_status & HDA_DSP_REG_ADSPIS2_SNDW) 317 ret = true; 318 319 out: 320 return ret; 321 } 322 323 static bool hda_dsp_check_sdw_irq(struct snd_sof_dev *sdev) 324 { 325 u32 interface_mask = hda_get_interface_mask(sdev); 326 const struct sof_intel_dsp_desc *chip; 327 328 if (!(interface_mask & BIT(SOF_DAI_INTEL_ALH))) 329 return false; 330 331 chip = get_chip_info(sdev->pdata); 332 if (chip && chip->check_sdw_irq) 333 return chip->check_sdw_irq(sdev); 334 335 return false; 336 } 337 338 static irqreturn_t hda_dsp_sdw_thread(int irq, void *context) 339 { 340 return sdw_intel_thread(irq, context); 341 } 342 343 static bool hda_sdw_check_wakeen_irq(struct snd_sof_dev *sdev) 344 { 345 u32 interface_mask = hda_get_interface_mask(sdev); 346 struct sof_intel_hda_dev *hdev; 347 348 if (!(interface_mask & BIT(SOF_DAI_INTEL_ALH))) 349 return false; 350 351 hdev = sdev->pdata->hw_pdata; 352 if (hdev->sdw && 353 snd_sof_dsp_read(sdev, HDA_DSP_BAR, 354 hdev->desc->sdw_shim_base + SDW_SHIM_WAKESTS)) 355 return true; 356 357 return false; 358 } 359 360 void hda_sdw_process_wakeen(struct snd_sof_dev *sdev) 361 { 362 u32 interface_mask = hda_get_interface_mask(sdev); 363 struct sof_intel_hda_dev *hdev; 364 365 if (!(interface_mask & BIT(SOF_DAI_INTEL_ALH))) 366 return; 367 368 hdev = sdev->pdata->hw_pdata; 369 if (!hdev->sdw) 370 return; 371 372 sdw_intel_process_wakeen_event(hdev->sdw); 373 } 374 375 #else /* IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE) */ 376 static inline int hda_sdw_acpi_scan(struct snd_sof_dev *sdev) 377 { 378 return 0; 379 } 380 381 static inline int hda_sdw_probe(struct snd_sof_dev *sdev) 382 { 383 return 0; 384 } 385 386 static inline int hda_sdw_exit(struct snd_sof_dev *sdev) 387 { 388 return 0; 389 } 390 391 static inline bool hda_dsp_check_sdw_irq(struct snd_sof_dev *sdev) 392 { 393 return false; 394 } 395 396 static inline irqreturn_t hda_dsp_sdw_thread(int irq, void *context) 397 { 398 return IRQ_HANDLED; 399 } 400 401 static inline bool hda_sdw_check_wakeen_irq(struct snd_sof_dev *sdev) 402 { 403 return false; 404 } 405 406 #endif /* IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE) */ 407 408 /* 409 * Debug 410 */ 411 412 struct hda_dsp_msg_code { 413 u32 code; 414 const char *text; 415 }; 416 417 #if IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG) 418 static bool hda_use_msi = true; 419 module_param_named(use_msi, hda_use_msi, bool, 0444); 420 MODULE_PARM_DESC(use_msi, "SOF HDA use PCI MSI mode"); 421 #else 422 #define hda_use_msi (1) 423 #endif 424 425 int sof_hda_position_quirk = SOF_HDA_POSITION_QUIRK_USE_DPIB_REGISTERS; 426 module_param_named(position_quirk, sof_hda_position_quirk, int, 0444); 427 MODULE_PARM_DESC(position_quirk, "SOF HDaudio position quirk"); 428 429 static char *hda_model; 430 module_param(hda_model, charp, 0444); 431 MODULE_PARM_DESC(hda_model, "Use the given HDA board model."); 432 433 static int dmic_num_override = -1; 434 module_param_named(dmic_num, dmic_num_override, int, 0444); 435 MODULE_PARM_DESC(dmic_num, "SOF HDA DMIC number"); 436 437 static int mclk_id_override = -1; 438 module_param_named(mclk_id, mclk_id_override, int, 0444); 439 MODULE_PARM_DESC(mclk_id, "SOF SSP mclk_id"); 440 441 static const struct hda_dsp_msg_code hda_dsp_rom_fw_error_texts[] = { 442 {HDA_DSP_ROM_CSE_ERROR, "error: cse error"}, 443 {HDA_DSP_ROM_CSE_WRONG_RESPONSE, "error: cse wrong response"}, 444 {HDA_DSP_ROM_IMR_TO_SMALL, "error: IMR too small"}, 445 {HDA_DSP_ROM_BASE_FW_NOT_FOUND, "error: base fw not found"}, 446 {HDA_DSP_ROM_CSE_VALIDATION_FAILED, "error: signature verification failed"}, 447 {HDA_DSP_ROM_IPC_FATAL_ERROR, "error: ipc fatal error"}, 448 {HDA_DSP_ROM_L2_CACHE_ERROR, "error: L2 cache error"}, 449 {HDA_DSP_ROM_LOAD_OFFSET_TO_SMALL, "error: load offset too small"}, 450 {HDA_DSP_ROM_API_PTR_INVALID, "error: API ptr invalid"}, 451 {HDA_DSP_ROM_BASEFW_INCOMPAT, "error: base fw incompatible"}, 452 {HDA_DSP_ROM_UNHANDLED_INTERRUPT, "error: unhandled interrupt"}, 453 {HDA_DSP_ROM_MEMORY_HOLE_ECC, "error: ECC memory hole"}, 454 {HDA_DSP_ROM_KERNEL_EXCEPTION, "error: kernel exception"}, 455 {HDA_DSP_ROM_USER_EXCEPTION, "error: user exception"}, 456 {HDA_DSP_ROM_UNEXPECTED_RESET, "error: unexpected reset"}, 457 {HDA_DSP_ROM_NULL_FW_ENTRY, "error: null FW entry point"}, 458 }; 459 460 #define FSR_ROM_STATE_ENTRY(state) {FSR_STATE_ROM_##state, #state} 461 static const struct hda_dsp_msg_code fsr_rom_state_names[] = { 462 FSR_ROM_STATE_ENTRY(INIT), 463 FSR_ROM_STATE_ENTRY(INIT_DONE), 464 FSR_ROM_STATE_ENTRY(CSE_MANIFEST_LOADED), 465 FSR_ROM_STATE_ENTRY(FW_MANIFEST_LOADED), 466 FSR_ROM_STATE_ENTRY(FW_FW_LOADED), 467 FSR_ROM_STATE_ENTRY(FW_ENTERED), 468 FSR_ROM_STATE_ENTRY(VERIFY_FEATURE_MASK), 469 FSR_ROM_STATE_ENTRY(GET_LOAD_OFFSET), 470 FSR_ROM_STATE_ENTRY(FETCH_ROM_EXT), 471 FSR_ROM_STATE_ENTRY(FETCH_ROM_EXT_DONE), 472 /* CSE states */ 473 FSR_ROM_STATE_ENTRY(CSE_IMR_REQUEST), 474 FSR_ROM_STATE_ENTRY(CSE_IMR_GRANTED), 475 FSR_ROM_STATE_ENTRY(CSE_VALIDATE_IMAGE_REQUEST), 476 FSR_ROM_STATE_ENTRY(CSE_IMAGE_VALIDATED), 477 FSR_ROM_STATE_ENTRY(CSE_IPC_IFACE_INIT), 478 FSR_ROM_STATE_ENTRY(CSE_IPC_RESET_PHASE_1), 479 FSR_ROM_STATE_ENTRY(CSE_IPC_OPERATIONAL_ENTRY), 480 FSR_ROM_STATE_ENTRY(CSE_IPC_OPERATIONAL), 481 FSR_ROM_STATE_ENTRY(CSE_IPC_DOWN), 482 }; 483 484 #define FSR_BRINGUP_STATE_ENTRY(state) {FSR_STATE_BRINGUP_##state, #state} 485 static const struct hda_dsp_msg_code fsr_bringup_state_names[] = { 486 FSR_BRINGUP_STATE_ENTRY(INIT), 487 FSR_BRINGUP_STATE_ENTRY(INIT_DONE), 488 FSR_BRINGUP_STATE_ENTRY(HPSRAM_LOAD), 489 FSR_BRINGUP_STATE_ENTRY(UNPACK_START), 490 FSR_BRINGUP_STATE_ENTRY(IMR_RESTORE), 491 FSR_BRINGUP_STATE_ENTRY(FW_ENTERED), 492 }; 493 494 #define FSR_WAIT_STATE_ENTRY(state) {FSR_WAIT_FOR_##state, #state} 495 static const struct hda_dsp_msg_code fsr_wait_state_names[] = { 496 FSR_WAIT_STATE_ENTRY(IPC_BUSY), 497 FSR_WAIT_STATE_ENTRY(IPC_DONE), 498 FSR_WAIT_STATE_ENTRY(CACHE_INVALIDATION), 499 FSR_WAIT_STATE_ENTRY(LP_SRAM_OFF), 500 FSR_WAIT_STATE_ENTRY(DMA_BUFFER_FULL), 501 FSR_WAIT_STATE_ENTRY(CSE_CSR), 502 }; 503 504 #define FSR_MODULE_NAME_ENTRY(mod) [FSR_MOD_##mod] = #mod 505 static const char * const fsr_module_names[] = { 506 FSR_MODULE_NAME_ENTRY(ROM), 507 FSR_MODULE_NAME_ENTRY(ROM_BYP), 508 FSR_MODULE_NAME_ENTRY(BASE_FW), 509 FSR_MODULE_NAME_ENTRY(LP_BOOT), 510 FSR_MODULE_NAME_ENTRY(BRNGUP), 511 FSR_MODULE_NAME_ENTRY(ROM_EXT), 512 }; 513 514 static const char * 515 hda_dsp_get_state_text(u32 code, const struct hda_dsp_msg_code *msg_code, 516 size_t array_size) 517 { 518 int i; 519 520 for (i = 0; i < array_size; i++) { 521 if (code == msg_code[i].code) 522 return msg_code[i].text; 523 } 524 525 return NULL; 526 } 527 528 static void hda_dsp_get_state(struct snd_sof_dev *sdev, const char *level) 529 { 530 const struct sof_intel_dsp_desc *chip = get_chip_info(sdev->pdata); 531 const char *state_text, *error_text, *module_text; 532 u32 fsr, state, wait_state, module, error_code; 533 534 fsr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, chip->rom_status_reg); 535 state = FSR_TO_STATE_CODE(fsr); 536 wait_state = FSR_TO_WAIT_STATE_CODE(fsr); 537 module = FSR_TO_MODULE_CODE(fsr); 538 539 if (module > FSR_MOD_ROM_EXT) 540 module_text = "unknown"; 541 else 542 module_text = fsr_module_names[module]; 543 544 if (module == FSR_MOD_BRNGUP) 545 state_text = hda_dsp_get_state_text(state, fsr_bringup_state_names, 546 ARRAY_SIZE(fsr_bringup_state_names)); 547 else 548 state_text = hda_dsp_get_state_text(state, fsr_rom_state_names, 549 ARRAY_SIZE(fsr_rom_state_names)); 550 551 /* not for us, must be generic sof message */ 552 if (!state_text) { 553 dev_printk(level, sdev->dev, "%#010x: unknown ROM status value\n", fsr); 554 return; 555 } 556 557 if (wait_state) { 558 const char *wait_state_text; 559 560 wait_state_text = hda_dsp_get_state_text(wait_state, fsr_wait_state_names, 561 ARRAY_SIZE(fsr_wait_state_names)); 562 if (!wait_state_text) 563 wait_state_text = "unknown"; 564 565 dev_printk(level, sdev->dev, 566 "%#010x: module: %s, state: %s, waiting for: %s, %s\n", 567 fsr, module_text, state_text, wait_state_text, 568 fsr & FSR_HALTED ? "not running" : "running"); 569 } else { 570 dev_printk(level, sdev->dev, "%#010x: module: %s, state: %s, %s\n", 571 fsr, module_text, state_text, 572 fsr & FSR_HALTED ? "not running" : "running"); 573 } 574 575 error_code = snd_sof_dsp_read(sdev, HDA_DSP_BAR, chip->rom_status_reg + 4); 576 if (!error_code) 577 return; 578 579 error_text = hda_dsp_get_state_text(error_code, hda_dsp_rom_fw_error_texts, 580 ARRAY_SIZE(hda_dsp_rom_fw_error_texts)); 581 if (!error_text) 582 error_text = "unknown"; 583 584 if (state == FSR_STATE_FW_ENTERED) 585 dev_printk(level, sdev->dev, "status code: %#x (%s)\n", error_code, 586 error_text); 587 else 588 dev_printk(level, sdev->dev, "error code: %#x (%s)\n", error_code, 589 error_text); 590 } 591 592 static void hda_dsp_get_registers(struct snd_sof_dev *sdev, 593 struct sof_ipc_dsp_oops_xtensa *xoops, 594 struct sof_ipc_panic_info *panic_info, 595 u32 *stack, size_t stack_words) 596 { 597 u32 offset = sdev->dsp_oops_offset; 598 599 /* first read registers */ 600 sof_mailbox_read(sdev, offset, xoops, sizeof(*xoops)); 601 602 /* note: variable AR register array is not read */ 603 604 /* then get panic info */ 605 if (xoops->arch_hdr.totalsize > EXCEPT_MAX_HDR_SIZE) { 606 dev_err(sdev->dev, "invalid header size 0x%x. FW oops is bogus\n", 607 xoops->arch_hdr.totalsize); 608 return; 609 } 610 offset += xoops->arch_hdr.totalsize; 611 sof_block_read(sdev, sdev->mmio_bar, offset, 612 panic_info, sizeof(*panic_info)); 613 614 /* then get the stack */ 615 offset += sizeof(*panic_info); 616 sof_block_read(sdev, sdev->mmio_bar, offset, stack, 617 stack_words * sizeof(u32)); 618 } 619 620 /* dump the first 8 dwords representing the extended ROM status */ 621 static void hda_dsp_dump_ext_rom_status(struct snd_sof_dev *sdev, const char *level, 622 u32 flags) 623 { 624 const struct sof_intel_dsp_desc *chip; 625 char msg[128]; 626 int len = 0; 627 u32 value; 628 int i; 629 630 chip = get_chip_info(sdev->pdata); 631 for (i = 0; i < HDA_EXT_ROM_STATUS_SIZE; i++) { 632 value = snd_sof_dsp_read(sdev, HDA_DSP_BAR, chip->rom_status_reg + i * 0x4); 633 len += scnprintf(msg + len, sizeof(msg) - len, " 0x%x", value); 634 } 635 636 dev_printk(level, sdev->dev, "extended rom status: %s", msg); 637 638 } 639 640 void hda_dsp_dump(struct snd_sof_dev *sdev, u32 flags) 641 { 642 char *level = (flags & SOF_DBG_DUMP_OPTIONAL) ? KERN_DEBUG : KERN_ERR; 643 struct sof_ipc_dsp_oops_xtensa xoops; 644 struct sof_ipc_panic_info panic_info; 645 u32 stack[HDA_DSP_STACK_DUMP_SIZE]; 646 647 /* print ROM/FW status */ 648 hda_dsp_get_state(sdev, level); 649 650 /* The firmware register dump only available with IPC3 */ 651 if (flags & SOF_DBG_DUMP_REGS && sdev->pdata->ipc_type == SOF_IPC) { 652 u32 status = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_SRAM_REG_FW_STATUS); 653 u32 panic = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_SRAM_REG_FW_TRACEP); 654 655 hda_dsp_get_registers(sdev, &xoops, &panic_info, stack, 656 HDA_DSP_STACK_DUMP_SIZE); 657 sof_print_oops_and_stack(sdev, level, status, panic, &xoops, 658 &panic_info, stack, HDA_DSP_STACK_DUMP_SIZE); 659 } else { 660 hda_dsp_dump_ext_rom_status(sdev, level, flags); 661 } 662 } 663 664 static bool hda_check_ipc_irq(struct snd_sof_dev *sdev) 665 { 666 const struct sof_intel_dsp_desc *chip; 667 668 chip = get_chip_info(sdev->pdata); 669 if (chip && chip->check_ipc_irq) 670 return chip->check_ipc_irq(sdev); 671 672 return false; 673 } 674 675 void hda_ipc_irq_dump(struct snd_sof_dev *sdev) 676 { 677 u32 adspis; 678 u32 intsts; 679 u32 intctl; 680 u32 ppsts; 681 u8 rirbsts; 682 683 /* read key IRQ stats and config registers */ 684 adspis = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIS); 685 intsts = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTSTS); 686 intctl = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL); 687 ppsts = snd_sof_dsp_read(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPSTS); 688 rirbsts = snd_sof_dsp_read8(sdev, HDA_DSP_HDA_BAR, AZX_REG_RIRBSTS); 689 690 dev_err(sdev->dev, "hda irq intsts 0x%8.8x intlctl 0x%8.8x rirb %2.2x\n", 691 intsts, intctl, rirbsts); 692 dev_err(sdev->dev, "dsp irq ppsts 0x%8.8x adspis 0x%8.8x\n", ppsts, adspis); 693 } 694 695 void hda_ipc_dump(struct snd_sof_dev *sdev) 696 { 697 u32 hipcie; 698 u32 hipct; 699 u32 hipcctl; 700 701 hda_ipc_irq_dump(sdev); 702 703 /* read IPC status */ 704 hipcie = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCIE); 705 hipct = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCT); 706 hipcctl = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCCTL); 707 708 /* dump the IPC regs */ 709 /* TODO: parse the raw msg */ 710 dev_err(sdev->dev, "host status 0x%8.8x dsp status 0x%8.8x mask 0x%8.8x\n", 711 hipcie, hipct, hipcctl); 712 } 713 714 void hda_ipc4_dump(struct snd_sof_dev *sdev) 715 { 716 u32 hipci, hipcie, hipct, hipcte, hipcctl; 717 718 hda_ipc_irq_dump(sdev); 719 720 hipci = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCI); 721 hipcie = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCIE); 722 hipct = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCT); 723 hipcte = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCTE); 724 hipcctl = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCCTL); 725 726 /* dump the IPC regs */ 727 /* TODO: parse the raw msg */ 728 dev_err(sdev->dev, "Host IPC initiator: %#x|%#x, target: %#x|%#x, ctl: %#x\n", 729 hipci, hipcie, hipct, hipcte, hipcctl); 730 } 731 732 bool hda_ipc4_tx_is_busy(struct snd_sof_dev *sdev) 733 { 734 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 735 const struct sof_intel_dsp_desc *chip = hda->desc; 736 u32 val; 737 738 val = snd_sof_dsp_read(sdev, HDA_DSP_BAR, chip->ipc_req); 739 740 return !!(val & chip->ipc_req_mask); 741 } 742 743 static int hda_init(struct snd_sof_dev *sdev) 744 { 745 struct hda_bus *hbus; 746 struct hdac_bus *bus; 747 struct pci_dev *pci = to_pci_dev(sdev->dev); 748 int ret; 749 750 hbus = sof_to_hbus(sdev); 751 bus = sof_to_bus(sdev); 752 753 /* HDA bus init */ 754 sof_hda_bus_init(sdev, &pci->dev); 755 756 if (sof_hda_position_quirk == SOF_HDA_POSITION_QUIRK_USE_DPIB_REGISTERS) 757 bus->use_posbuf = 0; 758 else 759 bus->use_posbuf = 1; 760 bus->bdl_pos_adj = 0; 761 bus->sync_write = 1; 762 763 mutex_init(&hbus->prepare_mutex); 764 hbus->pci = pci; 765 hbus->mixer_assigned = -1; 766 hbus->modelname = hda_model; 767 768 /* initialise hdac bus */ 769 bus->addr = pci_resource_start(pci, 0); 770 bus->remap_addr = pci_ioremap_bar(pci, 0); 771 if (!bus->remap_addr) { 772 dev_err(bus->dev, "error: ioremap error\n"); 773 return -ENXIO; 774 } 775 776 /* HDA base */ 777 sdev->bar[HDA_DSP_HDA_BAR] = bus->remap_addr; 778 779 /* init i915 and HDMI codecs */ 780 ret = hda_codec_i915_init(sdev); 781 if (ret < 0) 782 dev_warn(sdev->dev, "init of i915 and HDMI codec failed\n"); 783 784 /* get controller capabilities */ 785 ret = hda_dsp_ctrl_get_caps(sdev); 786 if (ret < 0) 787 dev_err(sdev->dev, "error: get caps error\n"); 788 789 return ret; 790 } 791 792 static int check_dmic_num(struct snd_sof_dev *sdev) 793 { 794 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata; 795 struct nhlt_acpi_table *nhlt; 796 int dmic_num = 0; 797 798 nhlt = hdev->nhlt; 799 if (nhlt) 800 dmic_num = intel_nhlt_get_dmic_geo(sdev->dev, nhlt); 801 802 /* allow for module parameter override */ 803 if (dmic_num_override != -1) { 804 dev_dbg(sdev->dev, 805 "overriding DMICs detected in NHLT tables %d by kernel param %d\n", 806 dmic_num, dmic_num_override); 807 dmic_num = dmic_num_override; 808 } 809 810 if (dmic_num < 0 || dmic_num > 4) { 811 dev_dbg(sdev->dev, "invalid dmic_number %d\n", dmic_num); 812 dmic_num = 0; 813 } 814 815 return dmic_num; 816 } 817 818 static int check_nhlt_ssp_mask(struct snd_sof_dev *sdev) 819 { 820 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata; 821 struct nhlt_acpi_table *nhlt; 822 int ssp_mask = 0; 823 824 nhlt = hdev->nhlt; 825 if (!nhlt) 826 return ssp_mask; 827 828 if (intel_nhlt_has_endpoint_type(nhlt, NHLT_LINK_SSP)) { 829 ssp_mask = intel_nhlt_ssp_endpoint_mask(nhlt, NHLT_DEVICE_I2S); 830 if (ssp_mask) 831 dev_info(sdev->dev, "NHLT_DEVICE_I2S detected, ssp_mask %#x\n", ssp_mask); 832 } 833 834 return ssp_mask; 835 } 836 837 static int check_nhlt_ssp_mclk_mask(struct snd_sof_dev *sdev, int ssp_num) 838 { 839 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata; 840 struct nhlt_acpi_table *nhlt; 841 842 nhlt = hdev->nhlt; 843 if (!nhlt) 844 return 0; 845 846 return intel_nhlt_ssp_mclk_mask(nhlt, ssp_num); 847 } 848 849 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC) || IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE) 850 851 static const char *fixup_tplg_name(struct snd_sof_dev *sdev, 852 const char *sof_tplg_filename, 853 const char *idisp_str, 854 const char *dmic_str) 855 { 856 const char *tplg_filename = NULL; 857 char *filename, *tmp; 858 const char *split_ext; 859 860 filename = kstrdup(sof_tplg_filename, GFP_KERNEL); 861 if (!filename) 862 return NULL; 863 864 /* this assumes a .tplg extension */ 865 tmp = filename; 866 split_ext = strsep(&tmp, "."); 867 if (split_ext) 868 tplg_filename = devm_kasprintf(sdev->dev, GFP_KERNEL, 869 "%s%s%s.tplg", 870 split_ext, idisp_str, dmic_str); 871 kfree(filename); 872 873 return tplg_filename; 874 } 875 876 static int dmic_detect_topology_fixup(struct snd_sof_dev *sdev, 877 const char **tplg_filename, 878 const char *idisp_str, 879 int *dmic_found, 880 bool tplg_fixup) 881 { 882 const char *dmic_str; 883 int dmic_num; 884 885 /* first check for DMICs (using NHLT or module parameter) */ 886 dmic_num = check_dmic_num(sdev); 887 888 switch (dmic_num) { 889 case 1: 890 dmic_str = "-1ch"; 891 break; 892 case 2: 893 dmic_str = "-2ch"; 894 break; 895 case 3: 896 dmic_str = "-3ch"; 897 break; 898 case 4: 899 dmic_str = "-4ch"; 900 break; 901 default: 902 dmic_num = 0; 903 dmic_str = ""; 904 break; 905 } 906 907 if (tplg_fixup) { 908 const char *default_tplg_filename = *tplg_filename; 909 const char *fixed_tplg_filename; 910 911 fixed_tplg_filename = fixup_tplg_name(sdev, default_tplg_filename, 912 idisp_str, dmic_str); 913 if (!fixed_tplg_filename) 914 return -ENOMEM; 915 *tplg_filename = fixed_tplg_filename; 916 } 917 918 dev_info(sdev->dev, "DMICs detected in NHLT tables: %d\n", dmic_num); 919 *dmic_found = dmic_num; 920 921 return 0; 922 } 923 #endif 924 925 static int hda_init_caps(struct snd_sof_dev *sdev) 926 { 927 u32 interface_mask = hda_get_interface_mask(sdev); 928 struct hdac_bus *bus = sof_to_bus(sdev); 929 struct snd_sof_pdata *pdata = sdev->pdata; 930 struct sof_intel_hda_dev *hdev = pdata->hw_pdata; 931 u32 link_mask; 932 int ret = 0; 933 934 /* check if dsp is there */ 935 if (bus->ppcap) 936 dev_dbg(sdev->dev, "PP capability, will probe DSP later.\n"); 937 938 /* Init HDA controller after i915 init */ 939 ret = hda_dsp_ctrl_init_chip(sdev); 940 if (ret < 0) { 941 dev_err(bus->dev, "error: init chip failed with ret: %d\n", 942 ret); 943 return ret; 944 } 945 946 hda_bus_ml_init(bus); 947 948 /* Skip SoundWire if it is not supported */ 949 if (!(interface_mask & BIT(SOF_DAI_INTEL_ALH))) 950 goto skip_soundwire; 951 952 /* scan SoundWire capabilities exposed by DSDT */ 953 ret = hda_sdw_acpi_scan(sdev); 954 if (ret < 0) { 955 dev_dbg(sdev->dev, "skipping SoundWire, not detected with ACPI scan\n"); 956 goto skip_soundwire; 957 } 958 959 link_mask = hdev->info.link_mask; 960 if (!link_mask) { 961 dev_dbg(sdev->dev, "skipping SoundWire, no links enabled\n"); 962 goto skip_soundwire; 963 } 964 965 /* 966 * probe/allocate SoundWire resources. 967 * The hardware configuration takes place in hda_sdw_startup 968 * after power rails are enabled. 969 * It's entirely possible to have a mix of I2S/DMIC/SoundWire 970 * devices, so we allocate the resources in all cases. 971 */ 972 ret = hda_sdw_probe(sdev); 973 if (ret < 0) { 974 dev_err(sdev->dev, "error: SoundWire probe error\n"); 975 return ret; 976 } 977 978 skip_soundwire: 979 980 /* create codec instances */ 981 hda_codec_probe_bus(sdev); 982 983 if (!HDA_IDISP_CODEC(bus->codec_mask)) 984 hda_codec_i915_display_power(sdev, false); 985 986 hda_bus_ml_put_all(bus); 987 988 return 0; 989 } 990 991 static irqreturn_t hda_dsp_interrupt_handler(int irq, void *context) 992 { 993 struct snd_sof_dev *sdev = context; 994 995 /* 996 * Get global interrupt status. It includes all hardware interrupt 997 * sources in the Intel HD Audio controller. 998 */ 999 if (snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTSTS) & 1000 SOF_HDA_INTSTS_GIS) { 1001 1002 /* disable GIE interrupt */ 1003 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, 1004 SOF_HDA_INTCTL, 1005 SOF_HDA_INT_GLOBAL_EN, 1006 0); 1007 1008 return IRQ_WAKE_THREAD; 1009 } 1010 1011 return IRQ_NONE; 1012 } 1013 1014 static irqreturn_t hda_dsp_interrupt_thread(int irq, void *context) 1015 { 1016 struct snd_sof_dev *sdev = context; 1017 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata; 1018 1019 /* deal with streams and controller first */ 1020 if (hda_dsp_check_stream_irq(sdev)) { 1021 trace_sof_intel_hda_irq(sdev, "stream"); 1022 hda_dsp_stream_threaded_handler(irq, sdev); 1023 } 1024 1025 if (hda_check_ipc_irq(sdev)) { 1026 trace_sof_intel_hda_irq(sdev, "ipc"); 1027 sof_ops(sdev)->irq_thread(irq, sdev); 1028 } 1029 1030 if (hda_dsp_check_sdw_irq(sdev)) { 1031 trace_sof_intel_hda_irq(sdev, "sdw"); 1032 hda_dsp_sdw_thread(irq, hdev->sdw); 1033 } 1034 1035 if (hda_sdw_check_wakeen_irq(sdev)) { 1036 trace_sof_intel_hda_irq(sdev, "wakeen"); 1037 hda_sdw_process_wakeen(sdev); 1038 } 1039 1040 hda_codec_check_for_state_change(sdev); 1041 1042 /* enable GIE interrupt */ 1043 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, 1044 SOF_HDA_INTCTL, 1045 SOF_HDA_INT_GLOBAL_EN, 1046 SOF_HDA_INT_GLOBAL_EN); 1047 1048 return IRQ_HANDLED; 1049 } 1050 1051 int hda_dsp_probe(struct snd_sof_dev *sdev) 1052 { 1053 struct pci_dev *pci = to_pci_dev(sdev->dev); 1054 struct sof_intel_hda_dev *hdev; 1055 struct hdac_bus *bus; 1056 const struct sof_intel_dsp_desc *chip; 1057 int ret = 0; 1058 1059 if (!sdev->dspless_mode_selected) { 1060 /* 1061 * detect DSP by checking class/subclass/prog-id information 1062 * class=04 subclass 03 prog-if 00: no DSP, legacy driver is required 1063 * class=04 subclass 01 prog-if 00: DSP is present 1064 * (and may be required e.g. for DMIC or SSP support) 1065 * class=04 subclass 03 prog-if 80: either of DSP or legacy mode works 1066 */ 1067 if (pci->class == 0x040300) { 1068 dev_err(sdev->dev, "the DSP is not enabled on this platform, aborting probe\n"); 1069 return -ENODEV; 1070 } else if (pci->class != 0x040100 && pci->class != 0x040380) { 1071 dev_err(sdev->dev, "unknown PCI class/subclass/prog-if 0x%06x found, aborting probe\n", 1072 pci->class); 1073 return -ENODEV; 1074 } 1075 dev_info(sdev->dev, "DSP detected with PCI class/subclass/prog-if 0x%06x\n", 1076 pci->class); 1077 } 1078 1079 chip = get_chip_info(sdev->pdata); 1080 if (!chip) { 1081 dev_err(sdev->dev, "error: no such device supported, chip id:%x\n", 1082 pci->device); 1083 ret = -EIO; 1084 goto err; 1085 } 1086 1087 sdev->num_cores = chip->cores_num; 1088 1089 hdev = devm_kzalloc(sdev->dev, sizeof(*hdev), GFP_KERNEL); 1090 if (!hdev) 1091 return -ENOMEM; 1092 sdev->pdata->hw_pdata = hdev; 1093 hdev->desc = chip; 1094 1095 hdev->dmic_dev = platform_device_register_data(sdev->dev, "dmic-codec", 1096 PLATFORM_DEVID_NONE, 1097 NULL, 0); 1098 if (IS_ERR(hdev->dmic_dev)) { 1099 dev_err(sdev->dev, "error: failed to create DMIC device\n"); 1100 return PTR_ERR(hdev->dmic_dev); 1101 } 1102 1103 /* 1104 * use position update IPC if either it is forced 1105 * or we don't have other choice 1106 */ 1107 #if IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG_FORCE_IPC_POSITION) 1108 hdev->no_ipc_position = 0; 1109 #else 1110 hdev->no_ipc_position = sof_ops(sdev)->pcm_pointer ? 1 : 0; 1111 #endif 1112 1113 if (sdev->dspless_mode_selected) 1114 hdev->no_ipc_position = 1; 1115 1116 /* set up HDA base */ 1117 bus = sof_to_bus(sdev); 1118 ret = hda_init(sdev); 1119 if (ret < 0) 1120 goto hdac_bus_unmap; 1121 1122 if (sdev->dspless_mode_selected) 1123 goto skip_dsp_setup; 1124 1125 /* DSP base */ 1126 sdev->bar[HDA_DSP_BAR] = pci_ioremap_bar(pci, HDA_DSP_BAR); 1127 if (!sdev->bar[HDA_DSP_BAR]) { 1128 dev_err(sdev->dev, "error: ioremap error\n"); 1129 ret = -ENXIO; 1130 goto hdac_bus_unmap; 1131 } 1132 1133 sdev->mmio_bar = HDA_DSP_BAR; 1134 sdev->mailbox_bar = HDA_DSP_BAR; 1135 skip_dsp_setup: 1136 1137 /* allow 64bit DMA address if supported by H/W */ 1138 if (dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(64))) { 1139 dev_dbg(sdev->dev, "DMA mask is 32 bit\n"); 1140 dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(32)); 1141 } 1142 dma_set_max_seg_size(&pci->dev, UINT_MAX); 1143 1144 /* init streams */ 1145 ret = hda_dsp_stream_init(sdev); 1146 if (ret < 0) { 1147 dev_err(sdev->dev, "error: failed to init streams\n"); 1148 /* 1149 * not all errors are due to memory issues, but trying 1150 * to free everything does not harm 1151 */ 1152 goto free_streams; 1153 } 1154 1155 /* 1156 * register our IRQ 1157 * let's try to enable msi firstly 1158 * if it fails, use legacy interrupt mode 1159 * TODO: support msi multiple vectors 1160 */ 1161 if (hda_use_msi && pci_alloc_irq_vectors(pci, 1, 1, PCI_IRQ_MSI) > 0) { 1162 dev_info(sdev->dev, "use msi interrupt mode\n"); 1163 sdev->ipc_irq = pci_irq_vector(pci, 0); 1164 /* initialised to "false" by kzalloc() */ 1165 sdev->msi_enabled = true; 1166 } 1167 1168 if (!sdev->msi_enabled) { 1169 dev_info(sdev->dev, "use legacy interrupt mode\n"); 1170 /* 1171 * in IO-APIC mode, hda->irq and ipc_irq are using the same 1172 * irq number of pci->irq 1173 */ 1174 sdev->ipc_irq = pci->irq; 1175 } 1176 1177 dev_dbg(sdev->dev, "using IPC IRQ %d\n", sdev->ipc_irq); 1178 ret = request_threaded_irq(sdev->ipc_irq, hda_dsp_interrupt_handler, 1179 hda_dsp_interrupt_thread, 1180 IRQF_SHARED, "AudioDSP", sdev); 1181 if (ret < 0) { 1182 dev_err(sdev->dev, "error: failed to register IPC IRQ %d\n", 1183 sdev->ipc_irq); 1184 goto free_irq_vector; 1185 } 1186 1187 pci_set_master(pci); 1188 synchronize_irq(pci->irq); 1189 1190 /* 1191 * clear TCSEL to clear playback on some HD Audio 1192 * codecs. PCI TCSEL is defined in the Intel manuals. 1193 */ 1194 snd_sof_pci_update_bits(sdev, PCI_TCSEL, 0x07, 0); 1195 1196 /* init HDA capabilities */ 1197 ret = hda_init_caps(sdev); 1198 if (ret < 0) 1199 goto free_ipc_irq; 1200 1201 if (!sdev->dspless_mode_selected) { 1202 /* enable ppcap interrupt */ 1203 hda_dsp_ctrl_ppcap_enable(sdev, true); 1204 hda_dsp_ctrl_ppcap_int_enable(sdev, true); 1205 1206 /* set default mailbox offset for FW ready message */ 1207 sdev->dsp_box.offset = HDA_DSP_MBOX_UPLINK_OFFSET; 1208 1209 INIT_DELAYED_WORK(&hdev->d0i3_work, hda_dsp_d0i3_work); 1210 } 1211 1212 init_waitqueue_head(&hdev->waitq); 1213 1214 hdev->nhlt = intel_nhlt_init(sdev->dev); 1215 1216 return 0; 1217 1218 free_ipc_irq: 1219 free_irq(sdev->ipc_irq, sdev); 1220 free_irq_vector: 1221 if (sdev->msi_enabled) 1222 pci_free_irq_vectors(pci); 1223 free_streams: 1224 hda_dsp_stream_free(sdev); 1225 /* dsp_unmap: not currently used */ 1226 if (!sdev->dspless_mode_selected) 1227 iounmap(sdev->bar[HDA_DSP_BAR]); 1228 hdac_bus_unmap: 1229 platform_device_unregister(hdev->dmic_dev); 1230 iounmap(bus->remap_addr); 1231 hda_codec_i915_exit(sdev); 1232 err: 1233 return ret; 1234 } 1235 1236 int hda_dsp_remove(struct snd_sof_dev *sdev) 1237 { 1238 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 1239 const struct sof_intel_dsp_desc *chip = hda->desc; 1240 struct hdac_bus *bus = sof_to_bus(sdev); 1241 struct pci_dev *pci = to_pci_dev(sdev->dev); 1242 struct nhlt_acpi_table *nhlt = hda->nhlt; 1243 1244 if (nhlt) 1245 intel_nhlt_free(nhlt); 1246 1247 if (!sdev->dspless_mode_selected) 1248 /* cancel any attempt for DSP D0I3 */ 1249 cancel_delayed_work_sync(&hda->d0i3_work); 1250 1251 hda_codec_device_remove(sdev); 1252 1253 hda_sdw_exit(sdev); 1254 1255 if (!IS_ERR_OR_NULL(hda->dmic_dev)) 1256 platform_device_unregister(hda->dmic_dev); 1257 1258 if (!sdev->dspless_mode_selected) { 1259 /* disable DSP IRQ */ 1260 snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL, 1261 SOF_HDA_PPCTL_PIE, 0); 1262 } 1263 1264 /* disable CIE and GIE interrupts */ 1265 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL, 1266 SOF_HDA_INT_CTRL_EN | SOF_HDA_INT_GLOBAL_EN, 0); 1267 1268 if (sdev->dspless_mode_selected) 1269 goto skip_disable_dsp; 1270 1271 /* no need to check for error as the DSP will be disabled anyway */ 1272 if (chip && chip->power_down_dsp) 1273 chip->power_down_dsp(sdev); 1274 1275 /* disable DSP */ 1276 snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL, 1277 SOF_HDA_PPCTL_GPROCEN, 0); 1278 1279 skip_disable_dsp: 1280 free_irq(sdev->ipc_irq, sdev); 1281 if (sdev->msi_enabled) 1282 pci_free_irq_vectors(pci); 1283 1284 hda_dsp_stream_free(sdev); 1285 1286 hda_bus_ml_free(sof_to_bus(sdev)); 1287 1288 if (!sdev->dspless_mode_selected) 1289 iounmap(sdev->bar[HDA_DSP_BAR]); 1290 1291 iounmap(bus->remap_addr); 1292 1293 sof_hda_bus_exit(sdev); 1294 1295 hda_codec_i915_exit(sdev); 1296 1297 return 0; 1298 } 1299 1300 int hda_power_down_dsp(struct snd_sof_dev *sdev) 1301 { 1302 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 1303 const struct sof_intel_dsp_desc *chip = hda->desc; 1304 1305 return hda_dsp_core_reset_power_down(sdev, chip->host_managed_cores_mask); 1306 } 1307 1308 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC) 1309 static void hda_generic_machine_select(struct snd_sof_dev *sdev, 1310 struct snd_soc_acpi_mach **mach) 1311 { 1312 struct hdac_bus *bus = sof_to_bus(sdev); 1313 struct snd_soc_acpi_mach_params *mach_params; 1314 struct snd_soc_acpi_mach *hda_mach; 1315 struct snd_sof_pdata *pdata = sdev->pdata; 1316 const char *tplg_filename; 1317 const char *idisp_str; 1318 int dmic_num = 0; 1319 int codec_num = 0; 1320 int ret; 1321 int i; 1322 1323 /* codec detection */ 1324 if (!bus->codec_mask) { 1325 dev_info(bus->dev, "no hda codecs found!\n"); 1326 } else { 1327 dev_info(bus->dev, "hda codecs found, mask %lx\n", 1328 bus->codec_mask); 1329 1330 for (i = 0; i < HDA_MAX_CODECS; i++) { 1331 if (bus->codec_mask & (1 << i)) 1332 codec_num++; 1333 } 1334 1335 /* 1336 * If no machine driver is found, then: 1337 * 1338 * generic hda machine driver can handle: 1339 * - one HDMI codec, and/or 1340 * - one external HDAudio codec 1341 */ 1342 if (!*mach && codec_num <= 2) { 1343 bool tplg_fixup; 1344 1345 hda_mach = snd_soc_acpi_intel_hda_machines; 1346 1347 dev_info(bus->dev, "using HDA machine driver %s now\n", 1348 hda_mach->drv_name); 1349 1350 if (codec_num == 1 && HDA_IDISP_CODEC(bus->codec_mask)) 1351 idisp_str = "-idisp"; 1352 else 1353 idisp_str = ""; 1354 1355 /* topology: use the info from hda_machines */ 1356 if (pdata->tplg_filename) { 1357 tplg_fixup = false; 1358 tplg_filename = pdata->tplg_filename; 1359 } else { 1360 tplg_fixup = true; 1361 tplg_filename = hda_mach->sof_tplg_filename; 1362 } 1363 ret = dmic_detect_topology_fixup(sdev, &tplg_filename, idisp_str, &dmic_num, 1364 tplg_fixup); 1365 if (ret < 0) 1366 return; 1367 1368 hda_mach->mach_params.dmic_num = dmic_num; 1369 pdata->tplg_filename = tplg_filename; 1370 1371 if (codec_num == 2 || 1372 (codec_num == 1 && !HDA_IDISP_CODEC(bus->codec_mask))) { 1373 /* 1374 * Prevent SoundWire links from starting when an external 1375 * HDaudio codec is used 1376 */ 1377 hda_mach->mach_params.link_mask = 0; 1378 } else { 1379 /* 1380 * Allow SoundWire links to start when no external HDaudio codec 1381 * was detected. This will not create a SoundWire card but 1382 * will help detect if any SoundWire codec reports as ATTACHED. 1383 */ 1384 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata; 1385 1386 hda_mach->mach_params.link_mask = hdev->info.link_mask; 1387 } 1388 1389 *mach = hda_mach; 1390 } 1391 } 1392 1393 /* used by hda machine driver to create dai links */ 1394 if (*mach) { 1395 mach_params = &(*mach)->mach_params; 1396 mach_params->codec_mask = bus->codec_mask; 1397 mach_params->common_hdmi_codec_drv = true; 1398 } 1399 } 1400 #else 1401 static void hda_generic_machine_select(struct snd_sof_dev *sdev, 1402 struct snd_soc_acpi_mach **mach) 1403 { 1404 } 1405 #endif 1406 1407 #if IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE) 1408 1409 #define SDW_CODEC_ADR_MASK(_adr) ((_adr) & (SDW_DISCO_LINK_ID_MASK | SDW_VERSION_MASK | \ 1410 SDW_MFG_ID_MASK | SDW_PART_ID_MASK)) 1411 1412 /* Check if all Slaves defined on the link can be found */ 1413 static bool link_slaves_found(struct snd_sof_dev *sdev, 1414 const struct snd_soc_acpi_link_adr *link, 1415 struct sdw_intel_ctx *sdw) 1416 { 1417 struct hdac_bus *bus = sof_to_bus(sdev); 1418 struct sdw_intel_slave_id *ids = sdw->ids; 1419 int num_slaves = sdw->num_slaves; 1420 unsigned int part_id, link_id, unique_id, mfg_id, version; 1421 int i, j, k; 1422 1423 for (i = 0; i < link->num_adr; i++) { 1424 u64 adr = link->adr_d[i].adr; 1425 int reported_part_count = 0; 1426 1427 mfg_id = SDW_MFG_ID(adr); 1428 part_id = SDW_PART_ID(adr); 1429 link_id = SDW_DISCO_LINK_ID(adr); 1430 version = SDW_VERSION(adr); 1431 1432 for (j = 0; j < num_slaves; j++) { 1433 /* find out how many identical parts were reported on that link */ 1434 if (ids[j].link_id == link_id && 1435 ids[j].id.part_id == part_id && 1436 ids[j].id.mfg_id == mfg_id && 1437 ids[j].id.sdw_version == version) 1438 reported_part_count++; 1439 } 1440 1441 for (j = 0; j < num_slaves; j++) { 1442 int expected_part_count = 0; 1443 1444 if (ids[j].link_id != link_id || 1445 ids[j].id.part_id != part_id || 1446 ids[j].id.mfg_id != mfg_id || 1447 ids[j].id.sdw_version != version) 1448 continue; 1449 1450 /* find out how many identical parts are expected */ 1451 for (k = 0; k < link->num_adr; k++) { 1452 u64 adr2 = link->adr_d[k].adr; 1453 1454 if (SDW_CODEC_ADR_MASK(adr2) == SDW_CODEC_ADR_MASK(adr)) 1455 expected_part_count++; 1456 } 1457 1458 if (reported_part_count == expected_part_count) { 1459 /* 1460 * we have to check unique id 1461 * if there is more than one 1462 * Slave on the link 1463 */ 1464 unique_id = SDW_UNIQUE_ID(adr); 1465 if (reported_part_count == 1 || 1466 ids[j].id.unique_id == unique_id) { 1467 dev_dbg(bus->dev, "found %x at link %d\n", 1468 part_id, link_id); 1469 break; 1470 } 1471 } else { 1472 dev_dbg(bus->dev, "part %x reported %d expected %d on link %d, skipping\n", 1473 part_id, reported_part_count, expected_part_count, link_id); 1474 } 1475 } 1476 if (j == num_slaves) { 1477 dev_dbg(bus->dev, 1478 "Slave %x not found\n", 1479 part_id); 1480 return false; 1481 } 1482 } 1483 return true; 1484 } 1485 1486 static struct snd_soc_acpi_mach *hda_sdw_machine_select(struct snd_sof_dev *sdev) 1487 { 1488 struct snd_sof_pdata *pdata = sdev->pdata; 1489 const struct snd_soc_acpi_link_adr *link; 1490 struct snd_soc_acpi_mach *mach; 1491 struct sof_intel_hda_dev *hdev; 1492 u32 link_mask; 1493 int i; 1494 1495 hdev = pdata->hw_pdata; 1496 link_mask = hdev->info.link_mask; 1497 1498 /* 1499 * Select SoundWire machine driver if needed using the 1500 * alternate tables. This case deals with SoundWire-only 1501 * machines, for mixed cases with I2C/I2S the detection relies 1502 * on the HID list. 1503 */ 1504 if (link_mask) { 1505 for (mach = pdata->desc->alt_machines; 1506 mach && mach->link_mask; mach++) { 1507 /* 1508 * On some platforms such as Up Extreme all links 1509 * are enabled but only one link can be used by 1510 * external codec. Instead of exact match of two masks, 1511 * first check whether link_mask of mach is subset of 1512 * link_mask supported by hw and then go on searching 1513 * link_adr 1514 */ 1515 if (~link_mask & mach->link_mask) 1516 continue; 1517 1518 /* No need to match adr if there is no links defined */ 1519 if (!mach->links) 1520 break; 1521 1522 link = mach->links; 1523 for (i = 0; i < hdev->info.count && link->num_adr; 1524 i++, link++) { 1525 /* 1526 * Try next machine if any expected Slaves 1527 * are not found on this link. 1528 */ 1529 if (!link_slaves_found(sdev, link, hdev->sdw)) 1530 break; 1531 } 1532 /* Found if all Slaves are checked */ 1533 if (i == hdev->info.count || !link->num_adr) 1534 break; 1535 } 1536 if (mach && mach->link_mask) { 1537 int dmic_num = 0; 1538 bool tplg_fixup; 1539 const char *tplg_filename; 1540 1541 mach->mach_params.links = mach->links; 1542 mach->mach_params.link_mask = mach->link_mask; 1543 mach->mach_params.platform = dev_name(sdev->dev); 1544 1545 if (pdata->tplg_filename) { 1546 tplg_fixup = false; 1547 } else { 1548 tplg_fixup = true; 1549 tplg_filename = mach->sof_tplg_filename; 1550 } 1551 1552 /* 1553 * DMICs use up to 4 pins and are typically pin-muxed with SoundWire 1554 * link 2 and 3, or link 1 and 2, thus we only try to enable dmics 1555 * if all conditions are true: 1556 * a) 2 or fewer links are used by SoundWire 1557 * b) the NHLT table reports the presence of microphones 1558 */ 1559 if (hweight_long(mach->link_mask) <= 2) { 1560 int ret; 1561 1562 ret = dmic_detect_topology_fixup(sdev, &tplg_filename, "", 1563 &dmic_num, tplg_fixup); 1564 if (ret < 0) 1565 return NULL; 1566 } 1567 if (tplg_fixup) 1568 pdata->tplg_filename = tplg_filename; 1569 mach->mach_params.dmic_num = dmic_num; 1570 1571 dev_dbg(sdev->dev, 1572 "SoundWire machine driver %s topology %s\n", 1573 mach->drv_name, 1574 pdata->tplg_filename); 1575 1576 return mach; 1577 } 1578 1579 dev_info(sdev->dev, "No SoundWire machine driver found\n"); 1580 } 1581 1582 return NULL; 1583 } 1584 #else 1585 static struct snd_soc_acpi_mach *hda_sdw_machine_select(struct snd_sof_dev *sdev) 1586 { 1587 return NULL; 1588 } 1589 #endif 1590 1591 void hda_set_mach_params(struct snd_soc_acpi_mach *mach, 1592 struct snd_sof_dev *sdev) 1593 { 1594 struct snd_sof_pdata *pdata = sdev->pdata; 1595 const struct sof_dev_desc *desc = pdata->desc; 1596 struct snd_soc_acpi_mach_params *mach_params; 1597 1598 mach_params = &mach->mach_params; 1599 mach_params->platform = dev_name(sdev->dev); 1600 if (IS_ENABLED(CONFIG_SND_SOC_SOF_NOCODEC_DEBUG_SUPPORT) && 1601 sof_debug_check_flag(SOF_DBG_FORCE_NOCODEC)) 1602 mach_params->num_dai_drivers = SOF_SKL_NUM_DAIS_NOCODEC; 1603 else 1604 mach_params->num_dai_drivers = desc->ops->num_drv; 1605 mach_params->dai_drivers = desc->ops->drv; 1606 } 1607 1608 struct snd_soc_acpi_mach *hda_machine_select(struct snd_sof_dev *sdev) 1609 { 1610 u32 interface_mask = hda_get_interface_mask(sdev); 1611 struct snd_sof_pdata *sof_pdata = sdev->pdata; 1612 const struct sof_dev_desc *desc = sof_pdata->desc; 1613 struct snd_soc_acpi_mach *mach = NULL; 1614 const char *tplg_filename; 1615 1616 /* Try I2S or DMIC if it is supported */ 1617 if (interface_mask & (BIT(SOF_DAI_INTEL_SSP) | BIT(SOF_DAI_INTEL_DMIC))) 1618 mach = snd_soc_acpi_find_machine(desc->machines); 1619 1620 if (mach) { 1621 bool add_extension = false; 1622 bool tplg_fixup = false; 1623 1624 /* 1625 * If tplg file name is overridden, use it instead of 1626 * the one set in mach table 1627 */ 1628 if (!sof_pdata->tplg_filename) { 1629 sof_pdata->tplg_filename = mach->sof_tplg_filename; 1630 tplg_fixup = true; 1631 } 1632 1633 /* report to machine driver if any DMICs are found */ 1634 mach->mach_params.dmic_num = check_dmic_num(sdev); 1635 1636 if (tplg_fixup && 1637 mach->tplg_quirk_mask & SND_SOC_ACPI_TPLG_INTEL_DMIC_NUMBER && 1638 mach->mach_params.dmic_num) { 1639 tplg_filename = devm_kasprintf(sdev->dev, GFP_KERNEL, 1640 "%s%s%d%s", 1641 sof_pdata->tplg_filename, 1642 "-dmic", 1643 mach->mach_params.dmic_num, 1644 "ch"); 1645 if (!tplg_filename) 1646 return NULL; 1647 1648 sof_pdata->tplg_filename = tplg_filename; 1649 add_extension = true; 1650 } 1651 1652 if (mach->link_mask) { 1653 mach->mach_params.links = mach->links; 1654 mach->mach_params.link_mask = mach->link_mask; 1655 } 1656 1657 /* report SSP link mask to machine driver */ 1658 mach->mach_params.i2s_link_mask = check_nhlt_ssp_mask(sdev); 1659 1660 if (tplg_fixup && 1661 mach->tplg_quirk_mask & SND_SOC_ACPI_TPLG_INTEL_SSP_NUMBER && 1662 mach->mach_params.i2s_link_mask) { 1663 const struct sof_intel_dsp_desc *chip = get_chip_info(sdev->pdata); 1664 int ssp_num; 1665 int mclk_mask; 1666 1667 if (hweight_long(mach->mach_params.i2s_link_mask) > 1 && 1668 !(mach->tplg_quirk_mask & SND_SOC_ACPI_TPLG_INTEL_SSP_MSB)) 1669 dev_warn(sdev->dev, "More than one SSP exposed by NHLT, choosing MSB\n"); 1670 1671 /* fls returns 1-based results, SSPs indices are 0-based */ 1672 ssp_num = fls(mach->mach_params.i2s_link_mask) - 1; 1673 1674 if (ssp_num >= chip->ssp_count) { 1675 dev_err(sdev->dev, "Invalid SSP %d, max on this platform is %d\n", 1676 ssp_num, chip->ssp_count); 1677 return NULL; 1678 } 1679 1680 tplg_filename = devm_kasprintf(sdev->dev, GFP_KERNEL, 1681 "%s%s%d", 1682 sof_pdata->tplg_filename, 1683 "-ssp", 1684 ssp_num); 1685 if (!tplg_filename) 1686 return NULL; 1687 1688 sof_pdata->tplg_filename = tplg_filename; 1689 add_extension = true; 1690 1691 mclk_mask = check_nhlt_ssp_mclk_mask(sdev, ssp_num); 1692 1693 if (mclk_mask < 0) { 1694 dev_err(sdev->dev, "Invalid MCLK configuration\n"); 1695 return NULL; 1696 } 1697 1698 dev_dbg(sdev->dev, "MCLK mask %#x found in NHLT\n", mclk_mask); 1699 1700 if (mclk_mask) { 1701 dev_info(sdev->dev, "Overriding topology with MCLK mask %#x from NHLT\n", mclk_mask); 1702 sdev->mclk_id_override = true; 1703 sdev->mclk_id_quirk = (mclk_mask & BIT(0)) ? 0 : 1; 1704 } 1705 } 1706 1707 if (tplg_fixup && add_extension) { 1708 tplg_filename = devm_kasprintf(sdev->dev, GFP_KERNEL, 1709 "%s%s", 1710 sof_pdata->tplg_filename, 1711 ".tplg"); 1712 if (!tplg_filename) 1713 return NULL; 1714 1715 sof_pdata->tplg_filename = tplg_filename; 1716 } 1717 1718 /* check if mclk_id should be modified from topology defaults */ 1719 if (mclk_id_override >= 0) { 1720 dev_info(sdev->dev, "Overriding topology with MCLK %d from kernel_parameter\n", mclk_id_override); 1721 sdev->mclk_id_override = true; 1722 sdev->mclk_id_quirk = mclk_id_override; 1723 } 1724 } 1725 1726 /* If I2S fails, try SoundWire if it is supported */ 1727 if (!mach && (interface_mask & BIT(SOF_DAI_INTEL_ALH))) 1728 mach = hda_sdw_machine_select(sdev); 1729 1730 /* 1731 * Choose HDA generic machine driver if mach is NULL. 1732 * Otherwise, set certain mach params. 1733 */ 1734 hda_generic_machine_select(sdev, &mach); 1735 if (!mach) 1736 dev_warn(sdev->dev, "warning: No matching ASoC machine driver found\n"); 1737 1738 return mach; 1739 } 1740 1741 int hda_pci_intel_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) 1742 { 1743 int ret; 1744 1745 ret = snd_intel_dsp_driver_probe(pci); 1746 if (ret != SND_INTEL_DSP_DRIVER_ANY && ret != SND_INTEL_DSP_DRIVER_SOF) { 1747 dev_dbg(&pci->dev, "SOF PCI driver not selected, aborting probe\n"); 1748 return -ENODEV; 1749 } 1750 1751 return sof_pci_probe(pci, pci_id); 1752 } 1753 EXPORT_SYMBOL_NS(hda_pci_intel_probe, SND_SOC_SOF_INTEL_HDA_COMMON); 1754 1755 int hda_register_clients(struct snd_sof_dev *sdev) 1756 { 1757 return hda_probes_register(sdev); 1758 } 1759 1760 void hda_unregister_clients(struct snd_sof_dev *sdev) 1761 { 1762 hda_probes_unregister(sdev); 1763 } 1764 1765 MODULE_LICENSE("Dual BSD/GPL"); 1766 MODULE_IMPORT_NS(SND_SOC_SOF_PCI_DEV); 1767 MODULE_IMPORT_NS(SND_SOC_SOF_HDA_AUDIO_CODEC); 1768 MODULE_IMPORT_NS(SND_SOC_SOF_HDA_AUDIO_CODEC_I915); 1769 MODULE_IMPORT_NS(SND_SOC_SOF_XTENSA); 1770 MODULE_IMPORT_NS(SND_INTEL_SOUNDWIRE_ACPI); 1771 MODULE_IMPORT_NS(SOUNDWIRE_INTEL_INIT); 1772 MODULE_IMPORT_NS(SOUNDWIRE_INTEL); 1773 MODULE_IMPORT_NS(SND_SOC_SOF_HDA_MLINK); 1774