1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 // 3 // This file is provided under a dual BSD/GPLv2 license. When using or 4 // redistributing this file, you may do so under either license. 5 // 6 // Copyright(c) 2018 Intel Corporation. All rights reserved. 7 // 8 // Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com> 9 // Ranjani Sridharan <ranjani.sridharan@linux.intel.com> 10 // Rander Wang <rander.wang@intel.com> 11 // Keyon Jie <yang.jie@linux.intel.com> 12 // 13 14 /* 15 * Hardware interface for generic Intel audio DSP HDA IP 16 */ 17 18 #include <sound/hdaudio_ext.h> 19 #include <sound/hda_register.h> 20 21 #include <linux/acpi.h> 22 #include <linux/module.h> 23 #include <linux/soundwire/sdw.h> 24 #include <linux/soundwire/sdw_intel.h> 25 #include <sound/intel-dsp-config.h> 26 #include <sound/intel-nhlt.h> 27 #include <sound/sof.h> 28 #include <sound/sof/xtensa.h> 29 #include <sound/hda-mlink.h> 30 #include "../sof-audio.h" 31 #include "../sof-pci-dev.h" 32 #include "../ops.h" 33 #include "hda.h" 34 35 #define CREATE_TRACE_POINTS 36 #include <trace/events/sof_intel.h> 37 38 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) 39 #include <sound/soc-acpi-intel-match.h> 40 #endif 41 42 /* platform specific devices */ 43 #include "shim.h" 44 45 #define EXCEPT_MAX_HDR_SIZE 0x400 46 #define HDA_EXT_ROM_STATUS_SIZE 8 47 48 static u32 hda_get_interface_mask(struct snd_sof_dev *sdev) 49 { 50 const struct sof_intel_dsp_desc *chip; 51 u32 interface_mask[2] = { 0 }; 52 53 chip = get_chip_info(sdev->pdata); 54 switch (chip->hw_ip_version) { 55 case SOF_INTEL_TANGIER: 56 case SOF_INTEL_BAYTRAIL: 57 case SOF_INTEL_BROADWELL: 58 interface_mask[0] = BIT(SOF_DAI_INTEL_SSP); 59 break; 60 case SOF_INTEL_CAVS_1_5: 61 case SOF_INTEL_CAVS_1_5_PLUS: 62 interface_mask[0] = BIT(SOF_DAI_INTEL_SSP) | BIT(SOF_DAI_INTEL_DMIC) | 63 BIT(SOF_DAI_INTEL_HDA); 64 interface_mask[1] = BIT(SOF_DAI_INTEL_HDA); 65 break; 66 case SOF_INTEL_CAVS_1_8: 67 case SOF_INTEL_CAVS_2_0: 68 case SOF_INTEL_CAVS_2_5: 69 case SOF_INTEL_ACE_1_0: 70 interface_mask[0] = BIT(SOF_DAI_INTEL_SSP) | BIT(SOF_DAI_INTEL_DMIC) | 71 BIT(SOF_DAI_INTEL_HDA) | BIT(SOF_DAI_INTEL_ALH); 72 interface_mask[1] = BIT(SOF_DAI_INTEL_HDA); 73 break; 74 default: 75 break; 76 } 77 78 return interface_mask[sdev->dspless_mode_selected]; 79 } 80 81 #if IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE) 82 83 /* 84 * The default for SoundWire clock stop quirks is to power gate the IP 85 * and do a Bus Reset, this will need to be modified when the DSP 86 * needs to remain in D0i3 so that the Master does not lose context 87 * and enumeration is not required on clock restart 88 */ 89 static int sdw_clock_stop_quirks = SDW_INTEL_CLK_STOP_BUS_RESET; 90 module_param(sdw_clock_stop_quirks, int, 0444); 91 MODULE_PARM_DESC(sdw_clock_stop_quirks, "SOF SoundWire clock stop quirks"); 92 93 static int sdw_params_stream(struct device *dev, 94 struct sdw_intel_stream_params_data *params_data) 95 { 96 struct snd_soc_dai *d = params_data->dai; 97 struct snd_soc_dapm_widget *w = snd_soc_dai_get_widget(d, params_data->substream->stream); 98 struct snd_sof_dai_config_data data = { 0 }; 99 100 data.dai_index = (params_data->link_id << 8) | d->id; 101 data.dai_data = params_data->alh_stream_id; 102 103 return hda_dai_config(w, SOF_DAI_CONFIG_FLAGS_HW_PARAMS, &data); 104 } 105 106 struct sdw_intel_ops sdw_callback = { 107 .params_stream = sdw_params_stream, 108 }; 109 110 void hda_common_enable_sdw_irq(struct snd_sof_dev *sdev, bool enable) 111 { 112 struct sof_intel_hda_dev *hdev; 113 114 hdev = sdev->pdata->hw_pdata; 115 116 if (!hdev->sdw) 117 return; 118 119 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIC2, 120 HDA_DSP_REG_ADSPIC2_SNDW, 121 enable ? HDA_DSP_REG_ADSPIC2_SNDW : 0); 122 } 123 124 void hda_sdw_int_enable(struct snd_sof_dev *sdev, bool enable) 125 { 126 u32 interface_mask = hda_get_interface_mask(sdev); 127 const struct sof_intel_dsp_desc *chip; 128 129 if (!(interface_mask & BIT(SOF_DAI_INTEL_ALH))) 130 return; 131 132 chip = get_chip_info(sdev->pdata); 133 if (chip && chip->enable_sdw_irq) 134 chip->enable_sdw_irq(sdev, enable); 135 } 136 137 static int hda_sdw_acpi_scan(struct snd_sof_dev *sdev) 138 { 139 u32 interface_mask = hda_get_interface_mask(sdev); 140 struct sof_intel_hda_dev *hdev; 141 acpi_handle handle; 142 int ret; 143 144 if (!(interface_mask & BIT(SOF_DAI_INTEL_ALH))) 145 return -EINVAL; 146 147 handle = ACPI_HANDLE(sdev->dev); 148 149 /* save ACPI info for the probe step */ 150 hdev = sdev->pdata->hw_pdata; 151 152 ret = sdw_intel_acpi_scan(handle, &hdev->info); 153 if (ret < 0) 154 return -EINVAL; 155 156 return 0; 157 } 158 159 static int hda_sdw_probe(struct snd_sof_dev *sdev) 160 { 161 const struct sof_intel_dsp_desc *chip; 162 struct sof_intel_hda_dev *hdev; 163 struct sdw_intel_res res; 164 void *sdw; 165 166 hdev = sdev->pdata->hw_pdata; 167 168 memset(&res, 0, sizeof(res)); 169 170 chip = get_chip_info(sdev->pdata); 171 if (chip->hw_ip_version < SOF_INTEL_ACE_2_0) { 172 res.mmio_base = sdev->bar[HDA_DSP_BAR]; 173 res.hw_ops = &sdw_intel_cnl_hw_ops; 174 res.shim_base = hdev->desc->sdw_shim_base; 175 res.alh_base = hdev->desc->sdw_alh_base; 176 res.ext = false; 177 } else { 178 /* 179 * retrieve eml_lock needed to protect shared registers 180 * in the HDaudio multi-link areas 181 */ 182 res.eml_lock = hdac_bus_eml_get_mutex(sof_to_bus(sdev), true, 183 AZX_REG_ML_LEPTR_ID_SDW); 184 if (!res.eml_lock) 185 return -ENODEV; 186 187 res.mmio_base = sdev->bar[HDA_DSP_HDA_BAR]; 188 /* 189 * the SHIM and SoundWire register offsets are link-specific 190 * and will be determined when adding auxiliary devices 191 */ 192 res.hw_ops = &sdw_intel_lnl_hw_ops; 193 res.ext = true; 194 } 195 res.irq = sdev->ipc_irq; 196 res.handle = hdev->info.handle; 197 res.parent = sdev->dev; 198 res.ops = &sdw_callback; 199 res.dev = sdev->dev; 200 res.clock_stop_quirks = sdw_clock_stop_quirks; 201 res.hbus = sof_to_bus(sdev); 202 203 /* 204 * ops and arg fields are not populated for now, 205 * they will be needed when the DAI callbacks are 206 * provided 207 */ 208 209 /* we could filter links here if needed, e.g for quirks */ 210 res.count = hdev->info.count; 211 res.link_mask = hdev->info.link_mask; 212 213 sdw = sdw_intel_probe(&res); 214 if (!sdw) { 215 dev_err(sdev->dev, "error: SoundWire probe failed\n"); 216 return -EINVAL; 217 } 218 219 /* save context */ 220 hdev->sdw = sdw; 221 222 return 0; 223 } 224 225 int hda_sdw_check_lcount_common(struct snd_sof_dev *sdev) 226 { 227 struct sof_intel_hda_dev *hdev; 228 struct sdw_intel_ctx *ctx; 229 u32 caps; 230 231 hdev = sdev->pdata->hw_pdata; 232 ctx = hdev->sdw; 233 234 caps = snd_sof_dsp_read(sdev, HDA_DSP_BAR, ctx->shim_base + SDW_SHIM_LCAP); 235 caps &= SDW_SHIM_LCAP_LCOUNT_MASK; 236 237 /* Check HW supported vs property value */ 238 if (caps < ctx->count) { 239 dev_err(sdev->dev, 240 "%s: BIOS master count %d is larger than hardware capabilities %d\n", 241 __func__, ctx->count, caps); 242 return -EINVAL; 243 } 244 245 return 0; 246 } 247 248 int hda_sdw_check_lcount_ext(struct snd_sof_dev *sdev) 249 { 250 struct sof_intel_hda_dev *hdev; 251 struct sdw_intel_ctx *ctx; 252 struct hdac_bus *bus; 253 u32 slcount; 254 255 bus = sof_to_bus(sdev); 256 257 hdev = sdev->pdata->hw_pdata; 258 ctx = hdev->sdw; 259 260 slcount = hdac_bus_eml_get_count(bus, true, AZX_REG_ML_LEPTR_ID_SDW); 261 262 /* Check HW supported vs property value */ 263 if (slcount < ctx->count) { 264 dev_err(sdev->dev, 265 "%s: BIOS master count %d is larger than hardware capabilities %d\n", 266 __func__, ctx->count, slcount); 267 return -EINVAL; 268 } 269 270 return 0; 271 } 272 273 static int hda_sdw_check_lcount(struct snd_sof_dev *sdev) 274 { 275 const struct sof_intel_dsp_desc *chip; 276 277 chip = get_chip_info(sdev->pdata); 278 if (chip && chip->read_sdw_lcount) 279 return chip->read_sdw_lcount(sdev); 280 281 return 0; 282 } 283 284 int hda_sdw_startup(struct snd_sof_dev *sdev) 285 { 286 struct sof_intel_hda_dev *hdev; 287 struct snd_sof_pdata *pdata = sdev->pdata; 288 int ret; 289 290 hdev = sdev->pdata->hw_pdata; 291 292 if (!hdev->sdw) 293 return 0; 294 295 if (pdata->machine && !pdata->machine->mach_params.link_mask) 296 return 0; 297 298 ret = hda_sdw_check_lcount(sdev); 299 if (ret < 0) 300 return ret; 301 302 return sdw_intel_startup(hdev->sdw); 303 } 304 305 static int hda_sdw_exit(struct snd_sof_dev *sdev) 306 { 307 struct sof_intel_hda_dev *hdev; 308 309 hdev = sdev->pdata->hw_pdata; 310 311 hda_sdw_int_enable(sdev, false); 312 313 if (hdev->sdw) 314 sdw_intel_exit(hdev->sdw); 315 hdev->sdw = NULL; 316 317 return 0; 318 } 319 320 bool hda_common_check_sdw_irq(struct snd_sof_dev *sdev) 321 { 322 struct sof_intel_hda_dev *hdev; 323 bool ret = false; 324 u32 irq_status; 325 326 hdev = sdev->pdata->hw_pdata; 327 328 if (!hdev->sdw) 329 return ret; 330 331 /* store status */ 332 irq_status = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIS2); 333 334 /* invalid message ? */ 335 if (irq_status == 0xffffffff) 336 goto out; 337 338 /* SDW message ? */ 339 if (irq_status & HDA_DSP_REG_ADSPIS2_SNDW) 340 ret = true; 341 342 out: 343 return ret; 344 } 345 346 static bool hda_dsp_check_sdw_irq(struct snd_sof_dev *sdev) 347 { 348 u32 interface_mask = hda_get_interface_mask(sdev); 349 const struct sof_intel_dsp_desc *chip; 350 351 if (!(interface_mask & BIT(SOF_DAI_INTEL_ALH))) 352 return false; 353 354 chip = get_chip_info(sdev->pdata); 355 if (chip && chip->check_sdw_irq) 356 return chip->check_sdw_irq(sdev); 357 358 return false; 359 } 360 361 static irqreturn_t hda_dsp_sdw_thread(int irq, void *context) 362 { 363 return sdw_intel_thread(irq, context); 364 } 365 366 static bool hda_sdw_check_wakeen_irq(struct snd_sof_dev *sdev) 367 { 368 u32 interface_mask = hda_get_interface_mask(sdev); 369 struct sof_intel_hda_dev *hdev; 370 371 if (!(interface_mask & BIT(SOF_DAI_INTEL_ALH))) 372 return false; 373 374 hdev = sdev->pdata->hw_pdata; 375 if (hdev->sdw && 376 snd_sof_dsp_read(sdev, HDA_DSP_BAR, 377 hdev->desc->sdw_shim_base + SDW_SHIM_WAKESTS)) 378 return true; 379 380 return false; 381 } 382 383 void hda_sdw_process_wakeen(struct snd_sof_dev *sdev) 384 { 385 u32 interface_mask = hda_get_interface_mask(sdev); 386 struct sof_intel_hda_dev *hdev; 387 388 if (!(interface_mask & BIT(SOF_DAI_INTEL_ALH))) 389 return; 390 391 hdev = sdev->pdata->hw_pdata; 392 if (!hdev->sdw) 393 return; 394 395 sdw_intel_process_wakeen_event(hdev->sdw); 396 } 397 398 #else /* IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE) */ 399 static inline int hda_sdw_acpi_scan(struct snd_sof_dev *sdev) 400 { 401 return 0; 402 } 403 404 static inline int hda_sdw_probe(struct snd_sof_dev *sdev) 405 { 406 return 0; 407 } 408 409 static inline int hda_sdw_exit(struct snd_sof_dev *sdev) 410 { 411 return 0; 412 } 413 414 static inline bool hda_dsp_check_sdw_irq(struct snd_sof_dev *sdev) 415 { 416 return false; 417 } 418 419 static inline irqreturn_t hda_dsp_sdw_thread(int irq, void *context) 420 { 421 return IRQ_HANDLED; 422 } 423 424 static inline bool hda_sdw_check_wakeen_irq(struct snd_sof_dev *sdev) 425 { 426 return false; 427 } 428 429 #endif /* IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE) */ 430 431 /* 432 * Debug 433 */ 434 435 struct hda_dsp_msg_code { 436 u32 code; 437 const char *text; 438 }; 439 440 #if IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG) 441 static bool hda_use_msi = true; 442 module_param_named(use_msi, hda_use_msi, bool, 0444); 443 MODULE_PARM_DESC(use_msi, "SOF HDA use PCI MSI mode"); 444 #else 445 #define hda_use_msi (1) 446 #endif 447 448 int sof_hda_position_quirk = SOF_HDA_POSITION_QUIRK_USE_DPIB_REGISTERS; 449 module_param_named(position_quirk, sof_hda_position_quirk, int, 0444); 450 MODULE_PARM_DESC(position_quirk, "SOF HDaudio position quirk"); 451 452 static char *hda_model; 453 module_param(hda_model, charp, 0444); 454 MODULE_PARM_DESC(hda_model, "Use the given HDA board model."); 455 456 static int dmic_num_override = -1; 457 module_param_named(dmic_num, dmic_num_override, int, 0444); 458 MODULE_PARM_DESC(dmic_num, "SOF HDA DMIC number"); 459 460 static int mclk_id_override = -1; 461 module_param_named(mclk_id, mclk_id_override, int, 0444); 462 MODULE_PARM_DESC(mclk_id, "SOF SSP mclk_id"); 463 464 static const struct hda_dsp_msg_code hda_dsp_rom_fw_error_texts[] = { 465 {HDA_DSP_ROM_CSE_ERROR, "error: cse error"}, 466 {HDA_DSP_ROM_CSE_WRONG_RESPONSE, "error: cse wrong response"}, 467 {HDA_DSP_ROM_IMR_TO_SMALL, "error: IMR too small"}, 468 {HDA_DSP_ROM_BASE_FW_NOT_FOUND, "error: base fw not found"}, 469 {HDA_DSP_ROM_CSE_VALIDATION_FAILED, "error: signature verification failed"}, 470 {HDA_DSP_ROM_IPC_FATAL_ERROR, "error: ipc fatal error"}, 471 {HDA_DSP_ROM_L2_CACHE_ERROR, "error: L2 cache error"}, 472 {HDA_DSP_ROM_LOAD_OFFSET_TO_SMALL, "error: load offset too small"}, 473 {HDA_DSP_ROM_API_PTR_INVALID, "error: API ptr invalid"}, 474 {HDA_DSP_ROM_BASEFW_INCOMPAT, "error: base fw incompatible"}, 475 {HDA_DSP_ROM_UNHANDLED_INTERRUPT, "error: unhandled interrupt"}, 476 {HDA_DSP_ROM_MEMORY_HOLE_ECC, "error: ECC memory hole"}, 477 {HDA_DSP_ROM_KERNEL_EXCEPTION, "error: kernel exception"}, 478 {HDA_DSP_ROM_USER_EXCEPTION, "error: user exception"}, 479 {HDA_DSP_ROM_UNEXPECTED_RESET, "error: unexpected reset"}, 480 {HDA_DSP_ROM_NULL_FW_ENTRY, "error: null FW entry point"}, 481 }; 482 483 #define FSR_ROM_STATE_ENTRY(state) {FSR_STATE_ROM_##state, #state} 484 static const struct hda_dsp_msg_code fsr_rom_state_names[] = { 485 FSR_ROM_STATE_ENTRY(INIT), 486 FSR_ROM_STATE_ENTRY(INIT_DONE), 487 FSR_ROM_STATE_ENTRY(CSE_MANIFEST_LOADED), 488 FSR_ROM_STATE_ENTRY(FW_MANIFEST_LOADED), 489 FSR_ROM_STATE_ENTRY(FW_FW_LOADED), 490 FSR_ROM_STATE_ENTRY(FW_ENTERED), 491 FSR_ROM_STATE_ENTRY(VERIFY_FEATURE_MASK), 492 FSR_ROM_STATE_ENTRY(GET_LOAD_OFFSET), 493 FSR_ROM_STATE_ENTRY(FETCH_ROM_EXT), 494 FSR_ROM_STATE_ENTRY(FETCH_ROM_EXT_DONE), 495 /* CSE states */ 496 FSR_ROM_STATE_ENTRY(CSE_IMR_REQUEST), 497 FSR_ROM_STATE_ENTRY(CSE_IMR_GRANTED), 498 FSR_ROM_STATE_ENTRY(CSE_VALIDATE_IMAGE_REQUEST), 499 FSR_ROM_STATE_ENTRY(CSE_IMAGE_VALIDATED), 500 FSR_ROM_STATE_ENTRY(CSE_IPC_IFACE_INIT), 501 FSR_ROM_STATE_ENTRY(CSE_IPC_RESET_PHASE_1), 502 FSR_ROM_STATE_ENTRY(CSE_IPC_OPERATIONAL_ENTRY), 503 FSR_ROM_STATE_ENTRY(CSE_IPC_OPERATIONAL), 504 FSR_ROM_STATE_ENTRY(CSE_IPC_DOWN), 505 }; 506 507 #define FSR_BRINGUP_STATE_ENTRY(state) {FSR_STATE_BRINGUP_##state, #state} 508 static const struct hda_dsp_msg_code fsr_bringup_state_names[] = { 509 FSR_BRINGUP_STATE_ENTRY(INIT), 510 FSR_BRINGUP_STATE_ENTRY(INIT_DONE), 511 FSR_BRINGUP_STATE_ENTRY(HPSRAM_LOAD), 512 FSR_BRINGUP_STATE_ENTRY(UNPACK_START), 513 FSR_BRINGUP_STATE_ENTRY(IMR_RESTORE), 514 FSR_BRINGUP_STATE_ENTRY(FW_ENTERED), 515 }; 516 517 #define FSR_WAIT_STATE_ENTRY(state) {FSR_WAIT_FOR_##state, #state} 518 static const struct hda_dsp_msg_code fsr_wait_state_names[] = { 519 FSR_WAIT_STATE_ENTRY(IPC_BUSY), 520 FSR_WAIT_STATE_ENTRY(IPC_DONE), 521 FSR_WAIT_STATE_ENTRY(CACHE_INVALIDATION), 522 FSR_WAIT_STATE_ENTRY(LP_SRAM_OFF), 523 FSR_WAIT_STATE_ENTRY(DMA_BUFFER_FULL), 524 FSR_WAIT_STATE_ENTRY(CSE_CSR), 525 }; 526 527 #define FSR_MODULE_NAME_ENTRY(mod) [FSR_MOD_##mod] = #mod 528 static const char * const fsr_module_names[] = { 529 FSR_MODULE_NAME_ENTRY(ROM), 530 FSR_MODULE_NAME_ENTRY(ROM_BYP), 531 FSR_MODULE_NAME_ENTRY(BASE_FW), 532 FSR_MODULE_NAME_ENTRY(LP_BOOT), 533 FSR_MODULE_NAME_ENTRY(BRNGUP), 534 FSR_MODULE_NAME_ENTRY(ROM_EXT), 535 }; 536 537 static const char * 538 hda_dsp_get_state_text(u32 code, const struct hda_dsp_msg_code *msg_code, 539 size_t array_size) 540 { 541 int i; 542 543 for (i = 0; i < array_size; i++) { 544 if (code == msg_code[i].code) 545 return msg_code[i].text; 546 } 547 548 return NULL; 549 } 550 551 static void hda_dsp_get_state(struct snd_sof_dev *sdev, const char *level) 552 { 553 const struct sof_intel_dsp_desc *chip = get_chip_info(sdev->pdata); 554 const char *state_text, *error_text, *module_text; 555 u32 fsr, state, wait_state, module, error_code; 556 557 fsr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, chip->rom_status_reg); 558 state = FSR_TO_STATE_CODE(fsr); 559 wait_state = FSR_TO_WAIT_STATE_CODE(fsr); 560 module = FSR_TO_MODULE_CODE(fsr); 561 562 if (module > FSR_MOD_ROM_EXT) 563 module_text = "unknown"; 564 else 565 module_text = fsr_module_names[module]; 566 567 if (module == FSR_MOD_BRNGUP) 568 state_text = hda_dsp_get_state_text(state, fsr_bringup_state_names, 569 ARRAY_SIZE(fsr_bringup_state_names)); 570 else 571 state_text = hda_dsp_get_state_text(state, fsr_rom_state_names, 572 ARRAY_SIZE(fsr_rom_state_names)); 573 574 /* not for us, must be generic sof message */ 575 if (!state_text) { 576 dev_printk(level, sdev->dev, "%#010x: unknown ROM status value\n", fsr); 577 return; 578 } 579 580 if (wait_state) { 581 const char *wait_state_text; 582 583 wait_state_text = hda_dsp_get_state_text(wait_state, fsr_wait_state_names, 584 ARRAY_SIZE(fsr_wait_state_names)); 585 if (!wait_state_text) 586 wait_state_text = "unknown"; 587 588 dev_printk(level, sdev->dev, 589 "%#010x: module: %s, state: %s, waiting for: %s, %s\n", 590 fsr, module_text, state_text, wait_state_text, 591 fsr & FSR_HALTED ? "not running" : "running"); 592 } else { 593 dev_printk(level, sdev->dev, "%#010x: module: %s, state: %s, %s\n", 594 fsr, module_text, state_text, 595 fsr & FSR_HALTED ? "not running" : "running"); 596 } 597 598 error_code = snd_sof_dsp_read(sdev, HDA_DSP_BAR, chip->rom_status_reg + 4); 599 if (!error_code) 600 return; 601 602 error_text = hda_dsp_get_state_text(error_code, hda_dsp_rom_fw_error_texts, 603 ARRAY_SIZE(hda_dsp_rom_fw_error_texts)); 604 if (!error_text) 605 error_text = "unknown"; 606 607 if (state == FSR_STATE_FW_ENTERED) 608 dev_printk(level, sdev->dev, "status code: %#x (%s)\n", error_code, 609 error_text); 610 else 611 dev_printk(level, sdev->dev, "error code: %#x (%s)\n", error_code, 612 error_text); 613 } 614 615 static void hda_dsp_get_registers(struct snd_sof_dev *sdev, 616 struct sof_ipc_dsp_oops_xtensa *xoops, 617 struct sof_ipc_panic_info *panic_info, 618 u32 *stack, size_t stack_words) 619 { 620 u32 offset = sdev->dsp_oops_offset; 621 622 /* first read registers */ 623 sof_mailbox_read(sdev, offset, xoops, sizeof(*xoops)); 624 625 /* note: variable AR register array is not read */ 626 627 /* then get panic info */ 628 if (xoops->arch_hdr.totalsize > EXCEPT_MAX_HDR_SIZE) { 629 dev_err(sdev->dev, "invalid header size 0x%x. FW oops is bogus\n", 630 xoops->arch_hdr.totalsize); 631 return; 632 } 633 offset += xoops->arch_hdr.totalsize; 634 sof_block_read(sdev, sdev->mmio_bar, offset, 635 panic_info, sizeof(*panic_info)); 636 637 /* then get the stack */ 638 offset += sizeof(*panic_info); 639 sof_block_read(sdev, sdev->mmio_bar, offset, stack, 640 stack_words * sizeof(u32)); 641 } 642 643 /* dump the first 8 dwords representing the extended ROM status */ 644 static void hda_dsp_dump_ext_rom_status(struct snd_sof_dev *sdev, const char *level, 645 u32 flags) 646 { 647 const struct sof_intel_dsp_desc *chip; 648 char msg[128]; 649 int len = 0; 650 u32 value; 651 int i; 652 653 chip = get_chip_info(sdev->pdata); 654 for (i = 0; i < HDA_EXT_ROM_STATUS_SIZE; i++) { 655 value = snd_sof_dsp_read(sdev, HDA_DSP_BAR, chip->rom_status_reg + i * 0x4); 656 len += scnprintf(msg + len, sizeof(msg) - len, " 0x%x", value); 657 } 658 659 dev_printk(level, sdev->dev, "extended rom status: %s", msg); 660 661 } 662 663 void hda_dsp_dump(struct snd_sof_dev *sdev, u32 flags) 664 { 665 char *level = (flags & SOF_DBG_DUMP_OPTIONAL) ? KERN_DEBUG : KERN_ERR; 666 struct sof_ipc_dsp_oops_xtensa xoops; 667 struct sof_ipc_panic_info panic_info; 668 u32 stack[HDA_DSP_STACK_DUMP_SIZE]; 669 670 /* print ROM/FW status */ 671 hda_dsp_get_state(sdev, level); 672 673 /* The firmware register dump only available with IPC3 */ 674 if (flags & SOF_DBG_DUMP_REGS && sdev->pdata->ipc_type == SOF_IPC) { 675 u32 status = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_SRAM_REG_FW_STATUS); 676 u32 panic = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_SRAM_REG_FW_TRACEP); 677 678 hda_dsp_get_registers(sdev, &xoops, &panic_info, stack, 679 HDA_DSP_STACK_DUMP_SIZE); 680 sof_print_oops_and_stack(sdev, level, status, panic, &xoops, 681 &panic_info, stack, HDA_DSP_STACK_DUMP_SIZE); 682 } else { 683 hda_dsp_dump_ext_rom_status(sdev, level, flags); 684 } 685 } 686 687 static bool hda_check_ipc_irq(struct snd_sof_dev *sdev) 688 { 689 const struct sof_intel_dsp_desc *chip; 690 691 chip = get_chip_info(sdev->pdata); 692 if (chip && chip->check_ipc_irq) 693 return chip->check_ipc_irq(sdev); 694 695 return false; 696 } 697 698 void hda_ipc_irq_dump(struct snd_sof_dev *sdev) 699 { 700 u32 adspis; 701 u32 intsts; 702 u32 intctl; 703 u32 ppsts; 704 u8 rirbsts; 705 706 /* read key IRQ stats and config registers */ 707 adspis = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIS); 708 intsts = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTSTS); 709 intctl = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL); 710 ppsts = snd_sof_dsp_read(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPSTS); 711 rirbsts = snd_sof_dsp_read8(sdev, HDA_DSP_HDA_BAR, AZX_REG_RIRBSTS); 712 713 dev_err(sdev->dev, "hda irq intsts 0x%8.8x intlctl 0x%8.8x rirb %2.2x\n", 714 intsts, intctl, rirbsts); 715 dev_err(sdev->dev, "dsp irq ppsts 0x%8.8x adspis 0x%8.8x\n", ppsts, adspis); 716 } 717 718 void hda_ipc_dump(struct snd_sof_dev *sdev) 719 { 720 u32 hipcie; 721 u32 hipct; 722 u32 hipcctl; 723 724 hda_ipc_irq_dump(sdev); 725 726 /* read IPC status */ 727 hipcie = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCIE); 728 hipct = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCT); 729 hipcctl = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCCTL); 730 731 /* dump the IPC regs */ 732 /* TODO: parse the raw msg */ 733 dev_err(sdev->dev, "host status 0x%8.8x dsp status 0x%8.8x mask 0x%8.8x\n", 734 hipcie, hipct, hipcctl); 735 } 736 737 void hda_ipc4_dump(struct snd_sof_dev *sdev) 738 { 739 u32 hipci, hipcie, hipct, hipcte, hipcctl; 740 741 hda_ipc_irq_dump(sdev); 742 743 hipci = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCI); 744 hipcie = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCIE); 745 hipct = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCT); 746 hipcte = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCTE); 747 hipcctl = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCCTL); 748 749 /* dump the IPC regs */ 750 /* TODO: parse the raw msg */ 751 dev_err(sdev->dev, "Host IPC initiator: %#x|%#x, target: %#x|%#x, ctl: %#x\n", 752 hipci, hipcie, hipct, hipcte, hipcctl); 753 } 754 755 bool hda_ipc4_tx_is_busy(struct snd_sof_dev *sdev) 756 { 757 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 758 const struct sof_intel_dsp_desc *chip = hda->desc; 759 u32 val; 760 761 val = snd_sof_dsp_read(sdev, HDA_DSP_BAR, chip->ipc_req); 762 763 return !!(val & chip->ipc_req_mask); 764 } 765 766 static int hda_init(struct snd_sof_dev *sdev) 767 { 768 struct hda_bus *hbus; 769 struct hdac_bus *bus; 770 struct pci_dev *pci = to_pci_dev(sdev->dev); 771 int ret; 772 773 hbus = sof_to_hbus(sdev); 774 bus = sof_to_bus(sdev); 775 776 /* HDA bus init */ 777 sof_hda_bus_init(sdev, &pci->dev); 778 779 if (sof_hda_position_quirk == SOF_HDA_POSITION_QUIRK_USE_DPIB_REGISTERS) 780 bus->use_posbuf = 0; 781 else 782 bus->use_posbuf = 1; 783 bus->bdl_pos_adj = 0; 784 bus->sync_write = 1; 785 786 mutex_init(&hbus->prepare_mutex); 787 hbus->pci = pci; 788 hbus->mixer_assigned = -1; 789 hbus->modelname = hda_model; 790 791 /* initialise hdac bus */ 792 bus->addr = pci_resource_start(pci, 0); 793 bus->remap_addr = pci_ioremap_bar(pci, 0); 794 if (!bus->remap_addr) { 795 dev_err(bus->dev, "error: ioremap error\n"); 796 return -ENXIO; 797 } 798 799 /* HDA base */ 800 sdev->bar[HDA_DSP_HDA_BAR] = bus->remap_addr; 801 802 /* init i915 and HDMI codecs */ 803 ret = hda_codec_i915_init(sdev); 804 if (ret < 0) 805 dev_warn(sdev->dev, "init of i915 and HDMI codec failed\n"); 806 807 /* get controller capabilities */ 808 ret = hda_dsp_ctrl_get_caps(sdev); 809 if (ret < 0) 810 dev_err(sdev->dev, "error: get caps error\n"); 811 812 return ret; 813 } 814 815 static int check_dmic_num(struct snd_sof_dev *sdev) 816 { 817 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata; 818 struct nhlt_acpi_table *nhlt; 819 int dmic_num = 0; 820 821 nhlt = hdev->nhlt; 822 if (nhlt) 823 dmic_num = intel_nhlt_get_dmic_geo(sdev->dev, nhlt); 824 825 /* allow for module parameter override */ 826 if (dmic_num_override != -1) { 827 dev_dbg(sdev->dev, 828 "overriding DMICs detected in NHLT tables %d by kernel param %d\n", 829 dmic_num, dmic_num_override); 830 dmic_num = dmic_num_override; 831 } 832 833 if (dmic_num < 0 || dmic_num > 4) { 834 dev_dbg(sdev->dev, "invalid dmic_number %d\n", dmic_num); 835 dmic_num = 0; 836 } 837 838 return dmic_num; 839 } 840 841 static int check_nhlt_ssp_mask(struct snd_sof_dev *sdev) 842 { 843 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata; 844 struct nhlt_acpi_table *nhlt; 845 int ssp_mask = 0; 846 847 nhlt = hdev->nhlt; 848 if (!nhlt) 849 return ssp_mask; 850 851 if (intel_nhlt_has_endpoint_type(nhlt, NHLT_LINK_SSP)) { 852 ssp_mask = intel_nhlt_ssp_endpoint_mask(nhlt, NHLT_DEVICE_I2S); 853 if (ssp_mask) 854 dev_info(sdev->dev, "NHLT_DEVICE_I2S detected, ssp_mask %#x\n", ssp_mask); 855 } 856 857 return ssp_mask; 858 } 859 860 static int check_nhlt_ssp_mclk_mask(struct snd_sof_dev *sdev, int ssp_num) 861 { 862 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata; 863 struct nhlt_acpi_table *nhlt; 864 865 nhlt = hdev->nhlt; 866 if (!nhlt) 867 return 0; 868 869 return intel_nhlt_ssp_mclk_mask(nhlt, ssp_num); 870 } 871 872 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC) || IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE) 873 874 static const char *fixup_tplg_name(struct snd_sof_dev *sdev, 875 const char *sof_tplg_filename, 876 const char *idisp_str, 877 const char *dmic_str) 878 { 879 const char *tplg_filename = NULL; 880 char *filename, *tmp; 881 const char *split_ext; 882 883 filename = kstrdup(sof_tplg_filename, GFP_KERNEL); 884 if (!filename) 885 return NULL; 886 887 /* this assumes a .tplg extension */ 888 tmp = filename; 889 split_ext = strsep(&tmp, "."); 890 if (split_ext) 891 tplg_filename = devm_kasprintf(sdev->dev, GFP_KERNEL, 892 "%s%s%s.tplg", 893 split_ext, idisp_str, dmic_str); 894 kfree(filename); 895 896 return tplg_filename; 897 } 898 899 static int dmic_detect_topology_fixup(struct snd_sof_dev *sdev, 900 const char **tplg_filename, 901 const char *idisp_str, 902 int *dmic_found, 903 bool tplg_fixup) 904 { 905 const char *dmic_str; 906 int dmic_num; 907 908 /* first check for DMICs (using NHLT or module parameter) */ 909 dmic_num = check_dmic_num(sdev); 910 911 switch (dmic_num) { 912 case 1: 913 dmic_str = "-1ch"; 914 break; 915 case 2: 916 dmic_str = "-2ch"; 917 break; 918 case 3: 919 dmic_str = "-3ch"; 920 break; 921 case 4: 922 dmic_str = "-4ch"; 923 break; 924 default: 925 dmic_num = 0; 926 dmic_str = ""; 927 break; 928 } 929 930 if (tplg_fixup) { 931 const char *default_tplg_filename = *tplg_filename; 932 const char *fixed_tplg_filename; 933 934 fixed_tplg_filename = fixup_tplg_name(sdev, default_tplg_filename, 935 idisp_str, dmic_str); 936 if (!fixed_tplg_filename) 937 return -ENOMEM; 938 *tplg_filename = fixed_tplg_filename; 939 } 940 941 dev_info(sdev->dev, "DMICs detected in NHLT tables: %d\n", dmic_num); 942 *dmic_found = dmic_num; 943 944 return 0; 945 } 946 #endif 947 948 static int hda_init_caps(struct snd_sof_dev *sdev) 949 { 950 u32 interface_mask = hda_get_interface_mask(sdev); 951 struct hdac_bus *bus = sof_to_bus(sdev); 952 struct snd_sof_pdata *pdata = sdev->pdata; 953 struct sof_intel_hda_dev *hdev = pdata->hw_pdata; 954 u32 link_mask; 955 int ret = 0; 956 957 /* check if dsp is there */ 958 if (bus->ppcap) 959 dev_dbg(sdev->dev, "PP capability, will probe DSP later.\n"); 960 961 /* Init HDA controller after i915 init */ 962 ret = hda_dsp_ctrl_init_chip(sdev); 963 if (ret < 0) { 964 dev_err(bus->dev, "error: init chip failed with ret: %d\n", 965 ret); 966 return ret; 967 } 968 969 hda_bus_ml_init(bus); 970 971 /* Skip SoundWire if it is not supported */ 972 if (!(interface_mask & BIT(SOF_DAI_INTEL_ALH))) 973 goto skip_soundwire; 974 975 /* scan SoundWire capabilities exposed by DSDT */ 976 ret = hda_sdw_acpi_scan(sdev); 977 if (ret < 0) { 978 dev_dbg(sdev->dev, "skipping SoundWire, not detected with ACPI scan\n"); 979 goto skip_soundwire; 980 } 981 982 link_mask = hdev->info.link_mask; 983 if (!link_mask) { 984 dev_dbg(sdev->dev, "skipping SoundWire, no links enabled\n"); 985 goto skip_soundwire; 986 } 987 988 /* 989 * probe/allocate SoundWire resources. 990 * The hardware configuration takes place in hda_sdw_startup 991 * after power rails are enabled. 992 * It's entirely possible to have a mix of I2S/DMIC/SoundWire 993 * devices, so we allocate the resources in all cases. 994 */ 995 ret = hda_sdw_probe(sdev); 996 if (ret < 0) { 997 dev_err(sdev->dev, "error: SoundWire probe error\n"); 998 return ret; 999 } 1000 1001 skip_soundwire: 1002 1003 /* create codec instances */ 1004 hda_codec_probe_bus(sdev); 1005 1006 if (!HDA_IDISP_CODEC(bus->codec_mask)) 1007 hda_codec_i915_display_power(sdev, false); 1008 1009 hda_bus_ml_put_all(bus); 1010 1011 return 0; 1012 } 1013 1014 static irqreturn_t hda_dsp_interrupt_handler(int irq, void *context) 1015 { 1016 struct snd_sof_dev *sdev = context; 1017 1018 /* 1019 * Get global interrupt status. It includes all hardware interrupt 1020 * sources in the Intel HD Audio controller. 1021 */ 1022 if (snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTSTS) & 1023 SOF_HDA_INTSTS_GIS) { 1024 1025 /* disable GIE interrupt */ 1026 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, 1027 SOF_HDA_INTCTL, 1028 SOF_HDA_INT_GLOBAL_EN, 1029 0); 1030 1031 return IRQ_WAKE_THREAD; 1032 } 1033 1034 return IRQ_NONE; 1035 } 1036 1037 static irqreturn_t hda_dsp_interrupt_thread(int irq, void *context) 1038 { 1039 struct snd_sof_dev *sdev = context; 1040 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata; 1041 1042 /* deal with streams and controller first */ 1043 if (hda_dsp_check_stream_irq(sdev)) { 1044 trace_sof_intel_hda_irq(sdev, "stream"); 1045 hda_dsp_stream_threaded_handler(irq, sdev); 1046 } 1047 1048 if (hda_check_ipc_irq(sdev)) { 1049 trace_sof_intel_hda_irq(sdev, "ipc"); 1050 sof_ops(sdev)->irq_thread(irq, sdev); 1051 } 1052 1053 if (hda_dsp_check_sdw_irq(sdev)) { 1054 trace_sof_intel_hda_irq(sdev, "sdw"); 1055 hda_dsp_sdw_thread(irq, hdev->sdw); 1056 } 1057 1058 if (hda_sdw_check_wakeen_irq(sdev)) { 1059 trace_sof_intel_hda_irq(sdev, "wakeen"); 1060 hda_sdw_process_wakeen(sdev); 1061 } 1062 1063 hda_codec_check_for_state_change(sdev); 1064 1065 /* enable GIE interrupt */ 1066 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, 1067 SOF_HDA_INTCTL, 1068 SOF_HDA_INT_GLOBAL_EN, 1069 SOF_HDA_INT_GLOBAL_EN); 1070 1071 return IRQ_HANDLED; 1072 } 1073 1074 int hda_dsp_probe(struct snd_sof_dev *sdev) 1075 { 1076 struct pci_dev *pci = to_pci_dev(sdev->dev); 1077 struct sof_intel_hda_dev *hdev; 1078 struct hdac_bus *bus; 1079 const struct sof_intel_dsp_desc *chip; 1080 int ret = 0; 1081 1082 if (!sdev->dspless_mode_selected) { 1083 /* 1084 * detect DSP by checking class/subclass/prog-id information 1085 * class=04 subclass 03 prog-if 00: no DSP, legacy driver is required 1086 * class=04 subclass 01 prog-if 00: DSP is present 1087 * (and may be required e.g. for DMIC or SSP support) 1088 * class=04 subclass 03 prog-if 80: either of DSP or legacy mode works 1089 */ 1090 if (pci->class == 0x040300) { 1091 dev_err(sdev->dev, "the DSP is not enabled on this platform, aborting probe\n"); 1092 return -ENODEV; 1093 } else if (pci->class != 0x040100 && pci->class != 0x040380) { 1094 dev_err(sdev->dev, "unknown PCI class/subclass/prog-if 0x%06x found, aborting probe\n", 1095 pci->class); 1096 return -ENODEV; 1097 } 1098 dev_info(sdev->dev, "DSP detected with PCI class/subclass/prog-if 0x%06x\n", 1099 pci->class); 1100 } 1101 1102 chip = get_chip_info(sdev->pdata); 1103 if (!chip) { 1104 dev_err(sdev->dev, "error: no such device supported, chip id:%x\n", 1105 pci->device); 1106 ret = -EIO; 1107 goto err; 1108 } 1109 1110 sdev->num_cores = chip->cores_num; 1111 1112 hdev = devm_kzalloc(sdev->dev, sizeof(*hdev), GFP_KERNEL); 1113 if (!hdev) 1114 return -ENOMEM; 1115 sdev->pdata->hw_pdata = hdev; 1116 hdev->desc = chip; 1117 1118 hdev->dmic_dev = platform_device_register_data(sdev->dev, "dmic-codec", 1119 PLATFORM_DEVID_NONE, 1120 NULL, 0); 1121 if (IS_ERR(hdev->dmic_dev)) { 1122 dev_err(sdev->dev, "error: failed to create DMIC device\n"); 1123 return PTR_ERR(hdev->dmic_dev); 1124 } 1125 1126 /* 1127 * use position update IPC if either it is forced 1128 * or we don't have other choice 1129 */ 1130 #if IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG_FORCE_IPC_POSITION) 1131 hdev->no_ipc_position = 0; 1132 #else 1133 hdev->no_ipc_position = sof_ops(sdev)->pcm_pointer ? 1 : 0; 1134 #endif 1135 1136 if (sdev->dspless_mode_selected) 1137 hdev->no_ipc_position = 1; 1138 1139 /* set up HDA base */ 1140 bus = sof_to_bus(sdev); 1141 ret = hda_init(sdev); 1142 if (ret < 0) 1143 goto hdac_bus_unmap; 1144 1145 if (sdev->dspless_mode_selected) 1146 goto skip_dsp_setup; 1147 1148 /* DSP base */ 1149 sdev->bar[HDA_DSP_BAR] = pci_ioremap_bar(pci, HDA_DSP_BAR); 1150 if (!sdev->bar[HDA_DSP_BAR]) { 1151 dev_err(sdev->dev, "error: ioremap error\n"); 1152 ret = -ENXIO; 1153 goto hdac_bus_unmap; 1154 } 1155 1156 sdev->mmio_bar = HDA_DSP_BAR; 1157 sdev->mailbox_bar = HDA_DSP_BAR; 1158 skip_dsp_setup: 1159 1160 /* allow 64bit DMA address if supported by H/W */ 1161 if (dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(64))) { 1162 dev_dbg(sdev->dev, "DMA mask is 32 bit\n"); 1163 dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(32)); 1164 } 1165 dma_set_max_seg_size(&pci->dev, UINT_MAX); 1166 1167 /* init streams */ 1168 ret = hda_dsp_stream_init(sdev); 1169 if (ret < 0) { 1170 dev_err(sdev->dev, "error: failed to init streams\n"); 1171 /* 1172 * not all errors are due to memory issues, but trying 1173 * to free everything does not harm 1174 */ 1175 goto free_streams; 1176 } 1177 1178 /* 1179 * register our IRQ 1180 * let's try to enable msi firstly 1181 * if it fails, use legacy interrupt mode 1182 * TODO: support msi multiple vectors 1183 */ 1184 if (hda_use_msi && pci_alloc_irq_vectors(pci, 1, 1, PCI_IRQ_MSI) > 0) { 1185 dev_info(sdev->dev, "use msi interrupt mode\n"); 1186 sdev->ipc_irq = pci_irq_vector(pci, 0); 1187 /* initialised to "false" by kzalloc() */ 1188 sdev->msi_enabled = true; 1189 } 1190 1191 if (!sdev->msi_enabled) { 1192 dev_info(sdev->dev, "use legacy interrupt mode\n"); 1193 /* 1194 * in IO-APIC mode, hda->irq and ipc_irq are using the same 1195 * irq number of pci->irq 1196 */ 1197 sdev->ipc_irq = pci->irq; 1198 } 1199 1200 dev_dbg(sdev->dev, "using IPC IRQ %d\n", sdev->ipc_irq); 1201 ret = request_threaded_irq(sdev->ipc_irq, hda_dsp_interrupt_handler, 1202 hda_dsp_interrupt_thread, 1203 IRQF_SHARED, "AudioDSP", sdev); 1204 if (ret < 0) { 1205 dev_err(sdev->dev, "error: failed to register IPC IRQ %d\n", 1206 sdev->ipc_irq); 1207 goto free_irq_vector; 1208 } 1209 1210 pci_set_master(pci); 1211 synchronize_irq(pci->irq); 1212 1213 /* 1214 * clear TCSEL to clear playback on some HD Audio 1215 * codecs. PCI TCSEL is defined in the Intel manuals. 1216 */ 1217 snd_sof_pci_update_bits(sdev, PCI_TCSEL, 0x07, 0); 1218 1219 /* init HDA capabilities */ 1220 ret = hda_init_caps(sdev); 1221 if (ret < 0) 1222 goto free_ipc_irq; 1223 1224 if (!sdev->dspless_mode_selected) { 1225 /* enable ppcap interrupt */ 1226 hda_dsp_ctrl_ppcap_enable(sdev, true); 1227 hda_dsp_ctrl_ppcap_int_enable(sdev, true); 1228 1229 /* set default mailbox offset for FW ready message */ 1230 sdev->dsp_box.offset = HDA_DSP_MBOX_UPLINK_OFFSET; 1231 1232 INIT_DELAYED_WORK(&hdev->d0i3_work, hda_dsp_d0i3_work); 1233 } 1234 1235 init_waitqueue_head(&hdev->waitq); 1236 1237 hdev->nhlt = intel_nhlt_init(sdev->dev); 1238 1239 return 0; 1240 1241 free_ipc_irq: 1242 free_irq(sdev->ipc_irq, sdev); 1243 free_irq_vector: 1244 if (sdev->msi_enabled) 1245 pci_free_irq_vectors(pci); 1246 free_streams: 1247 hda_dsp_stream_free(sdev); 1248 /* dsp_unmap: not currently used */ 1249 if (!sdev->dspless_mode_selected) 1250 iounmap(sdev->bar[HDA_DSP_BAR]); 1251 hdac_bus_unmap: 1252 platform_device_unregister(hdev->dmic_dev); 1253 iounmap(bus->remap_addr); 1254 hda_codec_i915_exit(sdev); 1255 err: 1256 return ret; 1257 } 1258 1259 int hda_dsp_remove(struct snd_sof_dev *sdev) 1260 { 1261 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 1262 const struct sof_intel_dsp_desc *chip = hda->desc; 1263 struct hdac_bus *bus = sof_to_bus(sdev); 1264 struct pci_dev *pci = to_pci_dev(sdev->dev); 1265 struct nhlt_acpi_table *nhlt = hda->nhlt; 1266 1267 if (nhlt) 1268 intel_nhlt_free(nhlt); 1269 1270 if (!sdev->dspless_mode_selected) 1271 /* cancel any attempt for DSP D0I3 */ 1272 cancel_delayed_work_sync(&hda->d0i3_work); 1273 1274 hda_codec_device_remove(sdev); 1275 1276 hda_sdw_exit(sdev); 1277 1278 if (!IS_ERR_OR_NULL(hda->dmic_dev)) 1279 platform_device_unregister(hda->dmic_dev); 1280 1281 if (!sdev->dspless_mode_selected) { 1282 /* disable DSP IRQ */ 1283 snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL, 1284 SOF_HDA_PPCTL_PIE, 0); 1285 } 1286 1287 /* disable CIE and GIE interrupts */ 1288 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL, 1289 SOF_HDA_INT_CTRL_EN | SOF_HDA_INT_GLOBAL_EN, 0); 1290 1291 if (sdev->dspless_mode_selected) 1292 goto skip_disable_dsp; 1293 1294 /* no need to check for error as the DSP will be disabled anyway */ 1295 if (chip && chip->power_down_dsp) 1296 chip->power_down_dsp(sdev); 1297 1298 /* disable DSP */ 1299 snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL, 1300 SOF_HDA_PPCTL_GPROCEN, 0); 1301 1302 skip_disable_dsp: 1303 free_irq(sdev->ipc_irq, sdev); 1304 if (sdev->msi_enabled) 1305 pci_free_irq_vectors(pci); 1306 1307 hda_dsp_stream_free(sdev); 1308 1309 hda_bus_ml_free(sof_to_bus(sdev)); 1310 1311 if (!sdev->dspless_mode_selected) 1312 iounmap(sdev->bar[HDA_DSP_BAR]); 1313 1314 iounmap(bus->remap_addr); 1315 1316 sof_hda_bus_exit(sdev); 1317 1318 hda_codec_i915_exit(sdev); 1319 1320 return 0; 1321 } 1322 1323 int hda_power_down_dsp(struct snd_sof_dev *sdev) 1324 { 1325 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 1326 const struct sof_intel_dsp_desc *chip = hda->desc; 1327 1328 return hda_dsp_core_reset_power_down(sdev, chip->host_managed_cores_mask); 1329 } 1330 1331 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC) 1332 static void hda_generic_machine_select(struct snd_sof_dev *sdev, 1333 struct snd_soc_acpi_mach **mach) 1334 { 1335 struct hdac_bus *bus = sof_to_bus(sdev); 1336 struct snd_soc_acpi_mach_params *mach_params; 1337 struct snd_soc_acpi_mach *hda_mach; 1338 struct snd_sof_pdata *pdata = sdev->pdata; 1339 const char *tplg_filename; 1340 const char *idisp_str; 1341 int dmic_num = 0; 1342 int codec_num = 0; 1343 int ret; 1344 int i; 1345 1346 /* codec detection */ 1347 if (!bus->codec_mask) { 1348 dev_info(bus->dev, "no hda codecs found!\n"); 1349 } else { 1350 dev_info(bus->dev, "hda codecs found, mask %lx\n", 1351 bus->codec_mask); 1352 1353 for (i = 0; i < HDA_MAX_CODECS; i++) { 1354 if (bus->codec_mask & (1 << i)) 1355 codec_num++; 1356 } 1357 1358 /* 1359 * If no machine driver is found, then: 1360 * 1361 * generic hda machine driver can handle: 1362 * - one HDMI codec, and/or 1363 * - one external HDAudio codec 1364 */ 1365 if (!*mach && codec_num <= 2) { 1366 bool tplg_fixup; 1367 1368 hda_mach = snd_soc_acpi_intel_hda_machines; 1369 1370 dev_info(bus->dev, "using HDA machine driver %s now\n", 1371 hda_mach->drv_name); 1372 1373 if (codec_num == 1 && HDA_IDISP_CODEC(bus->codec_mask)) 1374 idisp_str = "-idisp"; 1375 else 1376 idisp_str = ""; 1377 1378 /* topology: use the info from hda_machines */ 1379 if (pdata->tplg_filename) { 1380 tplg_fixup = false; 1381 tplg_filename = pdata->tplg_filename; 1382 } else { 1383 tplg_fixup = true; 1384 tplg_filename = hda_mach->sof_tplg_filename; 1385 } 1386 ret = dmic_detect_topology_fixup(sdev, &tplg_filename, idisp_str, &dmic_num, 1387 tplg_fixup); 1388 if (ret < 0) 1389 return; 1390 1391 hda_mach->mach_params.dmic_num = dmic_num; 1392 pdata->tplg_filename = tplg_filename; 1393 1394 if (codec_num == 2 || 1395 (codec_num == 1 && !HDA_IDISP_CODEC(bus->codec_mask))) { 1396 /* 1397 * Prevent SoundWire links from starting when an external 1398 * HDaudio codec is used 1399 */ 1400 hda_mach->mach_params.link_mask = 0; 1401 } else { 1402 /* 1403 * Allow SoundWire links to start when no external HDaudio codec 1404 * was detected. This will not create a SoundWire card but 1405 * will help detect if any SoundWire codec reports as ATTACHED. 1406 */ 1407 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata; 1408 1409 hda_mach->mach_params.link_mask = hdev->info.link_mask; 1410 } 1411 1412 *mach = hda_mach; 1413 } 1414 } 1415 1416 /* used by hda machine driver to create dai links */ 1417 if (*mach) { 1418 mach_params = &(*mach)->mach_params; 1419 mach_params->codec_mask = bus->codec_mask; 1420 mach_params->common_hdmi_codec_drv = true; 1421 } 1422 } 1423 #else 1424 static void hda_generic_machine_select(struct snd_sof_dev *sdev, 1425 struct snd_soc_acpi_mach **mach) 1426 { 1427 } 1428 #endif 1429 1430 #if IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE) 1431 1432 #define SDW_CODEC_ADR_MASK(_adr) ((_adr) & (SDW_DISCO_LINK_ID_MASK | SDW_VERSION_MASK | \ 1433 SDW_MFG_ID_MASK | SDW_PART_ID_MASK)) 1434 1435 /* Check if all Slaves defined on the link can be found */ 1436 static bool link_slaves_found(struct snd_sof_dev *sdev, 1437 const struct snd_soc_acpi_link_adr *link, 1438 struct sdw_intel_ctx *sdw) 1439 { 1440 struct hdac_bus *bus = sof_to_bus(sdev); 1441 struct sdw_intel_slave_id *ids = sdw->ids; 1442 int num_slaves = sdw->num_slaves; 1443 unsigned int part_id, link_id, unique_id, mfg_id, version; 1444 int i, j, k; 1445 1446 for (i = 0; i < link->num_adr; i++) { 1447 u64 adr = link->adr_d[i].adr; 1448 int reported_part_count = 0; 1449 1450 mfg_id = SDW_MFG_ID(adr); 1451 part_id = SDW_PART_ID(adr); 1452 link_id = SDW_DISCO_LINK_ID(adr); 1453 version = SDW_VERSION(adr); 1454 1455 for (j = 0; j < num_slaves; j++) { 1456 /* find out how many identical parts were reported on that link */ 1457 if (ids[j].link_id == link_id && 1458 ids[j].id.part_id == part_id && 1459 ids[j].id.mfg_id == mfg_id && 1460 ids[j].id.sdw_version == version) 1461 reported_part_count++; 1462 } 1463 1464 for (j = 0; j < num_slaves; j++) { 1465 int expected_part_count = 0; 1466 1467 if (ids[j].link_id != link_id || 1468 ids[j].id.part_id != part_id || 1469 ids[j].id.mfg_id != mfg_id || 1470 ids[j].id.sdw_version != version) 1471 continue; 1472 1473 /* find out how many identical parts are expected */ 1474 for (k = 0; k < link->num_adr; k++) { 1475 u64 adr2 = link->adr_d[k].adr; 1476 1477 if (SDW_CODEC_ADR_MASK(adr2) == SDW_CODEC_ADR_MASK(adr)) 1478 expected_part_count++; 1479 } 1480 1481 if (reported_part_count == expected_part_count) { 1482 /* 1483 * we have to check unique id 1484 * if there is more than one 1485 * Slave on the link 1486 */ 1487 unique_id = SDW_UNIQUE_ID(adr); 1488 if (reported_part_count == 1 || 1489 ids[j].id.unique_id == unique_id) { 1490 dev_dbg(bus->dev, "found %x at link %d\n", 1491 part_id, link_id); 1492 break; 1493 } 1494 } else { 1495 dev_dbg(bus->dev, "part %x reported %d expected %d on link %d, skipping\n", 1496 part_id, reported_part_count, expected_part_count, link_id); 1497 } 1498 } 1499 if (j == num_slaves) { 1500 dev_dbg(bus->dev, 1501 "Slave %x not found\n", 1502 part_id); 1503 return false; 1504 } 1505 } 1506 return true; 1507 } 1508 1509 static struct snd_soc_acpi_mach *hda_sdw_machine_select(struct snd_sof_dev *sdev) 1510 { 1511 struct snd_sof_pdata *pdata = sdev->pdata; 1512 const struct snd_soc_acpi_link_adr *link; 1513 struct snd_soc_acpi_mach *mach; 1514 struct sof_intel_hda_dev *hdev; 1515 u32 link_mask; 1516 int i; 1517 1518 hdev = pdata->hw_pdata; 1519 link_mask = hdev->info.link_mask; 1520 1521 /* 1522 * Select SoundWire machine driver if needed using the 1523 * alternate tables. This case deals with SoundWire-only 1524 * machines, for mixed cases with I2C/I2S the detection relies 1525 * on the HID list. 1526 */ 1527 if (link_mask) { 1528 for (mach = pdata->desc->alt_machines; 1529 mach && mach->link_mask; mach++) { 1530 /* 1531 * On some platforms such as Up Extreme all links 1532 * are enabled but only one link can be used by 1533 * external codec. Instead of exact match of two masks, 1534 * first check whether link_mask of mach is subset of 1535 * link_mask supported by hw and then go on searching 1536 * link_adr 1537 */ 1538 if (~link_mask & mach->link_mask) 1539 continue; 1540 1541 /* No need to match adr if there is no links defined */ 1542 if (!mach->links) 1543 break; 1544 1545 link = mach->links; 1546 for (i = 0; i < hdev->info.count && link->num_adr; 1547 i++, link++) { 1548 /* 1549 * Try next machine if any expected Slaves 1550 * are not found on this link. 1551 */ 1552 if (!link_slaves_found(sdev, link, hdev->sdw)) 1553 break; 1554 } 1555 /* Found if all Slaves are checked */ 1556 if (i == hdev->info.count || !link->num_adr) 1557 break; 1558 } 1559 if (mach && mach->link_mask) { 1560 int dmic_num = 0; 1561 bool tplg_fixup; 1562 const char *tplg_filename; 1563 1564 mach->mach_params.links = mach->links; 1565 mach->mach_params.link_mask = mach->link_mask; 1566 mach->mach_params.platform = dev_name(sdev->dev); 1567 1568 if (pdata->tplg_filename) { 1569 tplg_fixup = false; 1570 } else { 1571 tplg_fixup = true; 1572 tplg_filename = mach->sof_tplg_filename; 1573 } 1574 1575 /* 1576 * DMICs use up to 4 pins and are typically pin-muxed with SoundWire 1577 * link 2 and 3, or link 1 and 2, thus we only try to enable dmics 1578 * if all conditions are true: 1579 * a) 2 or fewer links are used by SoundWire 1580 * b) the NHLT table reports the presence of microphones 1581 */ 1582 if (hweight_long(mach->link_mask) <= 2) { 1583 int ret; 1584 1585 ret = dmic_detect_topology_fixup(sdev, &tplg_filename, "", 1586 &dmic_num, tplg_fixup); 1587 if (ret < 0) 1588 return NULL; 1589 } 1590 if (tplg_fixup) 1591 pdata->tplg_filename = tplg_filename; 1592 mach->mach_params.dmic_num = dmic_num; 1593 1594 dev_dbg(sdev->dev, 1595 "SoundWire machine driver %s topology %s\n", 1596 mach->drv_name, 1597 pdata->tplg_filename); 1598 1599 return mach; 1600 } 1601 1602 dev_info(sdev->dev, "No SoundWire machine driver found\n"); 1603 } 1604 1605 return NULL; 1606 } 1607 #else 1608 static struct snd_soc_acpi_mach *hda_sdw_machine_select(struct snd_sof_dev *sdev) 1609 { 1610 return NULL; 1611 } 1612 #endif 1613 1614 void hda_set_mach_params(struct snd_soc_acpi_mach *mach, 1615 struct snd_sof_dev *sdev) 1616 { 1617 struct snd_sof_pdata *pdata = sdev->pdata; 1618 const struct sof_dev_desc *desc = pdata->desc; 1619 struct snd_soc_acpi_mach_params *mach_params; 1620 1621 mach_params = &mach->mach_params; 1622 mach_params->platform = dev_name(sdev->dev); 1623 if (IS_ENABLED(CONFIG_SND_SOC_SOF_NOCODEC_DEBUG_SUPPORT) && 1624 sof_debug_check_flag(SOF_DBG_FORCE_NOCODEC)) 1625 mach_params->num_dai_drivers = SOF_SKL_NUM_DAIS_NOCODEC; 1626 else 1627 mach_params->num_dai_drivers = desc->ops->num_drv; 1628 mach_params->dai_drivers = desc->ops->drv; 1629 } 1630 1631 struct snd_soc_acpi_mach *hda_machine_select(struct snd_sof_dev *sdev) 1632 { 1633 u32 interface_mask = hda_get_interface_mask(sdev); 1634 struct snd_sof_pdata *sof_pdata = sdev->pdata; 1635 const struct sof_dev_desc *desc = sof_pdata->desc; 1636 struct snd_soc_acpi_mach *mach = NULL; 1637 const char *tplg_filename; 1638 1639 /* Try I2S or DMIC if it is supported */ 1640 if (interface_mask & (BIT(SOF_DAI_INTEL_SSP) | BIT(SOF_DAI_INTEL_DMIC))) 1641 mach = snd_soc_acpi_find_machine(desc->machines); 1642 1643 if (mach) { 1644 bool add_extension = false; 1645 bool tplg_fixup = false; 1646 1647 /* 1648 * If tplg file name is overridden, use it instead of 1649 * the one set in mach table 1650 */ 1651 if (!sof_pdata->tplg_filename) { 1652 sof_pdata->tplg_filename = mach->sof_tplg_filename; 1653 tplg_fixup = true; 1654 } 1655 1656 /* report to machine driver if any DMICs are found */ 1657 mach->mach_params.dmic_num = check_dmic_num(sdev); 1658 1659 if (tplg_fixup && 1660 mach->tplg_quirk_mask & SND_SOC_ACPI_TPLG_INTEL_DMIC_NUMBER && 1661 mach->mach_params.dmic_num) { 1662 tplg_filename = devm_kasprintf(sdev->dev, GFP_KERNEL, 1663 "%s%s%d%s", 1664 sof_pdata->tplg_filename, 1665 "-dmic", 1666 mach->mach_params.dmic_num, 1667 "ch"); 1668 if (!tplg_filename) 1669 return NULL; 1670 1671 sof_pdata->tplg_filename = tplg_filename; 1672 add_extension = true; 1673 } 1674 1675 if (mach->link_mask) { 1676 mach->mach_params.links = mach->links; 1677 mach->mach_params.link_mask = mach->link_mask; 1678 } 1679 1680 /* report SSP link mask to machine driver */ 1681 mach->mach_params.i2s_link_mask = check_nhlt_ssp_mask(sdev); 1682 1683 if (tplg_fixup && 1684 mach->tplg_quirk_mask & SND_SOC_ACPI_TPLG_INTEL_SSP_NUMBER && 1685 mach->mach_params.i2s_link_mask) { 1686 const struct sof_intel_dsp_desc *chip = get_chip_info(sdev->pdata); 1687 int ssp_num; 1688 int mclk_mask; 1689 1690 if (hweight_long(mach->mach_params.i2s_link_mask) > 1 && 1691 !(mach->tplg_quirk_mask & SND_SOC_ACPI_TPLG_INTEL_SSP_MSB)) 1692 dev_warn(sdev->dev, "More than one SSP exposed by NHLT, choosing MSB\n"); 1693 1694 /* fls returns 1-based results, SSPs indices are 0-based */ 1695 ssp_num = fls(mach->mach_params.i2s_link_mask) - 1; 1696 1697 if (ssp_num >= chip->ssp_count) { 1698 dev_err(sdev->dev, "Invalid SSP %d, max on this platform is %d\n", 1699 ssp_num, chip->ssp_count); 1700 return NULL; 1701 } 1702 1703 tplg_filename = devm_kasprintf(sdev->dev, GFP_KERNEL, 1704 "%s%s%d", 1705 sof_pdata->tplg_filename, 1706 "-ssp", 1707 ssp_num); 1708 if (!tplg_filename) 1709 return NULL; 1710 1711 sof_pdata->tplg_filename = tplg_filename; 1712 add_extension = true; 1713 1714 mclk_mask = check_nhlt_ssp_mclk_mask(sdev, ssp_num); 1715 1716 if (mclk_mask < 0) { 1717 dev_err(sdev->dev, "Invalid MCLK configuration\n"); 1718 return NULL; 1719 } 1720 1721 dev_dbg(sdev->dev, "MCLK mask %#x found in NHLT\n", mclk_mask); 1722 1723 if (mclk_mask) { 1724 dev_info(sdev->dev, "Overriding topology with MCLK mask %#x from NHLT\n", mclk_mask); 1725 sdev->mclk_id_override = true; 1726 sdev->mclk_id_quirk = (mclk_mask & BIT(0)) ? 0 : 1; 1727 } 1728 } 1729 1730 if (tplg_fixup && add_extension) { 1731 tplg_filename = devm_kasprintf(sdev->dev, GFP_KERNEL, 1732 "%s%s", 1733 sof_pdata->tplg_filename, 1734 ".tplg"); 1735 if (!tplg_filename) 1736 return NULL; 1737 1738 sof_pdata->tplg_filename = tplg_filename; 1739 } 1740 1741 /* check if mclk_id should be modified from topology defaults */ 1742 if (mclk_id_override >= 0) { 1743 dev_info(sdev->dev, "Overriding topology with MCLK %d from kernel_parameter\n", mclk_id_override); 1744 sdev->mclk_id_override = true; 1745 sdev->mclk_id_quirk = mclk_id_override; 1746 } 1747 } 1748 1749 /* If I2S fails, try SoundWire if it is supported */ 1750 if (!mach && (interface_mask & BIT(SOF_DAI_INTEL_ALH))) 1751 mach = hda_sdw_machine_select(sdev); 1752 1753 /* 1754 * Choose HDA generic machine driver if mach is NULL. 1755 * Otherwise, set certain mach params. 1756 */ 1757 hda_generic_machine_select(sdev, &mach); 1758 if (!mach) 1759 dev_warn(sdev->dev, "warning: No matching ASoC machine driver found\n"); 1760 1761 return mach; 1762 } 1763 1764 int hda_pci_intel_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) 1765 { 1766 int ret; 1767 1768 ret = snd_intel_dsp_driver_probe(pci); 1769 if (ret != SND_INTEL_DSP_DRIVER_ANY && ret != SND_INTEL_DSP_DRIVER_SOF) { 1770 dev_dbg(&pci->dev, "SOF PCI driver not selected, aborting probe\n"); 1771 return -ENODEV; 1772 } 1773 1774 return sof_pci_probe(pci, pci_id); 1775 } 1776 EXPORT_SYMBOL_NS(hda_pci_intel_probe, SND_SOC_SOF_INTEL_HDA_COMMON); 1777 1778 int hda_register_clients(struct snd_sof_dev *sdev) 1779 { 1780 return hda_probes_register(sdev); 1781 } 1782 1783 void hda_unregister_clients(struct snd_sof_dev *sdev) 1784 { 1785 hda_probes_unregister(sdev); 1786 } 1787 1788 MODULE_LICENSE("Dual BSD/GPL"); 1789 MODULE_IMPORT_NS(SND_SOC_SOF_PCI_DEV); 1790 MODULE_IMPORT_NS(SND_SOC_SOF_HDA_AUDIO_CODEC); 1791 MODULE_IMPORT_NS(SND_SOC_SOF_HDA_AUDIO_CODEC_I915); 1792 MODULE_IMPORT_NS(SND_SOC_SOF_XTENSA); 1793 MODULE_IMPORT_NS(SND_INTEL_SOUNDWIRE_ACPI); 1794 MODULE_IMPORT_NS(SOUNDWIRE_INTEL_INIT); 1795 MODULE_IMPORT_NS(SOUNDWIRE_INTEL); 1796 MODULE_IMPORT_NS(SND_SOC_SOF_HDA_MLINK); 1797