1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 // 3 // This file is provided under a dual BSD/GPLv2 license. When using or 4 // redistributing this file, you may do so under either license. 5 // 6 // Copyright(c) 2018 Intel Corporation. All rights reserved. 7 // 8 // Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com> 9 // Ranjani Sridharan <ranjani.sridharan@linux.intel.com> 10 // Rander Wang <rander.wang@intel.com> 11 // Keyon Jie <yang.jie@linux.intel.com> 12 // 13 14 /* 15 * Hardware interface for generic Intel audio DSP HDA IP 16 */ 17 18 #include <sound/hdaudio_ext.h> 19 #include <sound/hda_register.h> 20 21 #include <linux/acpi.h> 22 #include <linux/module.h> 23 #include <linux/soundwire/sdw.h> 24 #include <linux/soundwire/sdw_intel.h> 25 #include <sound/intel-dsp-config.h> 26 #include <sound/intel-nhlt.h> 27 #include <sound/sof.h> 28 #include <sound/sof/xtensa.h> 29 #include "../sof-audio.h" 30 #include "../sof-pci-dev.h" 31 #include "../ops.h" 32 #include "hda.h" 33 34 #define CREATE_TRACE_POINTS 35 #include <trace/events/sof_intel.h> 36 37 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) 38 #include <sound/soc-acpi-intel-match.h> 39 #endif 40 41 /* platform specific devices */ 42 #include "shim.h" 43 44 #define EXCEPT_MAX_HDR_SIZE 0x400 45 #define HDA_EXT_ROM_STATUS_SIZE 8 46 47 #if IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE) 48 49 /* 50 * The default for SoundWire clock stop quirks is to power gate the IP 51 * and do a Bus Reset, this will need to be modified when the DSP 52 * needs to remain in D0i3 so that the Master does not lose context 53 * and enumeration is not required on clock restart 54 */ 55 static int sdw_clock_stop_quirks = SDW_INTEL_CLK_STOP_BUS_RESET; 56 module_param(sdw_clock_stop_quirks, int, 0444); 57 MODULE_PARM_DESC(sdw_clock_stop_quirks, "SOF SoundWire clock stop quirks"); 58 59 static int sdw_params_stream(struct device *dev, 60 struct sdw_intel_stream_params_data *params_data) 61 { 62 struct snd_soc_dai *d = params_data->dai; 63 struct snd_soc_dapm_widget *w = snd_soc_dai_get_widget(d, params_data->stream); 64 struct snd_sof_dai_config_data data = { 0 }; 65 66 data.dai_index = (params_data->link_id << 8) | d->id; 67 data.dai_data = params_data->alh_stream_id; 68 69 return hda_dai_config(w, SOF_DAI_CONFIG_FLAGS_HW_PARAMS, &data); 70 } 71 72 struct sdw_intel_ops sdw_callback = { 73 .params_stream = sdw_params_stream, 74 }; 75 76 void hda_common_enable_sdw_irq(struct snd_sof_dev *sdev, bool enable) 77 { 78 struct sof_intel_hda_dev *hdev; 79 80 hdev = sdev->pdata->hw_pdata; 81 82 if (!hdev->sdw) 83 return; 84 85 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIC2, 86 HDA_DSP_REG_ADSPIC2_SNDW, 87 enable ? HDA_DSP_REG_ADSPIC2_SNDW : 0); 88 } 89 90 void hda_sdw_int_enable(struct snd_sof_dev *sdev, bool enable) 91 { 92 const struct sof_intel_dsp_desc *chip; 93 94 chip = get_chip_info(sdev->pdata); 95 if (chip && chip->enable_sdw_irq) 96 chip->enable_sdw_irq(sdev, enable); 97 } 98 99 static int hda_sdw_acpi_scan(struct snd_sof_dev *sdev) 100 { 101 struct sof_intel_hda_dev *hdev; 102 acpi_handle handle; 103 int ret; 104 105 handle = ACPI_HANDLE(sdev->dev); 106 107 /* save ACPI info for the probe step */ 108 hdev = sdev->pdata->hw_pdata; 109 110 ret = sdw_intel_acpi_scan(handle, &hdev->info); 111 if (ret < 0) 112 return -EINVAL; 113 114 return 0; 115 } 116 117 static int hda_sdw_probe(struct snd_sof_dev *sdev) 118 { 119 struct sof_intel_hda_dev *hdev; 120 struct sdw_intel_res res; 121 void *sdw; 122 123 hdev = sdev->pdata->hw_pdata; 124 125 memset(&res, 0, sizeof(res)); 126 127 res.hw_ops = &sdw_intel_cnl_hw_ops; 128 res.mmio_base = sdev->bar[HDA_DSP_BAR]; 129 res.shim_base = hdev->desc->sdw_shim_base; 130 res.alh_base = hdev->desc->sdw_alh_base; 131 res.irq = sdev->ipc_irq; 132 res.handle = hdev->info.handle; 133 res.parent = sdev->dev; 134 res.ops = &sdw_callback; 135 res.dev = sdev->dev; 136 res.clock_stop_quirks = sdw_clock_stop_quirks; 137 138 /* 139 * ops and arg fields are not populated for now, 140 * they will be needed when the DAI callbacks are 141 * provided 142 */ 143 144 /* we could filter links here if needed, e.g for quirks */ 145 res.count = hdev->info.count; 146 res.link_mask = hdev->info.link_mask; 147 148 sdw = sdw_intel_probe(&res); 149 if (!sdw) { 150 dev_err(sdev->dev, "error: SoundWire probe failed\n"); 151 return -EINVAL; 152 } 153 154 /* save context */ 155 hdev->sdw = sdw; 156 157 return 0; 158 } 159 160 int hda_sdw_check_lcount_common(struct snd_sof_dev *sdev) 161 { 162 struct sof_intel_hda_dev *hdev; 163 struct sdw_intel_ctx *ctx; 164 u32 caps; 165 166 hdev = sdev->pdata->hw_pdata; 167 ctx = hdev->sdw; 168 169 caps = snd_sof_dsp_read(sdev, HDA_DSP_BAR, ctx->shim_base + SDW_SHIM_LCAP); 170 caps &= SDW_SHIM_LCAP_LCOUNT_MASK; 171 172 /* Check HW supported vs property value */ 173 if (caps < ctx->count) { 174 dev_err(sdev->dev, 175 "BIOS master count %d is larger than hardware capabilities %d\n", 176 ctx->count, caps); 177 return -EINVAL; 178 } 179 180 return 0; 181 } 182 183 static int hda_sdw_check_lcount(struct snd_sof_dev *sdev) 184 { 185 const struct sof_intel_dsp_desc *chip; 186 187 chip = get_chip_info(sdev->pdata); 188 if (chip && chip->read_sdw_lcount) 189 return chip->read_sdw_lcount(sdev); 190 191 return 0; 192 } 193 194 int hda_sdw_startup(struct snd_sof_dev *sdev) 195 { 196 struct sof_intel_hda_dev *hdev; 197 struct snd_sof_pdata *pdata = sdev->pdata; 198 int ret; 199 200 hdev = sdev->pdata->hw_pdata; 201 202 if (!hdev->sdw) 203 return 0; 204 205 if (pdata->machine && !pdata->machine->mach_params.link_mask) 206 return 0; 207 208 ret = hda_sdw_check_lcount(sdev); 209 if (ret < 0) 210 return ret; 211 212 return sdw_intel_startup(hdev->sdw); 213 } 214 215 static int hda_sdw_exit(struct snd_sof_dev *sdev) 216 { 217 struct sof_intel_hda_dev *hdev; 218 219 hdev = sdev->pdata->hw_pdata; 220 221 hda_sdw_int_enable(sdev, false); 222 223 if (hdev->sdw) 224 sdw_intel_exit(hdev->sdw); 225 hdev->sdw = NULL; 226 227 return 0; 228 } 229 230 bool hda_common_check_sdw_irq(struct snd_sof_dev *sdev) 231 { 232 struct sof_intel_hda_dev *hdev; 233 bool ret = false; 234 u32 irq_status; 235 236 hdev = sdev->pdata->hw_pdata; 237 238 if (!hdev->sdw) 239 return ret; 240 241 /* store status */ 242 irq_status = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIS2); 243 244 /* invalid message ? */ 245 if (irq_status == 0xffffffff) 246 goto out; 247 248 /* SDW message ? */ 249 if (irq_status & HDA_DSP_REG_ADSPIS2_SNDW) 250 ret = true; 251 252 out: 253 return ret; 254 } 255 256 static bool hda_dsp_check_sdw_irq(struct snd_sof_dev *sdev) 257 { 258 const struct sof_intel_dsp_desc *chip; 259 260 chip = get_chip_info(sdev->pdata); 261 if (chip && chip->check_sdw_irq) 262 return chip->check_sdw_irq(sdev); 263 264 return false; 265 } 266 267 static irqreturn_t hda_dsp_sdw_thread(int irq, void *context) 268 { 269 return sdw_intel_thread(irq, context); 270 } 271 272 static bool hda_sdw_check_wakeen_irq(struct snd_sof_dev *sdev) 273 { 274 struct sof_intel_hda_dev *hdev; 275 276 hdev = sdev->pdata->hw_pdata; 277 if (hdev->sdw && 278 snd_sof_dsp_read(sdev, HDA_DSP_BAR, 279 hdev->desc->sdw_shim_base + SDW_SHIM_WAKESTS)) 280 return true; 281 282 return false; 283 } 284 285 void hda_sdw_process_wakeen(struct snd_sof_dev *sdev) 286 { 287 struct sof_intel_hda_dev *hdev; 288 289 hdev = sdev->pdata->hw_pdata; 290 if (!hdev->sdw) 291 return; 292 293 sdw_intel_process_wakeen_event(hdev->sdw); 294 } 295 296 #else /* IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE) */ 297 static inline int hda_sdw_acpi_scan(struct snd_sof_dev *sdev) 298 { 299 return 0; 300 } 301 302 static inline int hda_sdw_probe(struct snd_sof_dev *sdev) 303 { 304 return 0; 305 } 306 307 static inline int hda_sdw_exit(struct snd_sof_dev *sdev) 308 { 309 return 0; 310 } 311 312 static inline bool hda_dsp_check_sdw_irq(struct snd_sof_dev *sdev) 313 { 314 return false; 315 } 316 317 static inline irqreturn_t hda_dsp_sdw_thread(int irq, void *context) 318 { 319 return IRQ_HANDLED; 320 } 321 322 static inline bool hda_sdw_check_wakeen_irq(struct snd_sof_dev *sdev) 323 { 324 return false; 325 } 326 327 #endif /* IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE) */ 328 329 /* 330 * Debug 331 */ 332 333 struct hda_dsp_msg_code { 334 u32 code; 335 const char *text; 336 }; 337 338 #if IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG) 339 static bool hda_use_msi = true; 340 module_param_named(use_msi, hda_use_msi, bool, 0444); 341 MODULE_PARM_DESC(use_msi, "SOF HDA use PCI MSI mode"); 342 #else 343 #define hda_use_msi (1) 344 #endif 345 346 int sof_hda_position_quirk = SOF_HDA_POSITION_QUIRK_USE_DPIB_REGISTERS; 347 module_param_named(position_quirk, sof_hda_position_quirk, int, 0444); 348 MODULE_PARM_DESC(position_quirk, "SOF HDaudio position quirk"); 349 350 static char *hda_model; 351 module_param(hda_model, charp, 0444); 352 MODULE_PARM_DESC(hda_model, "Use the given HDA board model."); 353 354 static int dmic_num_override = -1; 355 module_param_named(dmic_num, dmic_num_override, int, 0444); 356 MODULE_PARM_DESC(dmic_num, "SOF HDA DMIC number"); 357 358 static int mclk_id_override = -1; 359 module_param_named(mclk_id, mclk_id_override, int, 0444); 360 MODULE_PARM_DESC(mclk_id, "SOF SSP mclk_id"); 361 362 static const struct hda_dsp_msg_code hda_dsp_rom_fw_error_texts[] = { 363 {HDA_DSP_ROM_CSE_ERROR, "error: cse error"}, 364 {HDA_DSP_ROM_CSE_WRONG_RESPONSE, "error: cse wrong response"}, 365 {HDA_DSP_ROM_IMR_TO_SMALL, "error: IMR too small"}, 366 {HDA_DSP_ROM_BASE_FW_NOT_FOUND, "error: base fw not found"}, 367 {HDA_DSP_ROM_CSE_VALIDATION_FAILED, "error: signature verification failed"}, 368 {HDA_DSP_ROM_IPC_FATAL_ERROR, "error: ipc fatal error"}, 369 {HDA_DSP_ROM_L2_CACHE_ERROR, "error: L2 cache error"}, 370 {HDA_DSP_ROM_LOAD_OFFSET_TO_SMALL, "error: load offset too small"}, 371 {HDA_DSP_ROM_API_PTR_INVALID, "error: API ptr invalid"}, 372 {HDA_DSP_ROM_BASEFW_INCOMPAT, "error: base fw incompatible"}, 373 {HDA_DSP_ROM_UNHANDLED_INTERRUPT, "error: unhandled interrupt"}, 374 {HDA_DSP_ROM_MEMORY_HOLE_ECC, "error: ECC memory hole"}, 375 {HDA_DSP_ROM_KERNEL_EXCEPTION, "error: kernel exception"}, 376 {HDA_DSP_ROM_USER_EXCEPTION, "error: user exception"}, 377 {HDA_DSP_ROM_UNEXPECTED_RESET, "error: unexpected reset"}, 378 {HDA_DSP_ROM_NULL_FW_ENTRY, "error: null FW entry point"}, 379 }; 380 381 #define FSR_ROM_STATE_ENTRY(state) {FSR_STATE_ROM_##state, #state} 382 static const struct hda_dsp_msg_code fsr_rom_state_names[] = { 383 FSR_ROM_STATE_ENTRY(INIT), 384 FSR_ROM_STATE_ENTRY(INIT_DONE), 385 FSR_ROM_STATE_ENTRY(CSE_MANIFEST_LOADED), 386 FSR_ROM_STATE_ENTRY(FW_MANIFEST_LOADED), 387 FSR_ROM_STATE_ENTRY(FW_FW_LOADED), 388 FSR_ROM_STATE_ENTRY(FW_ENTERED), 389 FSR_ROM_STATE_ENTRY(VERIFY_FEATURE_MASK), 390 FSR_ROM_STATE_ENTRY(GET_LOAD_OFFSET), 391 FSR_ROM_STATE_ENTRY(FETCH_ROM_EXT), 392 FSR_ROM_STATE_ENTRY(FETCH_ROM_EXT_DONE), 393 /* CSE states */ 394 FSR_ROM_STATE_ENTRY(CSE_IMR_REQUEST), 395 FSR_ROM_STATE_ENTRY(CSE_IMR_GRANTED), 396 FSR_ROM_STATE_ENTRY(CSE_VALIDATE_IMAGE_REQUEST), 397 FSR_ROM_STATE_ENTRY(CSE_IMAGE_VALIDATED), 398 FSR_ROM_STATE_ENTRY(CSE_IPC_IFACE_INIT), 399 FSR_ROM_STATE_ENTRY(CSE_IPC_RESET_PHASE_1), 400 FSR_ROM_STATE_ENTRY(CSE_IPC_OPERATIONAL_ENTRY), 401 FSR_ROM_STATE_ENTRY(CSE_IPC_OPERATIONAL), 402 FSR_ROM_STATE_ENTRY(CSE_IPC_DOWN), 403 }; 404 405 #define FSR_BRINGUP_STATE_ENTRY(state) {FSR_STATE_BRINGUP_##state, #state} 406 static const struct hda_dsp_msg_code fsr_bringup_state_names[] = { 407 FSR_BRINGUP_STATE_ENTRY(INIT), 408 FSR_BRINGUP_STATE_ENTRY(INIT_DONE), 409 FSR_BRINGUP_STATE_ENTRY(HPSRAM_LOAD), 410 FSR_BRINGUP_STATE_ENTRY(UNPACK_START), 411 FSR_BRINGUP_STATE_ENTRY(IMR_RESTORE), 412 FSR_BRINGUP_STATE_ENTRY(FW_ENTERED), 413 }; 414 415 #define FSR_WAIT_STATE_ENTRY(state) {FSR_WAIT_FOR_##state, #state} 416 static const struct hda_dsp_msg_code fsr_wait_state_names[] = { 417 FSR_WAIT_STATE_ENTRY(IPC_BUSY), 418 FSR_WAIT_STATE_ENTRY(IPC_DONE), 419 FSR_WAIT_STATE_ENTRY(CACHE_INVALIDATION), 420 FSR_WAIT_STATE_ENTRY(LP_SRAM_OFF), 421 FSR_WAIT_STATE_ENTRY(DMA_BUFFER_FULL), 422 FSR_WAIT_STATE_ENTRY(CSE_CSR), 423 }; 424 425 #define FSR_MODULE_NAME_ENTRY(mod) [FSR_MOD_##mod] = #mod 426 static const char * const fsr_module_names[] = { 427 FSR_MODULE_NAME_ENTRY(ROM), 428 FSR_MODULE_NAME_ENTRY(ROM_BYP), 429 FSR_MODULE_NAME_ENTRY(BASE_FW), 430 FSR_MODULE_NAME_ENTRY(LP_BOOT), 431 FSR_MODULE_NAME_ENTRY(BRNGUP), 432 FSR_MODULE_NAME_ENTRY(ROM_EXT), 433 }; 434 435 static const char * 436 hda_dsp_get_state_text(u32 code, const struct hda_dsp_msg_code *msg_code, 437 size_t array_size) 438 { 439 int i; 440 441 for (i = 0; i < array_size; i++) { 442 if (code == msg_code[i].code) 443 return msg_code[i].text; 444 } 445 446 return NULL; 447 } 448 449 static void hda_dsp_get_state(struct snd_sof_dev *sdev, const char *level) 450 { 451 const struct sof_intel_dsp_desc *chip = get_chip_info(sdev->pdata); 452 const char *state_text, *error_text, *module_text; 453 u32 fsr, state, wait_state, module, error_code; 454 455 fsr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, chip->rom_status_reg); 456 state = FSR_TO_STATE_CODE(fsr); 457 wait_state = FSR_TO_WAIT_STATE_CODE(fsr); 458 module = FSR_TO_MODULE_CODE(fsr); 459 460 if (module > FSR_MOD_ROM_EXT) 461 module_text = "unknown"; 462 else 463 module_text = fsr_module_names[module]; 464 465 if (module == FSR_MOD_BRNGUP) 466 state_text = hda_dsp_get_state_text(state, fsr_bringup_state_names, 467 ARRAY_SIZE(fsr_bringup_state_names)); 468 else 469 state_text = hda_dsp_get_state_text(state, fsr_rom_state_names, 470 ARRAY_SIZE(fsr_rom_state_names)); 471 472 /* not for us, must be generic sof message */ 473 if (!state_text) { 474 dev_printk(level, sdev->dev, "%#010x: unknown ROM status value\n", fsr); 475 return; 476 } 477 478 if (wait_state) { 479 const char *wait_state_text; 480 481 wait_state_text = hda_dsp_get_state_text(wait_state, fsr_wait_state_names, 482 ARRAY_SIZE(fsr_wait_state_names)); 483 if (!wait_state_text) 484 wait_state_text = "unknown"; 485 486 dev_printk(level, sdev->dev, 487 "%#010x: module: %s, state: %s, waiting for: %s, %s\n", 488 fsr, module_text, state_text, wait_state_text, 489 fsr & FSR_HALTED ? "not running" : "running"); 490 } else { 491 dev_printk(level, sdev->dev, "%#010x: module: %s, state: %s, %s\n", 492 fsr, module_text, state_text, 493 fsr & FSR_HALTED ? "not running" : "running"); 494 } 495 496 error_code = snd_sof_dsp_read(sdev, HDA_DSP_BAR, chip->rom_status_reg + 4); 497 if (!error_code) 498 return; 499 500 error_text = hda_dsp_get_state_text(error_code, hda_dsp_rom_fw_error_texts, 501 ARRAY_SIZE(hda_dsp_rom_fw_error_texts)); 502 if (!error_text) 503 error_text = "unknown"; 504 505 if (state == FSR_STATE_FW_ENTERED) 506 dev_printk(level, sdev->dev, "status code: %#x (%s)\n", error_code, 507 error_text); 508 else 509 dev_printk(level, sdev->dev, "error code: %#x (%s)\n", error_code, 510 error_text); 511 } 512 513 static void hda_dsp_get_registers(struct snd_sof_dev *sdev, 514 struct sof_ipc_dsp_oops_xtensa *xoops, 515 struct sof_ipc_panic_info *panic_info, 516 u32 *stack, size_t stack_words) 517 { 518 u32 offset = sdev->dsp_oops_offset; 519 520 /* first read registers */ 521 sof_mailbox_read(sdev, offset, xoops, sizeof(*xoops)); 522 523 /* note: variable AR register array is not read */ 524 525 /* then get panic info */ 526 if (xoops->arch_hdr.totalsize > EXCEPT_MAX_HDR_SIZE) { 527 dev_err(sdev->dev, "invalid header size 0x%x. FW oops is bogus\n", 528 xoops->arch_hdr.totalsize); 529 return; 530 } 531 offset += xoops->arch_hdr.totalsize; 532 sof_block_read(sdev, sdev->mmio_bar, offset, 533 panic_info, sizeof(*panic_info)); 534 535 /* then get the stack */ 536 offset += sizeof(*panic_info); 537 sof_block_read(sdev, sdev->mmio_bar, offset, stack, 538 stack_words * sizeof(u32)); 539 } 540 541 /* dump the first 8 dwords representing the extended ROM status */ 542 static void hda_dsp_dump_ext_rom_status(struct snd_sof_dev *sdev, const char *level, 543 u32 flags) 544 { 545 const struct sof_intel_dsp_desc *chip; 546 char msg[128]; 547 int len = 0; 548 u32 value; 549 int i; 550 551 chip = get_chip_info(sdev->pdata); 552 for (i = 0; i < HDA_EXT_ROM_STATUS_SIZE; i++) { 553 value = snd_sof_dsp_read(sdev, HDA_DSP_BAR, chip->rom_status_reg + i * 0x4); 554 len += scnprintf(msg + len, sizeof(msg) - len, " 0x%x", value); 555 } 556 557 dev_printk(level, sdev->dev, "extended rom status: %s", msg); 558 559 } 560 561 void hda_dsp_dump(struct snd_sof_dev *sdev, u32 flags) 562 { 563 char *level = (flags & SOF_DBG_DUMP_OPTIONAL) ? KERN_DEBUG : KERN_ERR; 564 struct sof_ipc_dsp_oops_xtensa xoops; 565 struct sof_ipc_panic_info panic_info; 566 u32 stack[HDA_DSP_STACK_DUMP_SIZE]; 567 568 /* print ROM/FW status */ 569 hda_dsp_get_state(sdev, level); 570 571 /* The firmware register dump only available with IPC3 */ 572 if (flags & SOF_DBG_DUMP_REGS && sdev->pdata->ipc_type == SOF_IPC) { 573 u32 status = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_SRAM_REG_FW_STATUS); 574 u32 panic = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_SRAM_REG_FW_TRACEP); 575 576 hda_dsp_get_registers(sdev, &xoops, &panic_info, stack, 577 HDA_DSP_STACK_DUMP_SIZE); 578 sof_print_oops_and_stack(sdev, level, status, panic, &xoops, 579 &panic_info, stack, HDA_DSP_STACK_DUMP_SIZE); 580 } else { 581 hda_dsp_dump_ext_rom_status(sdev, level, flags); 582 } 583 } 584 585 static bool hda_check_ipc_irq(struct snd_sof_dev *sdev) 586 { 587 const struct sof_intel_dsp_desc *chip; 588 589 chip = get_chip_info(sdev->pdata); 590 if (chip && chip->check_ipc_irq) 591 return chip->check_ipc_irq(sdev); 592 593 return false; 594 } 595 596 void hda_ipc_irq_dump(struct snd_sof_dev *sdev) 597 { 598 u32 adspis; 599 u32 intsts; 600 u32 intctl; 601 u32 ppsts; 602 u8 rirbsts; 603 604 /* read key IRQ stats and config registers */ 605 adspis = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIS); 606 intsts = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTSTS); 607 intctl = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL); 608 ppsts = snd_sof_dsp_read(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPSTS); 609 rirbsts = snd_sof_dsp_read8(sdev, HDA_DSP_HDA_BAR, AZX_REG_RIRBSTS); 610 611 dev_err(sdev->dev, "hda irq intsts 0x%8.8x intlctl 0x%8.8x rirb %2.2x\n", 612 intsts, intctl, rirbsts); 613 dev_err(sdev->dev, "dsp irq ppsts 0x%8.8x adspis 0x%8.8x\n", ppsts, adspis); 614 } 615 616 void hda_ipc_dump(struct snd_sof_dev *sdev) 617 { 618 u32 hipcie; 619 u32 hipct; 620 u32 hipcctl; 621 622 hda_ipc_irq_dump(sdev); 623 624 /* read IPC status */ 625 hipcie = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCIE); 626 hipct = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCT); 627 hipcctl = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCCTL); 628 629 /* dump the IPC regs */ 630 /* TODO: parse the raw msg */ 631 dev_err(sdev->dev, "host status 0x%8.8x dsp status 0x%8.8x mask 0x%8.8x\n", 632 hipcie, hipct, hipcctl); 633 } 634 635 void hda_ipc4_dump(struct snd_sof_dev *sdev) 636 { 637 u32 hipci, hipcie, hipct, hipcte, hipcctl; 638 639 hda_ipc_irq_dump(sdev); 640 641 hipci = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCI); 642 hipcie = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCIE); 643 hipct = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCT); 644 hipcte = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCTE); 645 hipcctl = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCCTL); 646 647 /* dump the IPC regs */ 648 /* TODO: parse the raw msg */ 649 dev_err(sdev->dev, "Host IPC initiator: %#x|%#x, target: %#x|%#x, ctl: %#x\n", 650 hipci, hipcie, hipct, hipcte, hipcctl); 651 } 652 653 bool hda_ipc4_tx_is_busy(struct snd_sof_dev *sdev) 654 { 655 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 656 const struct sof_intel_dsp_desc *chip = hda->desc; 657 u32 val; 658 659 val = snd_sof_dsp_read(sdev, HDA_DSP_BAR, chip->ipc_req); 660 661 return !!(val & chip->ipc_req_mask); 662 } 663 664 static int hda_init(struct snd_sof_dev *sdev) 665 { 666 struct hda_bus *hbus; 667 struct hdac_bus *bus; 668 struct pci_dev *pci = to_pci_dev(sdev->dev); 669 int ret; 670 671 hbus = sof_to_hbus(sdev); 672 bus = sof_to_bus(sdev); 673 674 /* HDA bus init */ 675 sof_hda_bus_init(sdev, &pci->dev); 676 677 if (sof_hda_position_quirk == SOF_HDA_POSITION_QUIRK_USE_DPIB_REGISTERS) 678 bus->use_posbuf = 0; 679 else 680 bus->use_posbuf = 1; 681 bus->bdl_pos_adj = 0; 682 bus->sync_write = 1; 683 684 mutex_init(&hbus->prepare_mutex); 685 hbus->pci = pci; 686 hbus->mixer_assigned = -1; 687 hbus->modelname = hda_model; 688 689 /* initialise hdac bus */ 690 bus->addr = pci_resource_start(pci, 0); 691 bus->remap_addr = pci_ioremap_bar(pci, 0); 692 if (!bus->remap_addr) { 693 dev_err(bus->dev, "error: ioremap error\n"); 694 return -ENXIO; 695 } 696 697 /* HDA base */ 698 sdev->bar[HDA_DSP_HDA_BAR] = bus->remap_addr; 699 700 /* init i915 and HDMI codecs */ 701 ret = hda_codec_i915_init(sdev); 702 if (ret < 0) 703 dev_warn(sdev->dev, "init of i915 and HDMI codec failed\n"); 704 705 /* get controller capabilities */ 706 ret = hda_dsp_ctrl_get_caps(sdev); 707 if (ret < 0) 708 dev_err(sdev->dev, "error: get caps error\n"); 709 710 return ret; 711 } 712 713 static int check_dmic_num(struct snd_sof_dev *sdev) 714 { 715 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata; 716 struct nhlt_acpi_table *nhlt; 717 int dmic_num = 0; 718 719 nhlt = hdev->nhlt; 720 if (nhlt) 721 dmic_num = intel_nhlt_get_dmic_geo(sdev->dev, nhlt); 722 723 /* allow for module parameter override */ 724 if (dmic_num_override != -1) { 725 dev_dbg(sdev->dev, 726 "overriding DMICs detected in NHLT tables %d by kernel param %d\n", 727 dmic_num, dmic_num_override); 728 dmic_num = dmic_num_override; 729 } 730 731 if (dmic_num < 0 || dmic_num > 4) { 732 dev_dbg(sdev->dev, "invalid dmic_number %d\n", dmic_num); 733 dmic_num = 0; 734 } 735 736 return dmic_num; 737 } 738 739 static int check_nhlt_ssp_mask(struct snd_sof_dev *sdev) 740 { 741 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata; 742 struct nhlt_acpi_table *nhlt; 743 int ssp_mask = 0; 744 745 nhlt = hdev->nhlt; 746 if (!nhlt) 747 return ssp_mask; 748 749 if (intel_nhlt_has_endpoint_type(nhlt, NHLT_LINK_SSP)) { 750 ssp_mask = intel_nhlt_ssp_endpoint_mask(nhlt, NHLT_DEVICE_I2S); 751 if (ssp_mask) 752 dev_info(sdev->dev, "NHLT_DEVICE_I2S detected, ssp_mask %#x\n", ssp_mask); 753 } 754 755 return ssp_mask; 756 } 757 758 static int check_nhlt_ssp_mclk_mask(struct snd_sof_dev *sdev, int ssp_num) 759 { 760 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata; 761 struct nhlt_acpi_table *nhlt; 762 763 nhlt = hdev->nhlt; 764 if (!nhlt) 765 return 0; 766 767 return intel_nhlt_ssp_mclk_mask(nhlt, ssp_num); 768 } 769 770 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC) || IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE) 771 772 static const char *fixup_tplg_name(struct snd_sof_dev *sdev, 773 const char *sof_tplg_filename, 774 const char *idisp_str, 775 const char *dmic_str) 776 { 777 const char *tplg_filename = NULL; 778 char *filename, *tmp; 779 const char *split_ext; 780 781 filename = kstrdup(sof_tplg_filename, GFP_KERNEL); 782 if (!filename) 783 return NULL; 784 785 /* this assumes a .tplg extension */ 786 tmp = filename; 787 split_ext = strsep(&tmp, "."); 788 if (split_ext) 789 tplg_filename = devm_kasprintf(sdev->dev, GFP_KERNEL, 790 "%s%s%s.tplg", 791 split_ext, idisp_str, dmic_str); 792 kfree(filename); 793 794 return tplg_filename; 795 } 796 797 static int dmic_detect_topology_fixup(struct snd_sof_dev *sdev, 798 const char **tplg_filename, 799 const char *idisp_str, 800 int *dmic_found, 801 bool tplg_fixup) 802 { 803 const char *dmic_str; 804 int dmic_num; 805 806 /* first check for DMICs (using NHLT or module parameter) */ 807 dmic_num = check_dmic_num(sdev); 808 809 switch (dmic_num) { 810 case 1: 811 dmic_str = "-1ch"; 812 break; 813 case 2: 814 dmic_str = "-2ch"; 815 break; 816 case 3: 817 dmic_str = "-3ch"; 818 break; 819 case 4: 820 dmic_str = "-4ch"; 821 break; 822 default: 823 dmic_num = 0; 824 dmic_str = ""; 825 break; 826 } 827 828 if (tplg_fixup) { 829 const char *default_tplg_filename = *tplg_filename; 830 const char *fixed_tplg_filename; 831 832 fixed_tplg_filename = fixup_tplg_name(sdev, default_tplg_filename, 833 idisp_str, dmic_str); 834 if (!fixed_tplg_filename) 835 return -ENOMEM; 836 *tplg_filename = fixed_tplg_filename; 837 } 838 839 dev_info(sdev->dev, "DMICs detected in NHLT tables: %d\n", dmic_num); 840 *dmic_found = dmic_num; 841 842 return 0; 843 } 844 #endif 845 846 static int hda_init_caps(struct snd_sof_dev *sdev) 847 { 848 struct hdac_bus *bus = sof_to_bus(sdev); 849 struct snd_sof_pdata *pdata = sdev->pdata; 850 struct sof_intel_hda_dev *hdev = pdata->hw_pdata; 851 u32 link_mask; 852 int ret = 0; 853 854 /* check if dsp is there */ 855 if (bus->ppcap) 856 dev_dbg(sdev->dev, "PP capability, will probe DSP later.\n"); 857 858 /* Init HDA controller after i915 init */ 859 ret = hda_dsp_ctrl_init_chip(sdev); 860 if (ret < 0) { 861 dev_err(bus->dev, "error: init chip failed with ret: %d\n", 862 ret); 863 return ret; 864 } 865 866 hda_bus_ml_get_capabilities(bus); 867 868 /* scan SoundWire capabilities exposed by DSDT */ 869 ret = hda_sdw_acpi_scan(sdev); 870 if (ret < 0) { 871 dev_dbg(sdev->dev, "skipping SoundWire, not detected with ACPI scan\n"); 872 goto skip_soundwire; 873 } 874 875 link_mask = hdev->info.link_mask; 876 if (!link_mask) { 877 dev_dbg(sdev->dev, "skipping SoundWire, no links enabled\n"); 878 goto skip_soundwire; 879 } 880 881 /* 882 * probe/allocate SoundWire resources. 883 * The hardware configuration takes place in hda_sdw_startup 884 * after power rails are enabled. 885 * It's entirely possible to have a mix of I2S/DMIC/SoundWire 886 * devices, so we allocate the resources in all cases. 887 */ 888 ret = hda_sdw_probe(sdev); 889 if (ret < 0) { 890 dev_err(sdev->dev, "error: SoundWire probe error\n"); 891 return ret; 892 } 893 894 skip_soundwire: 895 896 /* create codec instances */ 897 hda_codec_probe_bus(sdev); 898 899 if (!HDA_IDISP_CODEC(bus->codec_mask)) 900 hda_codec_i915_display_power(sdev, false); 901 902 hda_bus_ml_put_all(bus); 903 904 return 0; 905 } 906 907 static irqreturn_t hda_dsp_interrupt_handler(int irq, void *context) 908 { 909 struct snd_sof_dev *sdev = context; 910 911 /* 912 * Get global interrupt status. It includes all hardware interrupt 913 * sources in the Intel HD Audio controller. 914 */ 915 if (snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTSTS) & 916 SOF_HDA_INTSTS_GIS) { 917 918 /* disable GIE interrupt */ 919 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, 920 SOF_HDA_INTCTL, 921 SOF_HDA_INT_GLOBAL_EN, 922 0); 923 924 return IRQ_WAKE_THREAD; 925 } 926 927 return IRQ_NONE; 928 } 929 930 static irqreturn_t hda_dsp_interrupt_thread(int irq, void *context) 931 { 932 struct snd_sof_dev *sdev = context; 933 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata; 934 935 /* deal with streams and controller first */ 936 if (hda_dsp_check_stream_irq(sdev)) { 937 trace_sof_intel_hda_irq(sdev, "stream"); 938 hda_dsp_stream_threaded_handler(irq, sdev); 939 } 940 941 if (hda_check_ipc_irq(sdev)) { 942 trace_sof_intel_hda_irq(sdev, "ipc"); 943 sof_ops(sdev)->irq_thread(irq, sdev); 944 } 945 946 if (hda_dsp_check_sdw_irq(sdev)) { 947 trace_sof_intel_hda_irq(sdev, "sdw"); 948 hda_dsp_sdw_thread(irq, hdev->sdw); 949 } 950 951 if (hda_sdw_check_wakeen_irq(sdev)) { 952 trace_sof_intel_hda_irq(sdev, "wakeen"); 953 hda_sdw_process_wakeen(sdev); 954 } 955 956 hda_codec_check_for_state_change(sdev); 957 958 /* enable GIE interrupt */ 959 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, 960 SOF_HDA_INTCTL, 961 SOF_HDA_INT_GLOBAL_EN, 962 SOF_HDA_INT_GLOBAL_EN); 963 964 return IRQ_HANDLED; 965 } 966 967 int hda_dsp_probe(struct snd_sof_dev *sdev) 968 { 969 struct pci_dev *pci = to_pci_dev(sdev->dev); 970 struct sof_intel_hda_dev *hdev; 971 struct hdac_bus *bus; 972 const struct sof_intel_dsp_desc *chip; 973 int ret = 0; 974 975 /* 976 * detect DSP by checking class/subclass/prog-id information 977 * class=04 subclass 03 prog-if 00: no DSP, legacy driver is required 978 * class=04 subclass 01 prog-if 00: DSP is present 979 * (and may be required e.g. for DMIC or SSP support) 980 * class=04 subclass 03 prog-if 80: either of DSP or legacy mode works 981 */ 982 if (pci->class == 0x040300) { 983 dev_err(sdev->dev, "error: the DSP is not enabled on this platform, aborting probe\n"); 984 return -ENODEV; 985 } else if (pci->class != 0x040100 && pci->class != 0x040380) { 986 dev_err(sdev->dev, "error: unknown PCI class/subclass/prog-if 0x%06x found, aborting probe\n", pci->class); 987 return -ENODEV; 988 } 989 dev_info(sdev->dev, "DSP detected with PCI class/subclass/prog-if 0x%06x\n", pci->class); 990 991 chip = get_chip_info(sdev->pdata); 992 if (!chip) { 993 dev_err(sdev->dev, "error: no such device supported, chip id:%x\n", 994 pci->device); 995 ret = -EIO; 996 goto err; 997 } 998 999 sdev->num_cores = chip->cores_num; 1000 1001 hdev = devm_kzalloc(sdev->dev, sizeof(*hdev), GFP_KERNEL); 1002 if (!hdev) 1003 return -ENOMEM; 1004 sdev->pdata->hw_pdata = hdev; 1005 hdev->desc = chip; 1006 1007 hdev->dmic_dev = platform_device_register_data(sdev->dev, "dmic-codec", 1008 PLATFORM_DEVID_NONE, 1009 NULL, 0); 1010 if (IS_ERR(hdev->dmic_dev)) { 1011 dev_err(sdev->dev, "error: failed to create DMIC device\n"); 1012 return PTR_ERR(hdev->dmic_dev); 1013 } 1014 1015 /* 1016 * use position update IPC if either it is forced 1017 * or we don't have other choice 1018 */ 1019 #if IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG_FORCE_IPC_POSITION) 1020 hdev->no_ipc_position = 0; 1021 #else 1022 hdev->no_ipc_position = sof_ops(sdev)->pcm_pointer ? 1 : 0; 1023 #endif 1024 1025 /* set up HDA base */ 1026 bus = sof_to_bus(sdev); 1027 ret = hda_init(sdev); 1028 if (ret < 0) 1029 goto hdac_bus_unmap; 1030 1031 /* DSP base */ 1032 sdev->bar[HDA_DSP_BAR] = pci_ioremap_bar(pci, HDA_DSP_BAR); 1033 if (!sdev->bar[HDA_DSP_BAR]) { 1034 dev_err(sdev->dev, "error: ioremap error\n"); 1035 ret = -ENXIO; 1036 goto hdac_bus_unmap; 1037 } 1038 1039 sdev->mmio_bar = HDA_DSP_BAR; 1040 sdev->mailbox_bar = HDA_DSP_BAR; 1041 1042 /* allow 64bit DMA address if supported by H/W */ 1043 if (dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(64))) { 1044 dev_dbg(sdev->dev, "DMA mask is 32 bit\n"); 1045 dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(32)); 1046 } 1047 dma_set_max_seg_size(&pci->dev, UINT_MAX); 1048 1049 /* init streams */ 1050 ret = hda_dsp_stream_init(sdev); 1051 if (ret < 0) { 1052 dev_err(sdev->dev, "error: failed to init streams\n"); 1053 /* 1054 * not all errors are due to memory issues, but trying 1055 * to free everything does not harm 1056 */ 1057 goto free_streams; 1058 } 1059 1060 /* 1061 * register our IRQ 1062 * let's try to enable msi firstly 1063 * if it fails, use legacy interrupt mode 1064 * TODO: support msi multiple vectors 1065 */ 1066 if (hda_use_msi && pci_alloc_irq_vectors(pci, 1, 1, PCI_IRQ_MSI) > 0) { 1067 dev_info(sdev->dev, "use msi interrupt mode\n"); 1068 sdev->ipc_irq = pci_irq_vector(pci, 0); 1069 /* initialised to "false" by kzalloc() */ 1070 sdev->msi_enabled = true; 1071 } 1072 1073 if (!sdev->msi_enabled) { 1074 dev_info(sdev->dev, "use legacy interrupt mode\n"); 1075 /* 1076 * in IO-APIC mode, hda->irq and ipc_irq are using the same 1077 * irq number of pci->irq 1078 */ 1079 sdev->ipc_irq = pci->irq; 1080 } 1081 1082 dev_dbg(sdev->dev, "using IPC IRQ %d\n", sdev->ipc_irq); 1083 ret = request_threaded_irq(sdev->ipc_irq, hda_dsp_interrupt_handler, 1084 hda_dsp_interrupt_thread, 1085 IRQF_SHARED, "AudioDSP", sdev); 1086 if (ret < 0) { 1087 dev_err(sdev->dev, "error: failed to register IPC IRQ %d\n", 1088 sdev->ipc_irq); 1089 goto free_irq_vector; 1090 } 1091 1092 pci_set_master(pci); 1093 synchronize_irq(pci->irq); 1094 1095 /* 1096 * clear TCSEL to clear playback on some HD Audio 1097 * codecs. PCI TCSEL is defined in the Intel manuals. 1098 */ 1099 snd_sof_pci_update_bits(sdev, PCI_TCSEL, 0x07, 0); 1100 1101 /* init HDA capabilities */ 1102 ret = hda_init_caps(sdev); 1103 if (ret < 0) 1104 goto free_ipc_irq; 1105 1106 /* enable ppcap interrupt */ 1107 hda_dsp_ctrl_ppcap_enable(sdev, true); 1108 hda_dsp_ctrl_ppcap_int_enable(sdev, true); 1109 1110 /* set default mailbox offset for FW ready message */ 1111 sdev->dsp_box.offset = HDA_DSP_MBOX_UPLINK_OFFSET; 1112 1113 INIT_DELAYED_WORK(&hdev->d0i3_work, hda_dsp_d0i3_work); 1114 1115 init_waitqueue_head(&hdev->waitq); 1116 1117 hdev->nhlt = intel_nhlt_init(sdev->dev); 1118 1119 return 0; 1120 1121 free_ipc_irq: 1122 free_irq(sdev->ipc_irq, sdev); 1123 free_irq_vector: 1124 if (sdev->msi_enabled) 1125 pci_free_irq_vectors(pci); 1126 free_streams: 1127 hda_dsp_stream_free(sdev); 1128 /* dsp_unmap: not currently used */ 1129 iounmap(sdev->bar[HDA_DSP_BAR]); 1130 hdac_bus_unmap: 1131 platform_device_unregister(hdev->dmic_dev); 1132 iounmap(bus->remap_addr); 1133 hda_codec_i915_exit(sdev); 1134 err: 1135 return ret; 1136 } 1137 1138 int hda_dsp_remove(struct snd_sof_dev *sdev) 1139 { 1140 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 1141 const struct sof_intel_dsp_desc *chip = hda->desc; 1142 struct hdac_bus *bus = sof_to_bus(sdev); 1143 struct pci_dev *pci = to_pci_dev(sdev->dev); 1144 struct nhlt_acpi_table *nhlt = hda->nhlt; 1145 1146 if (nhlt) 1147 intel_nhlt_free(nhlt); 1148 1149 /* cancel any attempt for DSP D0I3 */ 1150 cancel_delayed_work_sync(&hda->d0i3_work); 1151 1152 hda_codec_device_remove(sdev); 1153 1154 hda_sdw_exit(sdev); 1155 1156 if (!IS_ERR_OR_NULL(hda->dmic_dev)) 1157 platform_device_unregister(hda->dmic_dev); 1158 1159 /* disable DSP IRQ */ 1160 snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL, 1161 SOF_HDA_PPCTL_PIE, 0); 1162 1163 /* disable CIE and GIE interrupts */ 1164 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL, 1165 SOF_HDA_INT_CTRL_EN | SOF_HDA_INT_GLOBAL_EN, 0); 1166 1167 /* no need to check for error as the DSP will be disabled anyway */ 1168 if (chip && chip->power_down_dsp) 1169 chip->power_down_dsp(sdev); 1170 1171 /* disable DSP */ 1172 snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL, 1173 SOF_HDA_PPCTL_GPROCEN, 0); 1174 1175 free_irq(sdev->ipc_irq, sdev); 1176 if (sdev->msi_enabled) 1177 pci_free_irq_vectors(pci); 1178 1179 hda_dsp_stream_free(sdev); 1180 1181 hda_bus_ml_free(sof_to_bus(sdev)); 1182 1183 iounmap(sdev->bar[HDA_DSP_BAR]); 1184 iounmap(bus->remap_addr); 1185 1186 sof_hda_bus_exit(sdev); 1187 1188 hda_codec_i915_exit(sdev); 1189 1190 return 0; 1191 } 1192 1193 int hda_power_down_dsp(struct snd_sof_dev *sdev) 1194 { 1195 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 1196 const struct sof_intel_dsp_desc *chip = hda->desc; 1197 1198 return hda_dsp_core_reset_power_down(sdev, chip->host_managed_cores_mask); 1199 } 1200 1201 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC) 1202 static void hda_generic_machine_select(struct snd_sof_dev *sdev, 1203 struct snd_soc_acpi_mach **mach) 1204 { 1205 struct hdac_bus *bus = sof_to_bus(sdev); 1206 struct snd_soc_acpi_mach_params *mach_params; 1207 struct snd_soc_acpi_mach *hda_mach; 1208 struct snd_sof_pdata *pdata = sdev->pdata; 1209 const char *tplg_filename; 1210 const char *idisp_str; 1211 int dmic_num = 0; 1212 int codec_num = 0; 1213 int ret; 1214 int i; 1215 1216 /* codec detection */ 1217 if (!bus->codec_mask) { 1218 dev_info(bus->dev, "no hda codecs found!\n"); 1219 } else { 1220 dev_info(bus->dev, "hda codecs found, mask %lx\n", 1221 bus->codec_mask); 1222 1223 for (i = 0; i < HDA_MAX_CODECS; i++) { 1224 if (bus->codec_mask & (1 << i)) 1225 codec_num++; 1226 } 1227 1228 /* 1229 * If no machine driver is found, then: 1230 * 1231 * generic hda machine driver can handle: 1232 * - one HDMI codec, and/or 1233 * - one external HDAudio codec 1234 */ 1235 if (!*mach && codec_num <= 2) { 1236 bool tplg_fixup; 1237 1238 hda_mach = snd_soc_acpi_intel_hda_machines; 1239 1240 dev_info(bus->dev, "using HDA machine driver %s now\n", 1241 hda_mach->drv_name); 1242 1243 if (codec_num == 1 && HDA_IDISP_CODEC(bus->codec_mask)) 1244 idisp_str = "-idisp"; 1245 else 1246 idisp_str = ""; 1247 1248 /* topology: use the info from hda_machines */ 1249 if (pdata->tplg_filename) { 1250 tplg_fixup = false; 1251 tplg_filename = pdata->tplg_filename; 1252 } else { 1253 tplg_fixup = true; 1254 tplg_filename = hda_mach->sof_tplg_filename; 1255 } 1256 ret = dmic_detect_topology_fixup(sdev, &tplg_filename, idisp_str, &dmic_num, 1257 tplg_fixup); 1258 if (ret < 0) 1259 return; 1260 1261 hda_mach->mach_params.dmic_num = dmic_num; 1262 pdata->tplg_filename = tplg_filename; 1263 1264 if (codec_num == 2) { 1265 /* 1266 * Prevent SoundWire links from starting when an external 1267 * HDaudio codec is used 1268 */ 1269 hda_mach->mach_params.link_mask = 0; 1270 } 1271 1272 *mach = hda_mach; 1273 } 1274 } 1275 1276 /* used by hda machine driver to create dai links */ 1277 if (*mach) { 1278 mach_params = &(*mach)->mach_params; 1279 mach_params->codec_mask = bus->codec_mask; 1280 mach_params->common_hdmi_codec_drv = true; 1281 } 1282 } 1283 #else 1284 static void hda_generic_machine_select(struct snd_sof_dev *sdev, 1285 struct snd_soc_acpi_mach **mach) 1286 { 1287 } 1288 #endif 1289 1290 #if IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE) 1291 1292 #define SDW_CODEC_ADR_MASK(_adr) ((_adr) & (SDW_DISCO_LINK_ID_MASK | SDW_VERSION_MASK | \ 1293 SDW_MFG_ID_MASK | SDW_PART_ID_MASK)) 1294 1295 /* Check if all Slaves defined on the link can be found */ 1296 static bool link_slaves_found(struct snd_sof_dev *sdev, 1297 const struct snd_soc_acpi_link_adr *link, 1298 struct sdw_intel_ctx *sdw) 1299 { 1300 struct hdac_bus *bus = sof_to_bus(sdev); 1301 struct sdw_intel_slave_id *ids = sdw->ids; 1302 int num_slaves = sdw->num_slaves; 1303 unsigned int part_id, link_id, unique_id, mfg_id, version; 1304 int i, j, k; 1305 1306 for (i = 0; i < link->num_adr; i++) { 1307 u64 adr = link->adr_d[i].adr; 1308 int reported_part_count = 0; 1309 1310 mfg_id = SDW_MFG_ID(adr); 1311 part_id = SDW_PART_ID(adr); 1312 link_id = SDW_DISCO_LINK_ID(adr); 1313 version = SDW_VERSION(adr); 1314 1315 for (j = 0; j < num_slaves; j++) { 1316 /* find out how many identical parts were reported on that link */ 1317 if (ids[j].link_id == link_id && 1318 ids[j].id.part_id == part_id && 1319 ids[j].id.mfg_id == mfg_id && 1320 ids[j].id.sdw_version == version) 1321 reported_part_count++; 1322 } 1323 1324 for (j = 0; j < num_slaves; j++) { 1325 int expected_part_count = 0; 1326 1327 if (ids[j].link_id != link_id || 1328 ids[j].id.part_id != part_id || 1329 ids[j].id.mfg_id != mfg_id || 1330 ids[j].id.sdw_version != version) 1331 continue; 1332 1333 /* find out how many identical parts are expected */ 1334 for (k = 0; k < link->num_adr; k++) { 1335 u64 adr2 = link->adr_d[k].adr; 1336 1337 if (SDW_CODEC_ADR_MASK(adr2) == SDW_CODEC_ADR_MASK(adr)) 1338 expected_part_count++; 1339 } 1340 1341 if (reported_part_count == expected_part_count) { 1342 /* 1343 * we have to check unique id 1344 * if there is more than one 1345 * Slave on the link 1346 */ 1347 unique_id = SDW_UNIQUE_ID(adr); 1348 if (reported_part_count == 1 || 1349 ids[j].id.unique_id == unique_id) { 1350 dev_dbg(bus->dev, "found %x at link %d\n", 1351 part_id, link_id); 1352 break; 1353 } 1354 } else { 1355 dev_dbg(bus->dev, "part %x reported %d expected %d on link %d, skipping\n", 1356 part_id, reported_part_count, expected_part_count, link_id); 1357 } 1358 } 1359 if (j == num_slaves) { 1360 dev_dbg(bus->dev, 1361 "Slave %x not found\n", 1362 part_id); 1363 return false; 1364 } 1365 } 1366 return true; 1367 } 1368 1369 static struct snd_soc_acpi_mach *hda_sdw_machine_select(struct snd_sof_dev *sdev) 1370 { 1371 struct snd_sof_pdata *pdata = sdev->pdata; 1372 const struct snd_soc_acpi_link_adr *link; 1373 struct snd_soc_acpi_mach *mach; 1374 struct sof_intel_hda_dev *hdev; 1375 u32 link_mask; 1376 int i; 1377 1378 hdev = pdata->hw_pdata; 1379 link_mask = hdev->info.link_mask; 1380 1381 /* 1382 * Select SoundWire machine driver if needed using the 1383 * alternate tables. This case deals with SoundWire-only 1384 * machines, for mixed cases with I2C/I2S the detection relies 1385 * on the HID list. 1386 */ 1387 if (link_mask) { 1388 for (mach = pdata->desc->alt_machines; 1389 mach && mach->link_mask; mach++) { 1390 /* 1391 * On some platforms such as Up Extreme all links 1392 * are enabled but only one link can be used by 1393 * external codec. Instead of exact match of two masks, 1394 * first check whether link_mask of mach is subset of 1395 * link_mask supported by hw and then go on searching 1396 * link_adr 1397 */ 1398 if (~link_mask & mach->link_mask) 1399 continue; 1400 1401 /* No need to match adr if there is no links defined */ 1402 if (!mach->links) 1403 break; 1404 1405 link = mach->links; 1406 for (i = 0; i < hdev->info.count && link->num_adr; 1407 i++, link++) { 1408 /* 1409 * Try next machine if any expected Slaves 1410 * are not found on this link. 1411 */ 1412 if (!link_slaves_found(sdev, link, hdev->sdw)) 1413 break; 1414 } 1415 /* Found if all Slaves are checked */ 1416 if (i == hdev->info.count || !link->num_adr) 1417 break; 1418 } 1419 if (mach && mach->link_mask) { 1420 int dmic_num = 0; 1421 bool tplg_fixup; 1422 const char *tplg_filename; 1423 1424 mach->mach_params.links = mach->links; 1425 mach->mach_params.link_mask = mach->link_mask; 1426 mach->mach_params.platform = dev_name(sdev->dev); 1427 1428 if (pdata->tplg_filename) { 1429 tplg_fixup = false; 1430 } else { 1431 tplg_fixup = true; 1432 tplg_filename = mach->sof_tplg_filename; 1433 } 1434 1435 /* 1436 * DMICs use up to 4 pins and are typically pin-muxed with SoundWire 1437 * link 2 and 3, or link 1 and 2, thus we only try to enable dmics 1438 * if all conditions are true: 1439 * a) 2 or fewer links are used by SoundWire 1440 * b) the NHLT table reports the presence of microphones 1441 */ 1442 if (hweight_long(mach->link_mask) <= 2) { 1443 int ret; 1444 1445 ret = dmic_detect_topology_fixup(sdev, &tplg_filename, "", 1446 &dmic_num, tplg_fixup); 1447 if (ret < 0) 1448 return NULL; 1449 } 1450 if (tplg_fixup) 1451 pdata->tplg_filename = tplg_filename; 1452 mach->mach_params.dmic_num = dmic_num; 1453 1454 dev_dbg(sdev->dev, 1455 "SoundWire machine driver %s topology %s\n", 1456 mach->drv_name, 1457 pdata->tplg_filename); 1458 1459 return mach; 1460 } 1461 1462 dev_info(sdev->dev, "No SoundWire machine driver found\n"); 1463 } 1464 1465 return NULL; 1466 } 1467 #else 1468 static struct snd_soc_acpi_mach *hda_sdw_machine_select(struct snd_sof_dev *sdev) 1469 { 1470 return NULL; 1471 } 1472 #endif 1473 1474 void hda_set_mach_params(struct snd_soc_acpi_mach *mach, 1475 struct snd_sof_dev *sdev) 1476 { 1477 struct snd_sof_pdata *pdata = sdev->pdata; 1478 const struct sof_dev_desc *desc = pdata->desc; 1479 struct snd_soc_acpi_mach_params *mach_params; 1480 1481 mach_params = &mach->mach_params; 1482 mach_params->platform = dev_name(sdev->dev); 1483 mach_params->num_dai_drivers = desc->ops->num_drv; 1484 mach_params->dai_drivers = desc->ops->drv; 1485 } 1486 1487 struct snd_soc_acpi_mach *hda_machine_select(struct snd_sof_dev *sdev) 1488 { 1489 struct snd_sof_pdata *sof_pdata = sdev->pdata; 1490 const struct sof_dev_desc *desc = sof_pdata->desc; 1491 struct snd_soc_acpi_mach *mach; 1492 const char *tplg_filename; 1493 1494 mach = snd_soc_acpi_find_machine(desc->machines); 1495 if (mach) { 1496 bool add_extension = false; 1497 bool tplg_fixup = false; 1498 1499 /* 1500 * If tplg file name is overridden, use it instead of 1501 * the one set in mach table 1502 */ 1503 if (!sof_pdata->tplg_filename) { 1504 sof_pdata->tplg_filename = mach->sof_tplg_filename; 1505 tplg_fixup = true; 1506 } 1507 1508 /* report to machine driver if any DMICs are found */ 1509 mach->mach_params.dmic_num = check_dmic_num(sdev); 1510 1511 if (tplg_fixup && 1512 mach->tplg_quirk_mask & SND_SOC_ACPI_TPLG_INTEL_DMIC_NUMBER && 1513 mach->mach_params.dmic_num) { 1514 tplg_filename = devm_kasprintf(sdev->dev, GFP_KERNEL, 1515 "%s%s%d%s", 1516 sof_pdata->tplg_filename, 1517 "-dmic", 1518 mach->mach_params.dmic_num, 1519 "ch"); 1520 if (!tplg_filename) 1521 return NULL; 1522 1523 sof_pdata->tplg_filename = tplg_filename; 1524 add_extension = true; 1525 } 1526 1527 if (mach->link_mask) { 1528 mach->mach_params.links = mach->links; 1529 mach->mach_params.link_mask = mach->link_mask; 1530 } 1531 1532 /* report SSP link mask to machine driver */ 1533 mach->mach_params.i2s_link_mask = check_nhlt_ssp_mask(sdev); 1534 1535 if (tplg_fixup && 1536 mach->tplg_quirk_mask & SND_SOC_ACPI_TPLG_INTEL_SSP_NUMBER && 1537 mach->mach_params.i2s_link_mask) { 1538 const struct sof_intel_dsp_desc *chip = get_chip_info(sdev->pdata); 1539 int ssp_num; 1540 int mclk_mask; 1541 1542 if (hweight_long(mach->mach_params.i2s_link_mask) > 1 && 1543 !(mach->tplg_quirk_mask & SND_SOC_ACPI_TPLG_INTEL_SSP_MSB)) 1544 dev_warn(sdev->dev, "More than one SSP exposed by NHLT, choosing MSB\n"); 1545 1546 /* fls returns 1-based results, SSPs indices are 0-based */ 1547 ssp_num = fls(mach->mach_params.i2s_link_mask) - 1; 1548 1549 if (ssp_num >= chip->ssp_count) { 1550 dev_err(sdev->dev, "Invalid SSP %d, max on this platform is %d\n", 1551 ssp_num, chip->ssp_count); 1552 return NULL; 1553 } 1554 1555 tplg_filename = devm_kasprintf(sdev->dev, GFP_KERNEL, 1556 "%s%s%d", 1557 sof_pdata->tplg_filename, 1558 "-ssp", 1559 ssp_num); 1560 if (!tplg_filename) 1561 return NULL; 1562 1563 sof_pdata->tplg_filename = tplg_filename; 1564 add_extension = true; 1565 1566 mclk_mask = check_nhlt_ssp_mclk_mask(sdev, ssp_num); 1567 1568 if (mclk_mask < 0) { 1569 dev_err(sdev->dev, "Invalid MCLK configuration\n"); 1570 return NULL; 1571 } 1572 1573 dev_dbg(sdev->dev, "MCLK mask %#x found in NHLT\n", mclk_mask); 1574 1575 if (mclk_mask) { 1576 dev_info(sdev->dev, "Overriding topology with MCLK mask %#x from NHLT\n", mclk_mask); 1577 sdev->mclk_id_override = true; 1578 sdev->mclk_id_quirk = (mclk_mask & BIT(0)) ? 0 : 1; 1579 } 1580 } 1581 1582 if (tplg_fixup && add_extension) { 1583 tplg_filename = devm_kasprintf(sdev->dev, GFP_KERNEL, 1584 "%s%s", 1585 sof_pdata->tplg_filename, 1586 ".tplg"); 1587 if (!tplg_filename) 1588 return NULL; 1589 1590 sof_pdata->tplg_filename = tplg_filename; 1591 } 1592 1593 /* check if mclk_id should be modified from topology defaults */ 1594 if (mclk_id_override >= 0) { 1595 dev_info(sdev->dev, "Overriding topology with MCLK %d from kernel_parameter\n", mclk_id_override); 1596 sdev->mclk_id_override = true; 1597 sdev->mclk_id_quirk = mclk_id_override; 1598 } 1599 } 1600 1601 /* 1602 * If I2S fails, try SoundWire 1603 */ 1604 if (!mach) 1605 mach = hda_sdw_machine_select(sdev); 1606 1607 /* 1608 * Choose HDA generic machine driver if mach is NULL. 1609 * Otherwise, set certain mach params. 1610 */ 1611 hda_generic_machine_select(sdev, &mach); 1612 if (!mach) 1613 dev_warn(sdev->dev, "warning: No matching ASoC machine driver found\n"); 1614 1615 return mach; 1616 } 1617 1618 int hda_pci_intel_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) 1619 { 1620 int ret; 1621 1622 ret = snd_intel_dsp_driver_probe(pci); 1623 if (ret != SND_INTEL_DSP_DRIVER_ANY && ret != SND_INTEL_DSP_DRIVER_SOF) { 1624 dev_dbg(&pci->dev, "SOF PCI driver not selected, aborting probe\n"); 1625 return -ENODEV; 1626 } 1627 1628 return sof_pci_probe(pci, pci_id); 1629 } 1630 EXPORT_SYMBOL_NS(hda_pci_intel_probe, SND_SOC_SOF_INTEL_HDA_COMMON); 1631 1632 int hda_register_clients(struct snd_sof_dev *sdev) 1633 { 1634 return hda_probes_register(sdev); 1635 } 1636 1637 void hda_unregister_clients(struct snd_sof_dev *sdev) 1638 { 1639 hda_probes_unregister(sdev); 1640 } 1641 1642 MODULE_LICENSE("Dual BSD/GPL"); 1643 MODULE_IMPORT_NS(SND_SOC_SOF_PCI_DEV); 1644 MODULE_IMPORT_NS(SND_SOC_SOF_HDA_AUDIO_CODEC); 1645 MODULE_IMPORT_NS(SND_SOC_SOF_HDA_AUDIO_CODEC_I915); 1646 MODULE_IMPORT_NS(SND_SOC_SOF_XTENSA); 1647 MODULE_IMPORT_NS(SND_INTEL_SOUNDWIRE_ACPI); 1648 MODULE_IMPORT_NS(SOUNDWIRE_INTEL_INIT); 1649 MODULE_IMPORT_NS(SOUNDWIRE_INTEL); 1650